123 lines
3.1 KiB
Rust
123 lines
3.1 KiB
Rust
//! # GPIO register module.
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#[bitbybit::bitfield(u32, default = 0x0)]
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#[derive(Debug)]
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pub struct MaskedOutput {
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#[bits(16..=31, w)]
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mask: u16,
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#[bits(0..=15, rw)]
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output: u16,
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}
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#[derive(derive_mmio::Mmio)]
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#[repr(C)]
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pub struct BankControlRegisters {
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/// Direction mode
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dirm: u32,
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/// Output enable
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out_en: u32,
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/// Interrupt mask status
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#[mmio(PureRead)]
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int_mask: u32,
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/// Interrupt enable/unmask
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#[mmio(Write)]
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int_en: u32,
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/// Interrupt disable/mask
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#[mmio(Write)]
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int_dis: u32,
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/// Interrupt status
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#[mmio(PureRead, Write)]
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int_sts: u32,
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/// Interrupt type
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int_type: u32,
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/// Interrupt polarity
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int_pol: u32,
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/// Interrupt any edge sensitivity
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int_any: u32,
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}
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/// GPIO register access.
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#[derive(derive_mmio::Mmio)]
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#[repr(C)]
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pub struct Registers {
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/// Maskable output data (GPIO bank 0, MIO, lower 16 bits)
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masked_out_0_lsw: MaskedOutput,
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/// Maskable output data (GPIO bank 0, MIO, upper 16 bits)
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masked_out_0_msw: MaskedOutput,
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/// Maskable output data (GPIO bank 1, MIO, lower 16 bits)
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masked_out_1_lsw: MaskedOutput,
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/// Maskable output data (GPIO bank 1, MIO, upper 16 bits)
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masked_out_1_msw: MaskedOutput,
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/// Maskable output data (GPIO bank 2, EMIO, lower 16 bits)
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masked_out_2_lsw: MaskedOutput,
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/// Maskable output data (GPIO bank 2, EMIO, upper 16 bits)
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masked_out_2_msw: MaskedOutput,
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/// Maskable output data (GPIO bank 3, EMIO, lower 16 bits)
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masked_out_3_lsw: MaskedOutput,
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/// Maskable output data (GPIO bank 3, EMIO, upper 16 bits)
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masked_out_3_msw: MaskedOutput,
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_reserved_0: [u32; 8],
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/// Output data (GPIO bank 0, MIO)
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out_0: u32,
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/// Output data (GPIO bank 1, MIO)
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out_1: u32,
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/// Output data (GPIO bank 2, EMIO)
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out_2: u32,
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/// Output data (GPIO bank 3, EMIO)
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out_3: u32,
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_reserved_1: [u32; 4],
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/// Input data (GPIO bank 0, MIO)
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#[mmio(PureRead)]
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in_0: u32,
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/// Input data (GPIO bank 1, MIO)
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#[mmio(PureRead)]
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in_1: u32,
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/// Input data (GPIO bank 2, EMIO)
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#[mmio(PureRead)]
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in_2: u32,
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/// Input data (GPIO bank 3, EMIO)
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#[mmio(PureRead)]
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in_3: u32,
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_reserved_2: [u32; 101],
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#[mmio(Inner)]
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bank_0: BankControlRegisters,
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_reserved_3: [u32; 7],
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#[mmio(Inner)]
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bank_1: BankControlRegisters,
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_reserved_4: [u32; 7],
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#[mmio(Inner)]
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bank_2: BankControlRegisters,
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_reserved_5: [u32; 7],
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#[mmio(Inner)]
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bank_3: BankControlRegisters,
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}
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static_assertions::const_assert_eq!(core::mem::size_of::<Registers>(), 0x2E8);
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impl Registers {
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/// Create a new XGPIOPS GPIO MMIO instance.
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///
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/// # Safety
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///
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/// This API can be used to potentially create a driver to the same peripheral structure
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/// from multiple threads. The user must ensure that concurrent accesses are safe and do not
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/// interfere with each other.
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pub const unsafe fn new_mmio_fixed() -> MmioRegisters<'static> {
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MmioRegisters {
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ptr: 0xE000A000 as *mut Registers,
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phantom: core::marker::PhantomData,
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}
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}
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}
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