this works with q7s and new sus

This commit is contained in:
2021-05-09 14:39:56 +02:00
parent 95f09469d1
commit 07d337c6ad
3 changed files with 18 additions and 6 deletions

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@ -19,7 +19,7 @@ namespace SUS {
* power on.
*
* @note Bit1 (DIFFSEL1) - Bit0 (DIFFSEL0): 0b00, No byte is following the setup byte
* Bit3 (REFSEL1) - Bit2 (REFSEL0): 0b00, internal reference, needs wake-up delay
* Bit3 (REFSEL1) - Bit2 (REFSEL0): 0b10, internal reference, no wake-up delay
* Bit5 (CLKSEL1) - Bit4 (CLKSEL0): 0b11, MAX1227 clocked through SPI SCLK
* Bit7 - Bit6: 0b01, tells MAX1227 that this is the setup register
*
@ -41,6 +41,7 @@ namespace SUS {
static const uint8_t CONVERT_DIFF_CHANNEL_2 = 0b10010110;
static const uint8_t CONVERT_DIFF_CHANNEL_3 = 0b10011110;
static const uint8_t CONVERT_DIFF_CHANNEL_4 = 0b10100110;
static const uint8_t CONVERT_DIFF_CHANNEL_5 = 0b10101110;
static const uint8_t RESET_FIFO = 0b00011000;