another try
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@ -61,15 +61,15 @@ git submodule update
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3. Open Xilinx SDK 2018.2
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3. Open Xilinx SDK 2018.2
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4. Import project
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4. Import project
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* File → Import → C/C++ → Existing Code as Makefile Project
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* File → Import → C/C++ → Existing Code as Makefile Project
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5. Set build command. Replace <target> with either debug or release.
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5. Set build command. Replace \<target\> with either debug or release.
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* When on Linux right click project → Properties → C/C++ Build → Set build command to make <target> -j
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* When on Linux right click project → Properties → C/C++ Build → Set build command to make \<target\> -j
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* -j causes the compiler to use all available cores
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* -j causes the compiler to use all available cores
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* On windows create a make target (Windows → Show View → Make Target)
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* On windows create a make target (Windows → Show View → Make Target)
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* Right click eive_obsw → New
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* Right click eive_obsw → New
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* Target name: all
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* Target name: all
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* Uncheck "Same as the target name"
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* Uncheck "Same as the target name"
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* Uncheck "Use builder settings"
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* Uncheck "Use builder settings"
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* As build command type: `make -j <target> WINDOWS=1`
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* As build command type: `make -j \<target\> WINDOWS=1`
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6. Run build command (double click the generated target)
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6. Run build command (double click the generated target)
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## Debugging the software (when workstation is directly conncected to Q7S)
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## Debugging the software (when workstation is directly conncected to Q7S)
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