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@ -163,8 +163,8 @@ void ObjectFactory::produce(void* args) {
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#if OBSW_ADD_CCSDS_IP_CORES == 1
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CcsdsIpCoreHandler* ipCoreHandler = nullptr;
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CcsdsComponentArgs ccsdsArgs(*gpioComIF, *ipcStore, *tmStore, stores, *pusFunnel, *cfdpFunnel,
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&ipCoreHandler);
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createCcsdsIpComponentsAddTmRouting(ccsdsArgs);
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&ipCoreHandler, 0, 0);
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createCcsdsIpComponentsWrapper(ccsdsArgs);
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#endif /* OBSW_ADD_CCSDS_IP_CORES == 1 */
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/* Test Task */
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@ -115,8 +115,8 @@ void ObjectFactory::produce(void* args) {
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#if OBSW_ADD_CCSDS_IP_CORES == 1
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CcsdsIpCoreHandler* ipCoreHandler = nullptr;
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CcsdsComponentArgs ccsdsArgs(*gpioComIF, *ipcStore, *tmStore, stores, *pusFunnel, *cfdpFunnel,
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&ipCoreHandler);
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createCcsdsIpComponentsAddTmRouting(ccsdsArgs);
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&ipCoreHandler, 0, 0);
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createCcsdsIpComponentsWrapper(ccsdsArgs);
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#endif /* OBSW_ADD_CCSDS_IP_CORES == 1 */
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#if OBSW_ADD_SCEX_DEVICE == 1
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@ -834,9 +834,9 @@ ReturnValue_t ObjectFactory::createCcsdsComponents(CcsdsComponentArgs& args) {
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uioNames.configMemory = q7s::UIO_PDEC_CONFIG_MEMORY;
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uioNames.ramMemory = q7s::UIO_PDEC_RAM;
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uioNames.registers = q7s::UIO_PDEC_REGISTERS;
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uioNames.irq = q7s::UIO_PDEC_IRQ;
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uint32_t cfgMemAddr = config::pdec::PDEC_CONFIG_BASE_ADDR_LEGACY;
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new PdecHandler(objects::PDEC_HANDLER, objects::CCSDS_HANDLER, &args.gpioComIF,
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gpioIds::PDEC_RESET, uioNames);
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gpioIds::PDEC_RESET, uioNames, args.pdecCfgMemBaseAddr, args.pdecRamBaseAddr);
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GpioCookie* gpioRS485Chip = new GpioCookie;
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gpio = new GpiodRegularByLineName(q7s::gpioNames::RS485_EN_TX_CLOCK, "RS485 Transceiver",
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Direction::OUT, Levels::LOW);
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@ -1062,7 +1062,13 @@ ReturnValue_t ObjectFactory::readFirmwareVersion() {
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return returnvalue::OK;
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}
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ReturnValue_t ObjectFactory::createCcsdsIpComponentsAddTmRouting(CcsdsComponentArgs& ccsdsArgs) {
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ReturnValue_t ObjectFactory::createCcsdsIpComponentsWrapper(CcsdsComponentArgs& ccsdsArgs) {
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ccsdsArgs.pdecCfgMemBaseAddr = config::pdec::PDEC_CONFIG_BASE_ADDR;
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ccsdsArgs.pdecRamBaseAddr = config::pdec::PDEC_RAM_ADDR;
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if (core::FW_VERSION_MAJOR < 6) {
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ccsdsArgs.pdecCfgMemBaseAddr = config::pdec::PDEC_CONFIG_BASE_ADDR_LEGACY;
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ccsdsArgs.pdecRamBaseAddr = config::pdec::PDEC_RAM_ADDR_LEGACY;
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}
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ReturnValue_t result = createCcsdsComponents(ccsdsArgs);
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#if OBSW_TM_TO_PTME == 1
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if (ccsdsArgs.normalLiveTmDest != MessageQueueIF::NO_QUEUE) {
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@ -31,14 +31,17 @@ namespace ObjectFactory {
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struct CcsdsComponentArgs {
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CcsdsComponentArgs(LinuxLibgpioIF& gpioIF, StorageManagerIF& ipcStore, StorageManagerIF& tmStore,
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PersistentTmStores& stores, PusTmFunnel& pusFunnel, CfdpTmFunnel& cfdpFunnel,
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CcsdsIpCoreHandler** ipCoreHandler)
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CcsdsIpCoreHandler** ipCoreHandler, uint32_t pdecCfgMemBaseAddr,
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uint32_t pdecRamBaseAddr)
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: gpioComIF(gpioIF),
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ipcStore(ipcStore),
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tmStore(tmStore),
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stores(stores),
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pusFunnel(pusFunnel),
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cfdpFunnel(cfdpFunnel),
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ipCoreHandler(ipCoreHandler) {}
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ipCoreHandler(ipCoreHandler),
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pdecCfgMemBaseAddr(pdecCfgMemBaseAddr),
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pdecRamBaseAddr(pdecRamBaseAddr) {}
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LinuxLibgpioIF& gpioComIF;
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StorageManagerIF& ipcStore;
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StorageManagerIF& tmStore;
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@ -46,6 +49,8 @@ struct CcsdsComponentArgs {
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PusTmFunnel& pusFunnel;
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CfdpTmFunnel& cfdpFunnel;
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CcsdsIpCoreHandler** ipCoreHandler;
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uint32_t pdecCfgMemBaseAddr;
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uint32_t pdecRamBaseAddr;
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MessageQueueId_t normalLiveTmDest = MessageQueueIF::NO_QUEUE;
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MessageQueueId_t cfdpLiveTmDest = MessageQueueIF::NO_QUEUE;
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};
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@ -75,7 +80,7 @@ void createSolarArrayDeploymentComponents(PowerSwitchIF& pwrSwitcher, GpioIF& gp
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void createSyrlinksComponents(PowerSwitchIF* pwrSwitcher);
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void createPayloadComponents(LinuxLibgpioIF* gpioComIF, PowerSwitchIF& pwrSwitcher);
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void createReactionWheelComponents(LinuxLibgpioIF* gpioComIF, PowerSwitchIF* pwrSwitcher);
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ReturnValue_t createCcsdsIpComponentsAddTmRouting(CcsdsComponentArgs& args);
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ReturnValue_t createCcsdsIpComponentsWrapper(CcsdsComponentArgs& args);
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ReturnValue_t createCcsdsComponents(CcsdsComponentArgs& args);
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ReturnValue_t readFirmwareVersion();
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void createMiscComponents();
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@ -116,8 +116,17 @@ static constexpr float SCHED_BLOCK_10_PERIOD =
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} // namespace spiSched
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namespace pdec {
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// Pre FW v6.0.0
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static constexpr uint32_t PDEC_CONFIG_BASE_ADDR_LEGACY = 0x24000000;
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}
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static constexpr uint32_t PDEC_RAM_ADDR_LEGACY = 0x26000000;
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// Post FW v6.0.0
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static constexpr uint32_t PDEC_CONFIG_BASE_ADDR = 0x4000000;
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static constexpr uint32_t PDEC_RAM_ADDR = 0x7000000;
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} // namespace pdec
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} // namespace config
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#endif /* COMMON_CONFIG_DEFINITIONS_H_ */
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@ -52,9 +52,9 @@ class PdecHandler : public SystemObject,
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public:
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static constexpr dur_millis_t IRQ_TIMEOUT_MS = 500;
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static constexpr uint32_t PDEC_CFG_MEM_SIZE = 0x1000;
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//static constexpr uint32_t PDEC_CFG_MEM_PHY_ADDR = 0x24000000;
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// static constexpr uint32_t PDEC_CFG_MEM_PHY_ADDR = 0x24000000;
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static constexpr uint32_t PDEC_RAM_SIZE = 0x10000;
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//static constexpr uint32_t PDEC_RAM_PHY_ADDR = 0x26000000;
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// static constexpr uint32_t PDEC_RAM_PHY_ADDR = 0x26000000;
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enum class Modes { POLLED, IRQ };
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2
tmtc
2
tmtc
@ -1 +1 @@
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Subproject commit 8f8bcde90e3b9113388cfedc47775426888d0781
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Subproject commit 97f99415d6be40d35bf9c373fea40b41c8457386
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