add some baseline defines and config values
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@ -31,3 +31,8 @@ uint32_t PdecConfig::getConfigWord(uint8_t wordNo) {
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}
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}
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return configWords[wordNo];
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return configWords[wordNo];
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}
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}
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uint32_t PdecConfig::getImrReg() {
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return static_cast<uint32_t>(enableNewFarIrq << 2) | static_cast<uint32_t>(enableTcAbortIrq << 1)
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| static_cast<uint32_t>(enableTcNewIrq);
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}
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@ -23,6 +23,7 @@ class PdecConfig {
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* @brief Returns the configuration word by specifying the position.
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* @brief Returns the configuration word by specifying the position.
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*/
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*/
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uint32_t getConfigWord(uint8_t wordNo);
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uint32_t getConfigWord(uint8_t wordNo);
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uint32_t getImrReg();
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private:
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private:
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// TC transfer frame configuration parameters
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// TC transfer frame configuration parameters
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@ -45,6 +46,9 @@ class PdecConfig {
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static const uint8_t CONFIG_WORDS_NUM = 2;
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static const uint8_t CONFIG_WORDS_NUM = 2;
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uint32_t configWords[CONFIG_WORDS_NUM];
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uint32_t configWords[CONFIG_WORDS_NUM];
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bool enableTcNewIrq = true;
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bool enableTcAbortIrq = true;
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bool enableNewFarIrq = true;
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void initialize();
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void initialize();
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};
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};
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@ -86,10 +86,12 @@ void PdecHandler::writePdecConfig() {
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*(memoryBaseAddress + FRAME_HEADER_OFFSET) = pdecConfig.getConfigWord(0);
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*(memoryBaseAddress + FRAME_HEADER_OFFSET) = pdecConfig.getConfigWord(0);
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*(memoryBaseAddress + FRAME_HEADER_OFFSET + 1) = pdecConfig.getConfigWord(1);
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*(memoryBaseAddress + FRAME_HEADER_OFFSET + 1) = pdecConfig.getConfigWord(1);
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// Configure interrupt mask register to enable interrupts
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(*memoryBaseAddress + PDEC_IMR_OFFSET) = pdecConfig.getImrReg();
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// Configure all MAP IDs as invalid
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// Configure all MAP IDs as invalid
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for (int idx = 0; idx <= MAX_MAP_ADDR; idx += 4) {
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for (int idx = 0; idx <= MAX_MAP_ADDR; idx += 4) {
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// TODO: adding 1 / 4 results in + 0. Check correctness
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*(memoryBaseAddress + MAP_ADDR_LUT_OFFSET + idx / 4) =
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*(memoryBaseAddress + MAP_ADDR_LUT_OFFSET + idx + 1 / 4) =
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NO_DESTINATION << 24 | NO_DESTINATION << 16 | NO_DESTINATION << 8 | NO_DESTINATION;
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NO_DESTINATION << 24 | NO_DESTINATION << 16 | NO_DESTINATION << 8 | NO_DESTINATION;
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}
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}
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@ -100,10 +102,10 @@ void PdecHandler::writePdecConfig() {
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// Write map id clock frequencies
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// Write map id clock frequencies
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for (int idx = 0; idx <= MAX_MAP_ADDR; idx += 4) {
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for (int idx = 0; idx <= MAX_MAP_ADDR; idx += 4) {
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// TODO: adding 1 / 4 results in + 0. Check correctness
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*(memoryBaseAddress + MAP_CLK_FREQ_OFFSET + idx / 4) =
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*(memoryBaseAddress + MAP_CLK_FREQ_OFFSET + idx / 4) =
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MAP_CLK_FREQ << 24 | MAP_CLK_FREQ << 16 | MAP_CLK_FREQ << 8 | MAP_CLK_FREQ;
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MAP_CLK_FREQ << 24 | MAP_CLK_FREQ << 16 | MAP_CLK_FREQ << 8 | MAP_CLK_FREQ;
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}
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}
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}
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}
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ReturnValue_t PdecHandler::resetFarStatFlag() {
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ReturnValue_t PdecHandler::resetFarStatFlag() {
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@ -147,6 +147,8 @@ class PdecHandler : public SystemObject, public ExecutableObjectIF, public HasAc
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* UIO is 4 byte aligned. Thus offset is calculated with "true offset" / 4
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* UIO is 4 byte aligned. Thus offset is calculated with "true offset" / 4
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* Example: PDEC_FAR = 0x2840 => Offset in virtual address space is 0xA10
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* Example: PDEC_FAR = 0x2840 => Offset in virtual address space is 0xA10
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*/
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*/
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static constexpr uint32_t PDEC_PIR_OFFSET = 0xA03;
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static constexpr uint32_t PDEC_IMR_OFFSET = 0xA04;
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static const uint32_t PDEC_FAR_OFFSET = 0xA10;
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static const uint32_t PDEC_FAR_OFFSET = 0xA10;
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static const uint32_t PDEC_CLCW_OFFSET = 0xA12;
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static const uint32_t PDEC_CLCW_OFFSET = 0xA12;
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static const uint32_t PDEC_BFREE_OFFSET = 0xA24;
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static const uint32_t PDEC_BFREE_OFFSET = 0xA24;
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