ploc components now compile for hosted (linux)
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@ -1,11 +1,12 @@
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#ifndef COMMON_CONFIG_DEVCONF_H_
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#define COMMON_CONFIG_DEVCONF_H_
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#include <fsfw_hal/linux/serial/SerialCookie.h>
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#include <cstdint>
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#include "fsfw/timemanager/clockDefinitions.h"
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#include "fsfw_hal/linux/spi/spiDefinitions.h"
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#include "fsfw_hal/linux/uart/UartCookie.h"
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/**
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* SPI configuration will be contained here to let the device handlers remain independent
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87
common/config/devices/addresses.h
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87
common/config/devices/addresses.h
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#ifndef FSFWCONFIG_DEVICES_ADDRESSES_H_
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#define FSFWCONFIG_DEVICES_ADDRESSES_H_
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#include <fsfw/devicehandlers/CookieIF.h>
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#include <cstdint>
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#include "objects/systemObjectList.h"
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namespace addresses {
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/* Logical addresses have uint32_t datatype */
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enum logicalAddresses : address_t {
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PCDU,
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MGM_0_LIS3 = objects::MGM_0_LIS3_HANDLER,
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MGM_1_RM3100 = objects::MGM_1_RM3100_HANDLER,
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MGM_2_LIS3 = objects::MGM_2_LIS3_HANDLER,
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MGM_3_RM3100 = objects::MGM_3_RM3100_HANDLER,
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GYRO_0_ADIS = objects::GYRO_0_ADIS_HANDLER,
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GYRO_1_L3G = objects::GYRO_1_L3G_HANDLER,
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GYRO_2_ADIS = objects::GYRO_2_ADIS_HANDLER,
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GYRO_3_L3G = objects::GYRO_3_L3G_HANDLER,
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RAD_SENSOR = objects::RAD_SENSOR,
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SUS_0 = objects::SUS_0_N_LOC_XFYFZM_PT_XF,
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SUS_1 = objects::SUS_1_N_LOC_XBYFZM_PT_XB,
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SUS_2 = objects::SUS_2_N_LOC_XFYBZB_PT_YB,
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SUS_3 = objects::SUS_3_N_LOC_XFYBZF_PT_YF,
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SUS_4 = objects::SUS_4_N_LOC_XMYFZF_PT_ZF,
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SUS_5 = objects::SUS_5_N_LOC_XFYMZB_PT_ZB,
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SUS_6 = objects::SUS_6_R_LOC_XFYBZM_PT_XF,
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SUS_7 = objects::SUS_7_R_LOC_XBYBZM_PT_XB,
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SUS_8 = objects::SUS_8_R_LOC_XBYBZB_PT_YB,
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SUS_9 = objects::SUS_9_R_LOC_XBYBZB_PT_YF,
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SUS_10 = objects::SUS_10_N_LOC_XMYBZF_PT_ZF,
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SUS_11 = objects::SUS_11_R_LOC_XBYMZB_PT_ZB,
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/* Dummy and Test Addresses */
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DUMMY_ECHO = 129,
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DUMMY_GPS0 = 130,
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DUMMY_GPS1 = 131,
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};
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enum i2cAddresses : address_t {
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BPX_BATTERY = 0x07,
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IMTQ = 0x10,
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TMP1075_TCS_1 = 0x48,
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TMP1075_TCS_2 = 0x49,
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};
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enum spiAddresses : address_t {
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RTD_IC_3,
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RTD_IC_4,
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RTD_IC_5,
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RTD_IC_6,
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RTD_IC_7,
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RTD_IC_8,
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RTD_IC_9,
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RTD_IC_10,
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RTD_IC_11,
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RTD_IC_12,
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RTD_IC_13,
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RTD_IC_14,
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RTD_IC_15,
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RTD_IC_16,
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RTD_IC_17,
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RTD_IC_18,
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RW1,
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RW2,
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RW3,
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RW4,
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PLPCDU_ADC
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};
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/* Addresses of devices supporting the CSP protocol */
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enum cspAddresses : uint8_t {
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P60DOCK = 4,
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ACU = 2,
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PDU1 = 3,
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/* PDU2 occupies X4 slot of P60Dock */
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PDU2 = 6
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};
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} // namespace addresses
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#endif /* FSFWCONFIG_DEVICES_ADDRESSES_H_ */
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@ -16,6 +16,10 @@ enum commonObjects : uint32_t {
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PDEC_HANDLER = 0x50000700,
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CCSDS_HANDLER = 0x50000800,
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/* 0x49 ('I') for Communication Interfaces **/
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UART_COM_IF = 0x49030003,
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SCEX_UART_READER = 0x49010006,
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/* 0x43 ('C') for Controllers */
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THERMAL_CONTROLLER = 0x43400001,
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ACS_CONTROLLER = 0x43000002,
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