v1.16.0 #323
@ -33,6 +33,6 @@ uint32_t PdecConfig::getConfigWord(uint8_t wordNo) {
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}
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}
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uint32_t PdecConfig::getImrReg() {
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uint32_t PdecConfig::getImrReg() {
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return static_cast<uint32_t>(enableNewFarIrq << 2) | static_cast<uint32_t>(enableTcAbortIrq << 1)
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return static_cast<uint32_t>(enableNewFarIrq << 2) |
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| static_cast<uint32_t>(enableTcNewIrq);
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static_cast<uint32_t>(enableTcAbortIrq << 1) | static_cast<uint32_t>(enableTcNewIrq);
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}
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}
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@ -78,63 +78,16 @@ ReturnValue_t PdecHandler::initialize() {
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return returnvalue::OK;
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return returnvalue::OK;
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}
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}
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MessageQueueId_t PdecHandler::getCommandQueue() const { return commandQueue->getId(); }
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void PdecHandler::writePdecConfig() {
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PdecConfig pdecConfig;
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*(memoryBaseAddress + FRAME_HEADER_OFFSET) = pdecConfig.getConfigWord(0);
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*(memoryBaseAddress + FRAME_HEADER_OFFSET + 1) = pdecConfig.getConfigWord(1);
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// Configure interrupt mask register to enable interrupts
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*(memoryBaseAddress + PDEC_IMR_OFFSET) = pdecConfig.getImrReg();
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// Configure all MAP IDs as invalid
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for (int idx = 0; idx <= MAX_MAP_ADDR; idx += 4) {
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*(memoryBaseAddress + MAP_ADDR_LUT_OFFSET + idx / 4) =
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NO_DESTINATION << 24 | NO_DESTINATION << 16 | NO_DESTINATION << 8 | NO_DESTINATION;
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}
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// All TCs with MAP ID 7 will be routed to the PM module (can then be read from memory)
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uint8_t routeToPm = calcMapAddrEntry(PM_BUFFER);
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*(memoryBaseAddress + MAP_ADDR_LUT_OFFSET + 1) =
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(NO_DESTINATION << 24) | (NO_DESTINATION << 16) | (NO_DESTINATION << 8) | routeToPm;
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// Write map id clock frequencies
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for (int idx = 0; idx <= MAX_MAP_ADDR; idx += 4) {
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*(memoryBaseAddress + MAP_CLK_FREQ_OFFSET + idx / 4) =
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MAP_CLK_FREQ << 24 | MAP_CLK_FREQ << 16 | MAP_CLK_FREQ << 8 | MAP_CLK_FREQ;
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}
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}
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ReturnValue_t PdecHandler::resetFarStatFlag() {
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uint32_t pdecFar = *(registerBaseAddress + PDEC_FAR_OFFSET);
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if (pdecFar != FAR_RESET) {
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sif::warning << "PdecHandler::resetFarStatFlag: FAR register did not match expected value."
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<< " Read value: 0x" << std::hex << static_cast<unsigned int>(pdecFar)
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<< std::endl;
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return returnvalue::FAILED;
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}
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#if OBSW_DEBUG_PDEC_HANDLER == 1
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sif::debug << "PdecHandler::resetFarStatFlag: read FAR with value: 0x" << std::hex << pdecFar
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<< std::endl;
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#endif /* OBSW_DEBUG_PDEC_HANDLER == 1 */
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return returnvalue::OK;
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}
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ReturnValue_t PdecHandler::releasePdec() {
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ReturnValue_t result = returnvalue::OK;
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result = gpioComIF->pullHigh(pdecReset);
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if (result != returnvalue::OK) {
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sif::error << "PdecHandler::releasePdec: Failed to release PDEC reset signal" << std::endl;
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}
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return result;
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}
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ReturnValue_t PdecHandler::performOperation(uint8_t operationCode) {
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ReturnValue_t PdecHandler::performOperation(uint8_t operationCode) {
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ReturnValue_t result = returnvalue::OK;
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ReturnValue_t result = returnvalue::OK;
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if (OP_MODE == Modes::POLLED) {
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polledOperation();
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} else if (OP_MODE == Modes::IRQ) {
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irqOperation();
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}
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}
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ReturnValue_t PdecHandler::polledOperation() {
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readCommandQueue();
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readCommandQueue();
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switch (state) {
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switch (state) {
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@ -164,6 +117,13 @@ ReturnValue_t PdecHandler::performOperation(uint8_t operationCode) {
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return returnvalue::OK;
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return returnvalue::OK;
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}
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}
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ReturnValue_t PdecHandler::irqOperation() {
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while (true) {
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readCommandQueue();
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}
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return returnvalue::OK;
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}
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void PdecHandler::readCommandQueue(void) {
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void PdecHandler::readCommandQueue(void) {
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CommandMessage commandMessage;
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CommandMessage commandMessage;
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ReturnValue_t result = returnvalue::FAILED;
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ReturnValue_t result = returnvalue::FAILED;
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@ -181,6 +141,61 @@ void PdecHandler::readCommandQueue(void) {
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}
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}
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}
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}
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MessageQueueId_t PdecHandler::getCommandQueue() const { return commandQueue->getId(); }
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void PdecHandler::writePdecConfig() {
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PdecConfig pdecConfig;
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*(memoryBaseAddress + FRAME_HEADER_OFFSET) = pdecConfig.getConfigWord(0);
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*(memoryBaseAddress + FRAME_HEADER_OFFSET + 1) = pdecConfig.getConfigWord(1);
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if (OP_MODE == Modes::IRQ) {
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// Configure interrupt mask register to enable interrupts
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*(memoryBaseAddress + PDEC_IMR_OFFSET) = pdecConfig.getImrReg();
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}
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// Configure all MAP IDs as invalid
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for (int idx = 0; idx <= MAX_MAP_ADDR; idx += 4) {
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*(memoryBaseAddress + MAP_ADDR_LUT_OFFSET + idx / 4) =
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NO_DESTINATION << 24 | NO_DESTINATION << 16 | NO_DESTINATION << 8 | NO_DESTINATION;
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}
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// All TCs with MAP ID 7 will be routed to the PM module (can then be read from memory)
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uint8_t routeToPm = calcMapAddrEntry(PM_BUFFER);
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*(memoryBaseAddress + MAP_ADDR_LUT_OFFSET + 1) =
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(NO_DESTINATION << 24) | (NO_DESTINATION << 16) | (NO_DESTINATION << 8) | routeToPm;
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// Write map id clock frequencies
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for (int idx = 0; idx <= MAX_MAP_ADDR; idx += 4) {
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*(memoryBaseAddress + MAP_CLK_FREQ_OFFSET + idx / 4) =
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MAP_CLK_FREQ << 24 | MAP_CLK_FREQ << 16 | MAP_CLK_FREQ << 8 | MAP_CLK_FREQ;
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}
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}
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ReturnValue_t PdecHandler::resetFarStatFlag() {
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uint32_t pdecFar = *(registerBaseAddress + PDEC_FAR_OFFSET);
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if (pdecFar != FAR_RESET) {
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sif::warning << "PdecHandler::resetFarStatFlag: FAR register did not match expected value."
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<< " Read value: 0x" << std::hex << static_cast<unsigned int>(pdecFar)
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<< std::endl;
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return returnvalue::FAILED;
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}
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#if OBSW_DEBUG_PDEC_HANDLER == 1
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sif::debug << "PdecHandler::resetFarStatFlag: read FAR with value: 0x" << std::hex << pdecFar
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<< std::endl;
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#endif /* OBSW_DEBUG_PDEC_HANDLER == 1 */
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return returnvalue::OK;
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}
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ReturnValue_t PdecHandler::releasePdec() {
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ReturnValue_t result = returnvalue::OK;
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result = gpioComIF->pullHigh(pdecReset);
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if (result != returnvalue::OK) {
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sif::error << "PdecHandler::releasePdec: Failed to release PDEC reset signal" << std::endl;
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}
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return result;
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}
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bool PdecHandler::newTcReceived() {
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bool PdecHandler::newTcReceived() {
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uint32_t pdecFar = *(registerBaseAddress + PDEC_FAR_OFFSET);
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uint32_t pdecFar = *(registerBaseAddress + PDEC_FAR_OFFSET);
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@ -33,6 +33,8 @@
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*/
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*/
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class PdecHandler : public SystemObject, public ExecutableObjectIF, public HasActionsIF {
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class PdecHandler : public SystemObject, public ExecutableObjectIF, public HasActionsIF {
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public:
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public:
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enum class Modes { POLLED, IRQ };
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/**
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/**
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* @brief Constructor
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* @brief Constructor
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* @param objectId Object ID of PDEC handler system object
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* @param objectId Object ID of PDEC handler system object
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@ -78,6 +80,8 @@ class PdecHandler : public SystemObject, public ExecutableObjectIF, public HasAc
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private:
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private:
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static const uint8_t INTERFACE_ID = CLASS_ID::PDEC_HANDLER;
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static const uint8_t INTERFACE_ID = CLASS_ID::PDEC_HANDLER;
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static constexpr Modes OP_MODE = Modes::POLLED;
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static const ReturnValue_t ABANDONED_CLTU = MAKE_RETURN_CODE(0xA0);
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static const ReturnValue_t ABANDONED_CLTU = MAKE_RETURN_CODE(0xA0);
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static const ReturnValue_t FRAME_DIRTY = MAKE_RETURN_CODE(0xA1);
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static const ReturnValue_t FRAME_DIRTY = MAKE_RETURN_CODE(0xA1);
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static const ReturnValue_t FRAME_ILLEGAL_ONE_REASON = MAKE_RETURN_CODE(0xA2);
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static const ReturnValue_t FRAME_ILLEGAL_ONE_REASON = MAKE_RETURN_CODE(0xA2);
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@ -234,6 +238,9 @@ class PdecHandler : public SystemObject, public ExecutableObjectIF, public HasAc
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*/
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*/
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void readCommandQueue(void);
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void readCommandQueue(void);
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ReturnValue_t polledOperation();
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ReturnValue_t irqOperation();
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/**
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/**
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* @brief This functions writes the configuration parameters to the configuration
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* @brief This functions writes the configuration parameters to the configuration
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* section of the PDEC.
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* section of the PDEC.
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@ -321,7 +321,8 @@ ReturnValue_t ImtqHandler::scanForReply(const uint8_t* start, size_t remainingSi
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break;
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break;
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case (IMTQ::CC::PAST_AVAILABLE_RESPONSE_BYTES): {
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case (IMTQ::CC::PAST_AVAILABLE_RESPONSE_BYTES): {
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sif::warning << "IMTQHandler::scanForReply: Read 0xFF command byte, reading past available "
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sif::warning << "IMTQHandler::scanForReply: Read 0xFF command byte, reading past available "
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"bytes. Keep 1 ms delay between I2C send and read" << std::endl;
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"bytes. Keep 1 ms delay between I2C send and read"
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<< std::endl;
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result = IGNORE_REPLY_DATA;
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result = IGNORE_REPLY_DATA;
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break;
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break;
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}
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}
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