129 lines
1.6 KiB
C++
129 lines
1.6 KiB
C++
#ifndef FSFWCONFIG_DEVICES_GPIOIDS_H_
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#define FSFWCONFIG_DEVICES_GPIOIDS_H_
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#include <fsfw_hal/common/gpio/GpioIF.h>
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namespace gpioIds {
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enum gpioId_t {
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HEATER_0,
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HEATER_1,
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HEATER_2,
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HEATER_3,
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HEATER_4,
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HEATER_5,
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HEATER_6,
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HEATER_7,
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DEPLSA1,
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DEPLSA2,
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MGM_0_LIS3_CS,
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MGM_1_RM3100_CS,
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GYRO_0_ADIS_CS,
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GYRO_1_L3G_CS,
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GYRO_2_ADIS_CS,
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GYRO_3_L3G_CS,
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MGM_2_LIS3_CS,
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MGM_3_RM3100_CS,
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GNSS_0_NRESET,
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GNSS_1_NRESET,
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GNSS_0_ENABLE,
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GNSS_1_ENABLE,
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GNSS_SELECT,
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GYRO_0_ENABLE,
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GYRO_2_ENABLE,
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TEST_ID_0,
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TEST_ID_1,
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RTD_IC_0,
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RTD_IC_1,
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RTD_IC_2,
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RTD_IC_3,
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RTD_IC_4,
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RTD_IC_5,
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RTD_IC_6,
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RTD_IC_7,
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RTD_IC_8,
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RTD_IC_9,
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RTD_IC_10,
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RTD_IC_11,
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RTD_IC_12,
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RTD_IC_13,
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RTD_IC_14,
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RTD_IC_15,
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CS_SUS_0,
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CS_SUS_1,
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CS_SUS_2,
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CS_SUS_3,
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CS_SUS_4,
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CS_SUS_5,
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CS_SUS_6,
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CS_SUS_7,
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CS_SUS_8,
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CS_SUS_9,
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CS_SUS_10,
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CS_SUS_11,
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SPI_MUX_BIT_0,
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SPI_MUX_BIT_1,
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SPI_MUX_BIT_2,
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SPI_MUX_BIT_3,
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SPI_MUX_BIT_4,
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SPI_MUX_BIT_5,
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CS_RAD_SENSOR,
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ENABLE_RADFET,
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PL_I2C_ARESETN,
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PAPB_BUSY_N,
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PAPB_EMPTY,
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EN_RW1,
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EN_RW2,
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EN_RW3,
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EN_RW4,
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CS_RW1,
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CS_RW2,
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CS_RW3,
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CS_RW4,
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EN_RW_CS,
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SPI_MUX,
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VC0_PAPB_EMPTY,
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VC1_PAPB_EMPTY,
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VC2_PAPB_EMPTY,
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VC3_PAPB_EMPTY,
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PTME_RESETN,
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PDEC_RESET,
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RS485_EN_TX_DATA,
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RS485_EN_TX_CLOCK,
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RS485_EN_RX_DATA,
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RS485_EN_RX_CLOCK,
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BIT_RATE_SEL,
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PLPCDU_ENB_VBAT0,
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PLPCDU_ENB_VBAT1,
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PLPCDU_ENB_DRO,
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PLPCDU_ENB_X8,
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PLPCDU_ENB_TX,
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PLPCDU_ENB_HPA,
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PLPCDU_ENB_MPA,
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PLPCDU_ADC_CS,
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ENABLE_MPSOC_UART,
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ENABLE_SUPV_UART
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};
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}
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#endif /* FSFWCONFIG_DEVICES_GPIOIDS_H_ */
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