388 lines
12 KiB
Makefile
388 lines
12 KiB
Makefile
#-------------------------------------------------------------------------------
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# Makefile for EIVE OBSW
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#-------------------------------------------------------------------------------
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# User-modifiable options
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#-------------------------------------------------------------------------------
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# Fundamentals on the build process of C/C++ Software:
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# https://www3.ntu.edu.sg/home/ehchua/programming/cpp/gcc_make.html
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# Make documentation: https://www.gnu.org/software/make/manual/make.pdf
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# Online: https://www.gnu.org/software/make/manual/make.html
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# General rules: http://make.mad-scientist.net/papers/rules-of-makefiles/#rule3
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SHELL = /bin/sh
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# Chip & board used for compilation
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# (can be overriden by adding CHIP=chip and BOARD=board to the command-line)
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BOARD_FILE_ROOT = bsp_linux
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BOARD = linux
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OS_FSFW = linux
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CUSTOM_DEFINES += -D$(OS_FSFW)
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CUSTOM_DEFINES += -DLINUX
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# General folder paths
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FRAMEWORK_PATH = fsfw
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MISSION_PATH = mission
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CONFIG_PATH = fsfwconfig
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TEST_PATH = test
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UNITTEST_PATH = unittest
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LIBCSP_PATH = libcsp
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# Board specific paths
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BSP_PATH = $(BOARD_FILE_ROOT)
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BOARDTEST_PATH = $(BOARD_FILE_ROOT)/boardtest
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# Output file basename
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BASENAME = eiveobsw
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BINARY_NAME = $(BASENAME)-$(BOARD)
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# Output files will be put in this directory inside
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OUTPUT_FOLDER = $(OS_FSFW)
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# Default debug output
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DEBUG_LEVEL = -g3
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# Optimization level. -O0 default, -Os for size, -O3 for speed and size.
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OPTIMIZATION = -O0
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ifdef GCOV
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CUSTOM_DEFINES += -DGCOV
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endif
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# Output directories
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BUILDPATH = _bin
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DEPENDPATH = _dep
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OBJECTPATH = _obj
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ifeq ($(MAKECMDGOALS), release)
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BUILD_FOLDER = mission
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else
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BUILD_FOLDER = devel
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endif
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DEPENDDIR = $(DEPENDPATH)/$(OUTPUT_FOLDER)/$(BUILD_FOLDER)
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OBJDIR = $(OBJECTPATH)/$(OUTPUT_FOLDER)/$(BUILD_FOLDER)
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BINDIR = $(BUILDPATH)/$(OUTPUT_FOLDER)/$(BUILD_FOLDER)
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CLEANDEP = $(DEPENDPATH)/$(OUTPUT_FOLDER)
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CLEANOBJ = $(OBJECTPATH)/$(OUTPUT_FOLDER)
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CLEANBIN1 = $(BUILDPATH)/$(OUTPUT_FOLDER)/mission
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CLEANBIN2 = $(BUILDPATH)/$(OUTPUT_FOLDER)/devel
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#-------------------------------------------------------------------------------
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# Tools and Includes
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#-------------------------------------------------------------------------------
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# Tool suffix when cross-compiling
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ifdef HOST_LINUX
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CROSS_COMPILE =
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else
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CROSS_COMPILE = arm-linux-gnueabihf-
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endif
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ifdef WINDOWS
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# C Compiler
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CC = $(CROSS_COMPILE)gcc.exe
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# C++ compiler
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CXX = $(CROSS_COMPILE)g++.exe
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# Additional Tools
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SIZE = $(CROSS_COMPILE)size.exe
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STRIP = $(CROSS_COMPILE)strip.exe
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CP = $(CROSS_COMPILE)objcopy.exe
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else
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# C Compiler
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CC = $(CROSS_COMPILE)gcc
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# C++ compiler
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CXX = $(CROSS_COMPILE)g++
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# Additional Tools
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SIZE = $(CROSS_COMPILE)size
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STRIP = $(CROSS_COMPILE)strip
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CP = $(CROSS_COMPILE)objcopy
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endif
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HEXCOPY = $(CP) -O ihex
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BINCOPY = $(CP) -O binary
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# files to be compiled, will be filled in by include makefiles
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# := assignment here is neccessary as initialization so that the +=
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# operator can be used in the submakefiles to achieve immediate evaluation.
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# See: http://make.mad-scientist.net/evaluation-and-expansion/
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CSRC :=
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CXXSRC :=
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ASRC :=
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INCLUDES :=
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# Directories where $(directoryname).mk files should be included from
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SUBDIRS := $(FRAMEWORK_PATH) $(TEST_PATH) $(BSP_PATH) $(UNITTEST_PATH)\
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$(CONFIG_PATH) $(MISSION_PATH) $(LIBCSP_PATH)
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# INCLUDES += framework/test/catch2
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# ETL library include.
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ETL_PATH = etl/include
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I_INCLUDES += -I$(ETL_PATH)
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I_INCLUDES += $(addprefix -I, $(INCLUDES))
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# This is a hack from http://make.mad-scientist.net/the-eval-function/
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#
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# The problem is, that included makefiles should be aware of their relative path
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# but not need to guess or hardcode it. So we set $(CURRENTPATH) for them. If
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# we do this globally and the included makefiles want to include other makefiles as
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# well, they would overwrite $(CURRENTPATH), screwing the include after them.
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#
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# By using a for-loop with an eval'd macro, we can generate the code to include all
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# sub-makefiles (with the correct $(CURRENTPATH) set) before actually evaluating
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# (and by this possibly changing $(CURRENTPATH)) them.
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#
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# This works recursively, if an included makefile wants to include, it can safely set
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# $(SUBDIRS) (which has already been evaluated here) and do
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# "$(foreach S,$(SUBDIRS),$(eval $(INCLUDE_FILE)))"
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# $(SUBDIRS) must be relative to the project root, so to include subdir foo, set
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# $(SUBDIRS) = $(CURRENTPATH)/foo.
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define INCLUDE_FILE
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CURRENTPATH := $S
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include $(S)/$(notdir $S).mk
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endef
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$(foreach S,$(SUBDIRS),$(eval $(INCLUDE_FILE)))
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#-------------------------------------------------------------------------------
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# Source Files
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#-------------------------------------------------------------------------------
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# Additional source files which were not includes by other .mk
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# files are added here.
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# To help Makefile find source files, the source location paths
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# can be added by using the VPATH variable
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# See: https://www.gnu.org/software/make/manual/html_node/General-Search.html
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# It is recommended to only use VPATH to add source locations
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# See: http://make.mad-scientist.net/papers/how-not-to-use-vpath/
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# Please ensure that no files are included by both .mk file and here !
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# All C Sources included by .mk files are assigned here
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# Add the objects to sources so dependency handling works
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C_OBJECTS += $(CSRC:.c=.o)
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# Objects built from Assembly source files
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ASM_OBJECTS = $(ASRC:.S=.o)
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# Objects built from C++ source files
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CXX_OBJECTS += $(CXXSRC:.cpp=.o)
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#-------------------------------------------------------------------------------
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# Build Configuration + Output
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#-------------------------------------------------------------------------------
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TARGET = Debug
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DEBUG_MESSAGE = Off
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OPTIMIZATION_MESSAGE = Off
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# Define Messages
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MSG_INFO = Software: EIVE OBSW Linux.
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MSG_LINKING = Linking:
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MSG_COMPILING = Compiling:
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MSG_ASSEMBLING = Assembling:
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MSG_BINARY = Generate binary:
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MSG_OPTIMIZATION = Optimization: $(OPTIMIZATION), $(OPTIMIZATION_MESSAGE)
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MSG_TARGET = Target Build: $(TARGET)
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MSG_DEBUG = FSFW Debugging: $(DEBUG_MESSAGE)
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MSG_COMIF = TMTC Communication Interface: $(COMIF_MESSAGE)
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# See: https://stackoverflow.com/questions/6687630/how-to-remove-unused-c-c-symbols-with-gcc-and-ld
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# Used to throw away unused code. Reduces code size significantly !
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# -Wl,--gc-sections: needs to be passed to the linker to throw aways unused code
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ifdef KEEP_UNUSED_CODE
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PROTOTYPE_OPTIMIZATION =
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DEAD_CODE_REMOVAL =
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else
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PROTOTYPE_OPTIMIZATION = -ffunction-sections -fdata-sections
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DEAD_CODE_REMOVAL = -Wl,--gc-sections
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# Link time optimization
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# See https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html for reference
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# Link time is larger and size of object files can not be retrieved
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# but resulting binary is smaller. Could be used in mission/deployment build
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# Requires -ffunction-section in linker call
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LINK_TIME_OPTIMIZATION = -flto
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OPTIMIZATION += $(PROTOTYPE_OPTIMIZATION)
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endif
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# Dependency Flags
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# These flags tell the compiler to build dependencies
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# See: https://www.gnu.org/software/make/manual/html_node/Automatic-Prerequisites.html
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# Using following guide:
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# http://make.mad-scientist.net/papers/advanced-auto-dependency-generation/
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DEPFLAGS = -MT $@ -MMD -MP -MF $(DEPENDDIR)/$*.d
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# Flags for the compiler call
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# - std: Which C++ version to use. Common versions: c++11, c++14 and c++17
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# - Wall: enable all warnings
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# - Wextra: enable extra warnings
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# - g: defines debug level
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# - fmessage-length: to control the formatting algorithm for diagnostic messages;
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# =0 means no line-wrapping is done; each error message appears on a single line
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# - fno-exceptions: stops generating extra code needed to propagate exceptions,
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# which can produce significant data size overhead
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WARNING_FLAGS = -Wall -Wshadow=local -Wextra -Wimplicit-fallthrough=1 \
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-Wno-unused-parameter
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CXXDEFINES := $(CUSTOM_DEFINES)
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CFLAGS +=
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CXXFLAGS += -I. $(DEBUG_LEVEL) $(OPTIMIZATION) $(DEPFLAGS) $(WARNING_FLAGS) \
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$(I_INCLUDES) -fmessage-length=0 $(CXXDEFINES)
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CPPFLAGS += -std=c++17 -fno-exceptions
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ASFLAGS = -Wall $(DEBUG_LEVEL) $(OPTIMIZATION) $(I_INCLUDES) -D__ASSEMBLY__
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# Flags for the linker call
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# LINK_INCLUDES specify the path to used libraries and the linker script
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# LINK_LIBRARIES link HCC and HAL library and enable float support
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LINK_FLAGS = $(DEBUG_LEVEL) $(DEAD_CODE_REMOVAL) $(OPTIMIZATION) -pthread
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LINK_INCLUDES =
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LINK_LIBRARIES = -lrt
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# Gnu Coverage Tools Flags
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ifdef GCOV
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GCOV_CXXFLAGS = -fprofile-arcs -ftest-coverage
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CXXFLAGS += $(GCOV_CXXFLAGS)
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GCOV_LINKER_LIBS = -lgcov -fprofile-arcs -ftest-coverage
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LINK_LIBRARIES += $(GCOV_LINKER_LIBS)
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endif
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#-------------------------------------------------------------------------------
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# Rules
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#-------------------------------------------------------------------------------
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# Makefile rules: https://www.gnu.org/software/make/manual/html_node/Rules.html
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# This is the primary section which defines the ruleset to build
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# the executable from the sources.
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default: all
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# In this section, the binaries are built for all selected memories
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all: executable
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# Cleans all files
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hardclean:
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-rm -rf $(BUILDPATH)
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-rm -rf $(OBJECTPATH)
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-rm -rf $(DEPENDPATH)
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# Only clean files for current build
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clean:
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@echo $(DEPFILES)
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-rm -rf $(CLEANOBJ)
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-rm -rf $(CLEANBIN)
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-rm -rf $(CLEANDEP)
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# Only clean binaries. Useful for changing the binary type when object files
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# are already compiled so complete rebuild is not necessary
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cleanbin:
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-rm -rf $(BUILDPATH)/$(OUTPUT_FOLDER)
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# Build target configuration
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release: OPTIMIZATION = -O2 $(PROTOTYPE_OPTIMIZATION) $(LINK_TIME_OPTIMIZATION)
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release: LINK_TIME_OPTIMIZATION = -flto
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release: TARGET = Release
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release: OPTIMIZATION_MESSAGE = On with Link Time Optimization
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release: DEBUG_LEVEL = -g0
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debug: CXXDEFINES += -DDEBUG
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debug: DEBUG_MESSAGE = On
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debug release: executable
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executable: $(BINDIR)/$(BINARY_NAME).elf
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@echo
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@echo $(MSG_INFO)
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@echo $(MSG_TARGET)
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@echo $(MSG_OPTIMIZATION)
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@echo $(MSG_DEBUG)
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# For debugging.
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# $(info $${C_OBJECTS} is [${C_OBJECTS}])
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# $(info $${CXX_OBJECTS} is [${CXX_OBJECTS}])
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C_OBJECTS_PREFIXED = $(addprefix $(OBJDIR)/, $(C_OBJECTS))
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CXX_OBJECTS_PREFIXED = $(addprefix $(OBJDIR)/, $(CXX_OBJECTS))
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ASM_OBJECTS_PREFIXED = $(addprefix $(OBJDIR)/, $(ASM_OBJECTS))
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ALL_OBJECTS_PREFIXED = $(ASM_OBJECTS_PREFIXED) $(C_OBJECTS_PREFIXED) \
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$(CXX_OBJECTS_PREFIXED)
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# Useful for debugging the Makefile
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# Also see: https://www.oreilly.com/openbook/make3/book/ch12.pdf
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# $$(info $${ALL_OBJECTS_PREFIXED} is [${ALL_OBJECTS_PREFIXED}])
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# Automatic variables are used here extensively. Some of them
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# are escaped($$) to suppress immediate evaluation. The most important ones are:
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# $@: Name of Target (left side of rule)
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# $<: Name of the first prerequisite (right side of rule)
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# @^: List of all prerequisite, omitting duplicates
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# @D: Directory and file-within-directory part of $@
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# Generates binary and displays all build properties
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# -p with mkdir ignores error and creates directory when needed.
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# SHOW_DETAILS = 1
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$(BINDIR)/$(BINARY_NAME).elf: $(ALL_OBJECTS_PREFIXED)
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@echo $(MSG_LINKING) Target $@
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@mkdir -p $(@D)
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ifdef SHOW_DETAILS
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$(CXX) $(LINK_FLAGS) $(LINK_INCLUDES) -o $@ $^ $(LINK_LIBRARIES)
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else
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@$(CXX) $(LINK_FLAGS) $(LINK_INCLUDES) -o $@ $^ $(LINK_LIBRARIES)
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endif
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ifeq ($(BUILD_FOLDER), release)
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# With Link Time Optimization, section size is not available
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$(SIZE) $@
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else
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@$(SIZE) $^ $@
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endif
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$(OBJDIR)/%.o: %.cpp
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$(OBJDIR)/%.o: %.cpp $(DEPENDDIR)/%.d | $(DEPENDDIR)
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@echo $(I_INCLUDES)
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@echo
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@echo $(MSG_COMPILING) $<
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@mkdir -p $(@D)
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ifdef SHOW_DETAILS
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$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c -o $@ $<
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else
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@$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c -o $@ $<
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endif
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$(OBJDIR)/%.o: %.c
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$(OBJDIR)/%.o: %.c $(DEPENDDIR)/%.d | $(DEPENDDIR)
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@echo
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@echo $(MSG_COMPILING) $<
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@mkdir -p $(@D)
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ifdef SHOW_DETAILS
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$(CC) $(CXXFLAGS) $(CFLAGS) -c -o $@ $<
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else
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@$(CC) $(CXXFLAGS) $(CFLAGS) -c -o $@ $<
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endif
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#-------------------------------------------------------------------------------
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# Dependency Handling
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#-------------------------------------------------------------------------------
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# Dependency Handling according to following guide:
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# http://make.mad-scientist.net/papers/advanced-auto-dependency-generation/
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$(DEPENDDIR):
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@mkdir -p $(@D)
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DEPENDENCY_RELATIVE = $(CSRC:.c=.d) $(CXXSRC:.cpp=.d)
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# This is the list of all dependencies
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DEPFILES = $(addprefix $(DEPENDDIR)/, $(DEPENDENCY_RELATIVE))
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# Create subdirectories for dependencies
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$(DEPFILES):
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@mkdir -p $(@D)
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# Include all dependencies
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include $(wildcard $(DEPFILES))
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# .PHONY tells make that these targets aren't files
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.PHONY: clean sdramCfg release debug all hardclean
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