337 lines
11 KiB
Makefile
337 lines
11 KiB
Makefile
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#-------------------------------------------------------------------------------
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# Makefile for FSFW Example
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#-------------------------------------------------------------------------------
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# User-modifiable options
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#-------------------------------------------------------------------------------
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# Fundamentals on the build process of C/C++ Software:
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# https://www3.ntu.edu.sg/home/ehchua/programming/cpp/gcc_make.html
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# Make documentation: https://www.gnu.org/software/make/manual/make.pdf
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# Online: https://www.gnu.org/software/make/manual/make.html
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# General rules: http://make.mad-scientist.net/papers/rules-of-makefiles/#rule3
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SHELL = /bin/sh
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#$(SHELL ./setup-siso-env.sh)
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FRAMEWORK_PATH = fsfw
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MISSION_PATH = mission
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CONFIG_PATH = bsp_linux/fsfwconfig
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#TEST_PATH = test
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# Board support package path. This will generally contain code which is
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# not portable and depends on the hardware.
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BSP_PATH = bsp_linux
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BASE_NAME = fsfw-example
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OS_FSFW = linux
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BOARD = linux
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OUTPUT_FOLDER = $(BOARD)
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BINARY_NAME = $(BASE_NAME)-$(BOARD)
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# Default debug level (for full debugging information)
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DEBUG_LEVEL = -g3
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# Default optimization level.
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# 1. -O0 default for debugging
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# 2. -Os for size
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# 3. -O3/-O2 for speed and size.
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OPTIMIZATION = -O0
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# Output directories
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BUILDPATH = _bin
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DEPENDPATH = _dep
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OBJECTPATH = _obj
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ifeq ($(MAKECMDGOALS),release)
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BUILD_FOLDER = release
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else
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BUILD_FOLDER = debug
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endif
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DEPENDDIR = $(DEPENDPATH)/$(OUTPUT_FOLDER)/$(BUILD_FOLDER)
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OBJDIR = $(OBJECTPATH)/$(OUTPUT_FOLDER)/$(BUILD_FOLDER)
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BINDIR = $(BUILDPATH)/$(OUTPUT_FOLDER)/$(BUILD_FOLDER)
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CLEANDEP = $(DEPENDPATH)/$(OUTPUT_FOLDER)
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CLEANOBJ = $(OBJECTPATH)/$(OUTPUT_FOLDER)
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CLEANBIN = $(BUILDPATH)
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#-------------------------------------------------------------------------------
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# Tools and Includes
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#-------------------------------------------------------------------------------
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CROSS_COMPILE =
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# c++ compiler
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CXX := $(CROSS_COMPILE)g++
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# c compiler
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CC := $(CROSS_COMPILE)gcc
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SIZE := $(CROSS_COMPILE)size
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# Empty initialization is important for submakefile handling!
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CXXSRC :=
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CSRC :=
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INCLUDES :=
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# Directries where $(directoryname).mk files should be included from
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SUBDIRS := $(BSP_PATH) $(CONFIG_PATH) $(MISSION_PATH) \
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$(FRAMEWORK_PATH)
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#SISODIR5 = /opt/siso
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#SISODIR5_INCLUDE=/opt/siso/include
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#PCODIR_1=/opt/pco_camera/pco_common/pco_include
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#PCODIR_2=/opt/pco_camera/pco_common/pco_classes
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#PCODIR_3=/opt/pco_camera/pco_me4/pco_classes
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#PCOLIB_DIR=/opt/pco_camera/pco_common/pco_lib
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#SISOLIB_DIR=/opt/siso/lib64
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#FG_LIB_PATH=/home/esbo/ESBOSW/DeviceTestsExample/mission/devices/Visible_Instrument
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# This is a hack from http://make.mad-scientist.net/the-eval-function/
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#
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# The problem is, that included makefiles should be aware of their relative path
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# but not need to guess or hardcode it. So we set $(CURRENTPATH) for them. If
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# we do this globally and the included makefiles want to include other makefiles as
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# well, they would overwrite $(CURRENTPATH), screwing the include after them.
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#
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# By using a for-loop with an eval'd macro, we can generate the code to include all
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# sub-makefiles (with the correct $(CURRENTPATH) set) before actually evaluating
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# (and by this possibly changing $(CURRENTPATH)) them.
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#
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# This works recursively, if an included makefile wants to include, it can safely set
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# $(SUBDIRS) (which has already been evaluated here) and do
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# "$(foreach S,$(SUBDIRS),$(eval $(INCLUDE_FILE)))"
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# $(SUBDIRS) must be relative to the project root, so to include subdir foo, set
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# $(SUBDIRS) = $(CURRENTPATH)/foo.
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define INCLUDE_FILE
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CURRENTPATH := $S
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include $(S)/$(notdir $S).mk
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endef
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$(foreach S,$(SUBDIRS),$(eval $(INCLUDE_FILE)))
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# Include all includes defined as INCLUDES=...
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I_INCLUDES += $(addprefix -I, $(INCLUDES))
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# Debug Info
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# $(info $${I_INCLUDES} is [${I_INCLUDES}])
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#-------------------------------------------------------------------------------
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# Source Files
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#-------------------------------------------------------------------------------
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# Additional source files which were not includes by other .mk
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# files are added here.
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# To help Makefile find source files, the source location paths
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# can be added by using the VPATH variable
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# See: https://www.gnu.org/software/make/manual/html_node/General-Search.html
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# It is recommended to only use VPATH to add source locations
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# See: http://make.mad-scientist.net/papers/how-not-to-use-vpath/
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# Please ensure that no files are included by both .mk file and here !
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# All C Sources included by .mk files are assigned here
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# Add the objects to sources so dependency handling works
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C_OBJECTS += $(CSRC:.c=.o)
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# Objects built from Assembly source files
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ASM_OBJECTS = $(ASRC:.S=.o)
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# Objects built from C++ source files
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CXX_OBJECTS += $(CXXSRC:.cpp=.o)
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#-------------------------------------------------------------------------------
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# Build Configuration + Output
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#-------------------------------------------------------------------------------
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WARNING_FLAGS = -Wall -Wshadow=local -Wextra -Wimplicit-fallthrough=1 \
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-Wno-unused-parameter -Wno-write-strings -Wno-unused-but-set-variable -Wno-unknown-pragmas
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CUSTOM_DEFINES += -DAPI=LINUX -DLINUX=2
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# Flags for both c++ and c
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CXXFLAGS += -I. $(OPTIMIZATION) $(DEBUG_LEVEL) $(DEPFLAGS) $(WARNING_FLAGS) \
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-fmessage-length=0 $(CUSTOM_DEFINES) $(I_INCLUDES)
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# Flags for c only
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CFLAGS +=
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# Flags for c++ only
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CPPFLAGS += -std=c++11 -fno-exceptions
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# For debugging.
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# $(info $${CXXFLAGS} is [${CXXFLAGS}])
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# $(info $${CFLAGS} is [${CFLAGS}])
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# $(info $${CPPFLAGS} is [${CPPFLAGS}])
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# See: https://stackoverflow.com/questions/6687630/how-to-remove-unused-c-c-symbols-with-gcc-and-ld
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# Used to throw away unused code. Reduces code size significantly !
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# -Wl,--gc-sections: needs to be passed to the linker to discard unused sections
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# KEEP_UNUSED_CODE = 1
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ifdef KEEP_UNUSED_CODE
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PROTOTYPE_OPTIMIZATION =
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UNUSED_CODE_REMOVAL =
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else
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PROTOTYPE_OPTIMIZATION = -ffunction-sections -fdata-sections
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UNUSED_CODE_REMOVAL = -Wl,--gc-sections
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# Link time optimization
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# See https://gcc.gnu.org/onlinedocs/gcc/Optimize-Options.html for reference
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# Link time is larger and size of object files can not be retrieved
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# but resulting binary is smaller. Could be used in mission/deployment build
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# Requires -ffunction-section in linker call
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LINK_TIME_OPTIMIZATION = -flto
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OPTIMIZATION += $(PROTOTYPE_OPTIMIZATION)
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endif
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# Dependency Flags
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# These flags tell the compiler to build dependencies
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# See: https://www.gnu.org/software/make/manual/html_node/Automatic-Prerequisites.html
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# Using following guide:
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# http://make.mad-scientist.net/papers/advanced-auto-dependency-generation/
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DEPFLAGS = -MT $@ -MMD -MP -MF $(DEPENDDIR)/$*.d
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#-L $(SISOLIB_DIR) -L $(SISOLIB_DIR) -L $(PCOLIB_DIR)
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LINKFLAGS = $(DEBUG_LEVEL) $(UNUSED_CODE_REMOVAL) $(OPTIMIZATION) -pthread
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#LINKLIB = -lrt -lfglib5 -lpcocom_me4 -lclsersis -lpcolog `pkg-config --libs opencv4`
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LINKLIB = -lrt
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TARGET = Debug
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OPTIMIZATION_MESSAGE = Off
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DEBUG_MESSAGE = Off\(no -DDEBUG\)
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# Define Messages
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MSG_INFO = Software: Hosted Flight Software Framework \(FSFW\) example.
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MSG_TARGET = Target Build: $(TARGET)
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MSG_DEPENDENCY = Collecting dependencies for:
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MSG_COMPILING = Compiling:
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MSG_LINKING = Linking:
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MSG_DEBUG = Debug level: $(DEBUG_LEVEL), FSFW Debugging: $(DEBUG_MESSAGE)
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MSG_OPTIMIZATION = Optimization: $(OPTIMIZATION), $(OPTIMIZATION_MESSAGE)
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#-------------------------------------------------------------------------------
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# Rules
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#-------------------------------------------------------------------------------
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# Makefile rules: https://www.gnu.org/software/make/manual/html_node/Rules.html
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# This is the primary section which defines the ruleset to build
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# the executable from the sources.
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# Default target
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default: all
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all: debug
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# building the different builds.
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release debug: executable
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# Target specific variables for release build.
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release: OPTIMIZATION = -O2
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release: DEBUG_LEVEL = -g0
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release: TARGET = Release
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release: OPTIMIZATION_MESSAGE = On
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# Target specific variables for debug build.
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debug: CXXDEFINES += -DDEBUG
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debug: DEBUG_MESSAGE = On\(-DDEBUG\)
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# Cleans all files
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hardclean:
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-rm -rf $(BUILDPATH)
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-rm -rf $(OBJECTPATH)
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-rm -rf $(DEPENDPATH)
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# Only clean files for current build
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clean:
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-rm -rf $(CLEANOBJ)
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-rm -rf $(CLEANBIN)
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-rm -rf $(CLEANDEP)
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# Only clean binaries. Useful for changing the binary type when object
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# files are already compiled so complete rebuild is not necessary
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cleanbin:
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-rm -rf $(BUILDPATH)/$(OUTPUT_FOLDER)
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executable: $(BINDIR)/$(BINARY_NAME).elf
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@echo
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@echo $(MSG_INFO)
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@echo $(MSG_TARGET)
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@echo $(MSG_OPTIMIZATION)
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@echo $(MSG_DEBUG)
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# For debugging.
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# $(info $${C_OBJECTS} is [${C_OBJECTS}])
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# $(info $${CXX_OBJECTS} is [${CXX_OBJECTS}])
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C_OBJECTS_PREFIXED = $(addprefix $(OBJDIR)/, $(C_OBJECTS))
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CXX_OBJECTS_PREFIXED = $(addprefix $(OBJDIR)/, $(CXX_OBJECTS))
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ASM_OBJECTS_PREFIXED = $(addprefix $(OBJDIR)/, $(ASM_OBJECTS))
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ALL_OBJECTS_PREFIXED = $(ASM_OBJECTS_PREFIXED) $(C_OBJECTS_PREFIXED) \
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$(CXX_OBJECTS_PREFIXED)
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# Useful for debugging the Makefile
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# Also see: https://www.oreilly.com/openbook/make3/book/ch12.pdf
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# $$(info $${ALL_OBJECTS_PREFIXED} is [${ALL_OBJECTS_PREFIXED}])
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# Automatic variables are used here extensively. Some of them
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# are escaped($$) to suppress immediate evaluation. The most important ones are:
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# $@: Name of Target (left side of rule)
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# $<: Name of the first prerequisite (right side of rule)
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# @^: List of all prerequisite, omitting duplicates
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# @D: Directory and file-within-directory part of $@
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# Generates binary and displays all build properties
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# -p with mkdir ignores error and creates directory when needed.
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# SHOW_DETAILS = 1
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$(BINDIR)/$(BINARY_NAME).elf: $(ALL_OBJECTS_PREFIXED)
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@echo $(MSG_LINKING) Target $@
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@mkdir -p $(@D)
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ifdef SHOW_DETAILS
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$(CXX) $(LINKFLAGS) $(LINK_INCLUDES) -o $@ $^ $(LINKLIB)
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else
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@$(CXX) $(LINKFLAGS) $(LINK_INCLUDES) -o $@ $^ $(LINKLIB)
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endif
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ifeq ($(BUILD_FOLDER), release)
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# With Link Time Optimization, section size is not available
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$(SIZE) $@
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else
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@$(SIZE) $^ $@
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endif
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$(OBJDIR)/%.o: %.cpp
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$(OBJDIR)/%.o: %.cpp $(DEPENDDIR)/%.d | $(DEPENDDIR)
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@echo
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@echo $(MSG_COMPILING) $<
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@mkdir -p $(@D)
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ifdef SHOW_DETAILS
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$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c -o $@ $<
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else
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@$(CXX) $(CXXFLAGS) $(CPPFLAGS) -c -o $@ $<
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endif
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$(OBJDIR)/%.o: %.c
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$(OBJDIR)/%.o: %.c $(DEPENDDIR)/%.d | $(DEPENDDIR)
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@echo
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@echo $(MSG_COMPILING) $<
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@mkdir -p $(@D)
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ifdef SHOW_DETAILS
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$(CC) $(CXXFLAGS) $(CFLAGS) -c -o $@ $<
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else
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@$(CC) $(CXXFLAGS) $(CFLAGS) -c -o $@ $<
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endif
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#-------------------------------------------------------------------------------
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# Dependency Handling
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#-------------------------------------------------------------------------------
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# Dependency Handling according to following guide:
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# http://make.mad-scientist.net/papers/advanced-auto-dependency-generation/
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$(DEPENDDIR):
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@mkdir -p $(@D)
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DEPENDENCY_RELATIVE = $(CSRC:.c=.d) $(CXXSRC:.cpp=.d)
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# This is the list of all dependencies
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DEPFILES = $(addprefix $(DEPENDDIR)/, $(DEPENDENCY_RELATIVE))
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# Create subdirectories for dependencies
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$(DEPFILES):
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@mkdir -p $(@D)
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# Include all dependencies
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include $(wildcard $(DEPFILES))
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.PHONY: release debug hardclean clean binclean all
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