fsfw/fsfw-hal
fsfw/fsfw-hal
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solves issue with DMA

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This commit is contained in:
Robin Müller 2021-06-04 12:58:30 +02:00
parent 20815c1d6b
commit cf8235cede
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GPG Key ID: 71B58F8A3CDFA9AC
2 changed files with 17 additions and 3 deletions
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16
stm32h7/devicetest/GyroL3GD20H.cpp
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@ -11,7 +11,10 @@
#include "stm32h7xx_hal_spi.h" #include "stm32h7xx_hal_spi.h"
#include "stm32h7xx_hal_rcc.h" #include "stm32h7xx_hal_rcc.h"
std::array<uint8_t, GyroL3GD20H::recvBufferSize> GyroL3GD20H::rxBuffer; alignas(32) std::array<uint8_t, GyroL3GD20H::recvBufferSize> GyroL3GD20H::rxBuffer;
alignas(32) std::array<uint8_t, GyroL3GD20H::txBufferSize>
GyroL3GD20H::txBuffer __attribute__((section(".dma_buffer")));
TransferStates transferState = TransferStates::IDLE; TransferStates transferState = TransferStates::IDLE;
DMA_HandleTypeDef txDmaHandle; DMA_HandleTypeDef txDmaHandle;
DMA_HandleTypeDef rxDmaHandle; DMA_HandleTypeDef rxDmaHandle;
@ -83,6 +86,15 @@ ReturnValue_t GyroL3GD20H::performOperation() {
} }
ReturnValue_t GyroL3GD20H::handleDmaTransfer() { ReturnValue_t GyroL3GD20H::handleDmaTransfer() {
/* Clean D-cache */
/* Make sure the address is 32-byte aligned and add 32-bytes to length,
in case it overlaps cacheline */
// See https://community.st.com/s/article/FAQ-DMA-is-not-working-on-STM32H7-devices
#if STM_USE_PERIPHERAL_TX_BUFFER_MPU_PROTECTION == 0
SCB_CleanDCache_by_Addr((uint32_t*)(((uint32_t)txBuffer.data()) & ~(uint32_t)0x1F),
txBuffer.size()+32);
#endif
if(HAL_SPI_TransmitReceive_DMA(spiHandle, txBuffer.data(), rxBuffer.data(), 2) != HAL_OK) { if(HAL_SPI_TransmitReceive_DMA(spiHandle, txBuffer.data(), rxBuffer.data(), 2) != HAL_OK) {
// Transfer error in transmission process // Transfer error in transmission process
sif::printWarning("Error transmitting SPI with DMA\n"); sif::printWarning("Error transmitting SPI with DMA\n");
@ -90,7 +102,7 @@ ReturnValue_t GyroL3GD20H::handleDmaTransfer() {
// Wait for the transfer to complete // Wait for the transfer to complete
while (transferState == TransferStates::WAIT) { while (transferState == TransferStates::WAIT) {
//TaskFactory::delayTask(1); TaskFactory::delayTask(1);
} }
// Invalidate cache prior to access by CPU // Invalidate cache prior to access by CPU

4
stm32h7/devicetest/GyroL3GD20H.h
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@ -33,8 +33,10 @@ private:
SPI_HandleTypeDef* spiHandle; SPI_HandleTypeDef* spiHandle;
spi::TransferModes transferMode; spi::TransferModes transferMode;
static constexpr size_t recvBufferSize = 32 * 10; static constexpr size_t recvBufferSize = 32 * 10;
static std::array<uint8_t, recvBufferSize> rxBuffer; static std::array<uint8_t, recvBufferSize> rxBuffer;
std::array<uint8_t, 32> txBuffer; static constexpr size_t txBufferSize = 32;
static std::array<uint8_t, txBufferSize> txBuffer;
ReturnValue_t handleDmaTransfer(); ReturnValue_t handleDmaTransfer();
ReturnValue_t handlePollingTransfer(); ReturnValue_t handlePollingTransfer();