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xilinx eth in own folder. found another bug/challenge with dma

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This commit is contained in:
Ulrich Mohr
2024-08-26 12:03:31 +02:00
parent 8497fe754c
commit ee06c79bf4
9 changed files with 163 additions and 233 deletions
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9
bsp_z7/lwip/include/lwipopts.h
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@ -114,7 +114,9 @@
byte alignment -> define MEM_ALIGNMENT to 2. */
/* MSVC port: intel processors don't need 4-byte alignment,
but are faster that way! */
#define MEM_ALIGNMENT 8U
//TODO documentation
//Zynq needs 32 for DMA to work (something about cache I guess...)
#define MEM_ALIGNMENT 32U
#define MEM_USE_POOLS 1
#define MEMP_USE_CUSTOM_POOLS MEM_USE_POOLS
@ -166,6 +168,7 @@ a lot of data that needs to be copied, this should be set high. */
#define PBUF_POOL_SIZE 120
/* PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. */
/* Needs to be large enough to fit eth MTU to be able to use DMA for xemacps rx*/
#define PBUF_POOL_BUFSIZE 1600
/** SYS_LIGHTWEIGHT_PROT
@ -177,7 +180,7 @@ a lot of data that needs to be copied, this should be set high. */
/* ---------- TCP options ---------- */
#define LWIP_TCP 1
#define LWIP_TCP 0
#define TCP_TTL 255
#define LWIP_ALTCP (LWIP_TCP)
@ -288,7 +291,7 @@ a lot of data that needs to be copied, this should be set high. */
#endif /* LWIP_STATS */
/* ---------- NETBIOS options ---------- */
#define LWIP_NETBIOS_RESPOND_NAME_QUERY 1
#define LWIP_NETBIOS_RESPOND_NAME_QUERY 0
/* ---------- PPP options ---------- */

16
bsp_z7/lwip/netif/xemacpsif.c
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@ -279,6 +279,14 @@ s32_t xemacpsif_input(struct netif *netif)
/* points to packet payload, which starts with an Ethernet header */
ethhdr = p->payload;
// xil_printf("\n %p %i\n",p->payload, p->len);
// for (int j = 0; j < 6; j++) {
// for (int i = 0; i < 8; i++) {
// xil_printf(" %02x", *((uint8_t *)(p->payload) + i + j * 8 ) );
// }
// xil_printf("\n");
// }
#if LINK_STATS
lwip_stats.link.recv++;
#endif /* LINK_STATS */
@ -305,9 +313,11 @@ s32_t xemacpsif_input(struct netif *netif)
break;
default:
for (int i = 0; i < 14; i++) {
xil_printf(" %02x", *((uint8_t *)(p->payload) + i ) );
}
//TODO debug
// for (int i = 0; i < 14; i++) {
// xil_printf(" %02x", *((uint8_t *)(p->payload) + i ) );
// }
// xil_printf("invalid eth type\n");
pbuf_free(p);
p = NULL;
break;

5
bsp_z7/lwip/netif/xemacpsif_dma.c
View File

@ -538,6 +538,7 @@ void emacps_recv_handler(void *arg)
}
for (k = 0, curbdptr=rxbdset; k < bd_processed; k++) {
// outbyte('r');
bdindex = XEMACPS_BD_TO_INDEX(rxring, curbdptr);
p = (struct pbuf *)rx_pbufs_storage[index + bdindex];
@ -552,6 +553,8 @@ void emacps_recv_handler(void *arg)
#endif
pbuf_realloc(p, rx_bytes);
// xil_printf("reading bd index %i bdindex %i p %p payload %p len %i\n", index, bdindex, p, p->payload, p->len);
/* Invalidate RX frame before queuing to handle
* L1 cache prefetch conditions on any architecture.
*/
@ -775,6 +778,8 @@ XStatus init_dma(struct xemac_s *xemac)
#endif
XEmacPs_BdSetAddressRx(rxbd, (UINTPTR)p->payload);
xil_printf("setting bd index %i bdindex %i p %p payload %p\n", index, bdindex, p, p->payload);
rx_pbufs_storage[index + bdindex] = (UINTPTR)p;
}
XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.RxBdRing.BaseBdAddr, 0, XEMACPS_RECV);