forked from ROMEO/obsw
xilinx eth lwip version xilinx_v2024.1
This commit is contained in:
@ -1,12 +0,0 @@
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target_sources(lwip_xil PRIVATE
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xadapter.c
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xpqueue.c
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xemacpsif_dma.c
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xemacpsif_physpeed.c
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xemacpsif_hw.c
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xemacpsif.c
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topology.c
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)
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target_include_directories(lwip_xil PRIVATE ${CMAKE_CURRENT_SOURCE_DIR})
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@ -1,37 +0,0 @@
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#include "netif/xtopology.h"
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// struct xtopology_t {
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// UINTPTR emac_baseaddr;
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// enum xemac_types emac_type;
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// #ifndef SDT
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// UINTPTR intc_baseaddr;
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// unsigned intc_emac_intr; /* valid only for xemac_type_xps_emaclite */
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// UINTPTR scugic_baseaddr; /* valid only for Zynq */
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// unsigned scugic_emac_intr; /* valid only for GEM */
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// #endif
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// };
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int xtopology_n_emacs = 2;
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struct xtopology_t xtopology[] = {
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{
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0xE000B000,
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xemac_type_emacps,
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#ifndef SDT
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0,
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0,
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0xF8F00100,
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0x36
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#endif
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},
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{
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0xE000C000,
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xemac_type_emacps,
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#ifndef SDT
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0,
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0,
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0xF8F00100,
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0x4D
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#endif
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}
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};
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@ -279,14 +279,6 @@ s32_t xemacpsif_input(struct netif *netif)
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/* points to packet payload, which starts with an Ethernet header */
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ethhdr = p->payload;
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// xil_printf("\n %p %i\n",p->payload, p->len);
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// for (int j = 0; j < 6; j++) {
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// for (int i = 0; i < 8; i++) {
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// xil_printf(" %02x", *((uint8_t *)(p->payload) + i + j * 8 ) );
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// }
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// xil_printf("\n");
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// }
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#if LINK_STATS
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lwip_stats.link.recv++;
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#endif /* LINK_STATS */
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@ -313,11 +305,6 @@ s32_t xemacpsif_input(struct netif *netif)
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break;
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default:
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//TODO debug
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// for (int i = 0; i < 14; i++) {
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// xil_printf(" %02x", *((uint8_t *)(p->payload) + i ) );
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// }
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// xil_printf("invalid eth type\n");
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pbuf_free(p);
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p = NULL;
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break;
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@ -538,7 +538,6 @@ void emacps_recv_handler(void *arg)
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}
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for (k = 0, curbdptr=rxbdset; k < bd_processed; k++) {
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// outbyte('r');
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bdindex = XEMACPS_BD_TO_INDEX(rxring, curbdptr);
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p = (struct pbuf *)rx_pbufs_storage[index + bdindex];
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@ -553,8 +552,6 @@ void emacps_recv_handler(void *arg)
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#endif
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pbuf_realloc(p, rx_bytes);
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// xil_printf("reading bd index %i bdindex %i p %p payload %p len %i\n", index, bdindex, p, p->payload, p->len);
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/* Invalidate RX frame before queuing to handle
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* L1 cache prefetch conditions on any architecture.
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*/
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@ -579,12 +576,10 @@ void emacps_recv_handler(void *arg)
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setup_rx_bds(xemacpsif, rxring);
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}
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#if !NO_SYS
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// BaseType_t xHigherPriorityTaskWoken;
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// xSemaphoreGiveFromISR(xemac->sem_rx_data_available.sem, &xHigherPriorityTaskWoken);
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// portYIELD_FROM_ISR(xHigherPriorityTaskWoken); //TODO delay this?
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sys_sem_signal(&xemac->sem_rx_data_available);
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xInsideISR--;
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#endif
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return;
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}
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@ -777,8 +772,6 @@ XStatus init_dma(struct xemac_s *xemac)
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#endif
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XEmacPs_BdSetAddressRx(rxbd, (UINTPTR)p->payload);
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xil_printf("setting bd index %i bdindex %i p %p payload %p\n", index, bdindex, p, p->payload);
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rx_pbufs_storage[index + bdindex] = (UINTPTR)p;
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}
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XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.RxBdRing.BaseBdAddr, 0, XEMACPS_RECV);
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@ -808,18 +801,18 @@ XStatus init_dma(struct xemac_s *xemac)
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XEmacPs_Out32((xemacpsif->emacps.Config.BaseAddress + XEMACPS_TXQBASE_OFFSET),
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(UINTPTR)bdtxterminate);
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}
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// #if !NO_SYS
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// #ifdef SDT
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// xPortInstallInterruptHandler(xemacpsif->emacps.Config.IntrId,
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// ( Xil_InterruptHandler ) XEmacPs_IntrHandler,
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// (void *)&xemacpsif->emacps);
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// #else
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// xPortInstallInterruptHandler(xtopologyp->scugic_emac_intr,
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// ( Xil_InterruptHandler ) XEmacPs_IntrHandler,
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// (void *)&xemacpsif->emacps);
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#if !NO_SYS
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#ifdef SDT
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xPortInstallInterruptHandler(xemacpsif->emacps.Config.IntrId,
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( Xil_InterruptHandler ) XEmacPs_IntrHandler,
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(void *)&xemacpsif->emacps);
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#else
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xPortInstallInterruptHandler(xtopologyp->scugic_emac_intr,
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( Xil_InterruptHandler ) XEmacPs_IntrHandler,
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(void *)&xemacpsif->emacps);
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// #endif
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// #else
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#endif
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#else
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#ifndef SDT
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/*
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* Connect the device driver handler that will be called when an
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@ -830,7 +823,7 @@ XStatus init_dma(struct xemac_s *xemac)
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(Xil_ExceptionHandler)XEmacPs_IntrHandler,
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(void *)&xemacpsif->emacps);
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#endif
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// #endif
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#endif
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/*
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* Enable the interrupt for emacps.
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*/
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