xilinx eth lwip version xilinx_v2024.1

This commit is contained in:
2024-10-14 14:06:49 +02:00
parent 65299e46c4
commit fd2c5a544f
16 changed files with 34 additions and 662 deletions

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@ -1,12 +0,0 @@
target_sources(lwip_xil PRIVATE
xadapter.c
xpqueue.c
xemacpsif_dma.c
xemacpsif_physpeed.c
xemacpsif_hw.c
xemacpsif.c
topology.c
)
target_include_directories(lwip_xil PRIVATE ${CMAKE_CURRENT_SOURCE_DIR})

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@ -1,37 +0,0 @@
#include "netif/xtopology.h"
// struct xtopology_t {
// UINTPTR emac_baseaddr;
// enum xemac_types emac_type;
// #ifndef SDT
// UINTPTR intc_baseaddr;
// unsigned intc_emac_intr; /* valid only for xemac_type_xps_emaclite */
// UINTPTR scugic_baseaddr; /* valid only for Zynq */
// unsigned scugic_emac_intr; /* valid only for GEM */
// #endif
// };
int xtopology_n_emacs = 2;
struct xtopology_t xtopology[] = {
{
0xE000B000,
xemac_type_emacps,
#ifndef SDT
0,
0,
0xF8F00100,
0x36
#endif
},
{
0xE000C000,
xemac_type_emacps,
#ifndef SDT
0,
0,
0xF8F00100,
0x4D
#endif
}
};

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@ -279,14 +279,6 @@ s32_t xemacpsif_input(struct netif *netif)
/* points to packet payload, which starts with an Ethernet header */
ethhdr = p->payload;
// xil_printf("\n %p %i\n",p->payload, p->len);
// for (int j = 0; j < 6; j++) {
// for (int i = 0; i < 8; i++) {
// xil_printf(" %02x", *((uint8_t *)(p->payload) + i + j * 8 ) );
// }
// xil_printf("\n");
// }
#if LINK_STATS
lwip_stats.link.recv++;
#endif /* LINK_STATS */
@ -313,11 +305,6 @@ s32_t xemacpsif_input(struct netif *netif)
break;
default:
//TODO debug
// for (int i = 0; i < 14; i++) {
// xil_printf(" %02x", *((uint8_t *)(p->payload) + i ) );
// }
// xil_printf("invalid eth type\n");
pbuf_free(p);
p = NULL;
break;

View File

@ -538,7 +538,6 @@ void emacps_recv_handler(void *arg)
}
for (k = 0, curbdptr=rxbdset; k < bd_processed; k++) {
// outbyte('r');
bdindex = XEMACPS_BD_TO_INDEX(rxring, curbdptr);
p = (struct pbuf *)rx_pbufs_storage[index + bdindex];
@ -553,8 +552,6 @@ void emacps_recv_handler(void *arg)
#endif
pbuf_realloc(p, rx_bytes);
// xil_printf("reading bd index %i bdindex %i p %p payload %p len %i\n", index, bdindex, p, p->payload, p->len);
/* Invalidate RX frame before queuing to handle
* L1 cache prefetch conditions on any architecture.
*/
@ -579,12 +576,10 @@ void emacps_recv_handler(void *arg)
setup_rx_bds(xemacpsif, rxring);
}
#if !NO_SYS
// BaseType_t xHigherPriorityTaskWoken;
// xSemaphoreGiveFromISR(xemac->sem_rx_data_available.sem, &xHigherPriorityTaskWoken);
// portYIELD_FROM_ISR(xHigherPriorityTaskWoken); //TODO delay this?
sys_sem_signal(&xemac->sem_rx_data_available);
xInsideISR--;
#endif
return;
}
@ -777,8 +772,6 @@ XStatus init_dma(struct xemac_s *xemac)
#endif
XEmacPs_BdSetAddressRx(rxbd, (UINTPTR)p->payload);
xil_printf("setting bd index %i bdindex %i p %p payload %p\n", index, bdindex, p, p->payload);
rx_pbufs_storage[index + bdindex] = (UINTPTR)p;
}
XEmacPs_SetQueuePtr(&(xemacpsif->emacps), xemacpsif->emacps.RxBdRing.BaseBdAddr, 0, XEMACPS_RECV);
@ -808,18 +801,18 @@ XStatus init_dma(struct xemac_s *xemac)
XEmacPs_Out32((xemacpsif->emacps.Config.BaseAddress + XEMACPS_TXQBASE_OFFSET),
(UINTPTR)bdtxterminate);
}
// #if !NO_SYS
// #ifdef SDT
// xPortInstallInterruptHandler(xemacpsif->emacps.Config.IntrId,
// ( Xil_InterruptHandler ) XEmacPs_IntrHandler,
// (void *)&xemacpsif->emacps);
// #else
// xPortInstallInterruptHandler(xtopologyp->scugic_emac_intr,
// ( Xil_InterruptHandler ) XEmacPs_IntrHandler,
// (void *)&xemacpsif->emacps);
#if !NO_SYS
#ifdef SDT
xPortInstallInterruptHandler(xemacpsif->emacps.Config.IntrId,
( Xil_InterruptHandler ) XEmacPs_IntrHandler,
(void *)&xemacpsif->emacps);
#else
xPortInstallInterruptHandler(xtopologyp->scugic_emac_intr,
( Xil_InterruptHandler ) XEmacPs_IntrHandler,
(void *)&xemacpsif->emacps);
// #endif
// #else
#endif
#else
#ifndef SDT
/*
* Connect the device driver handler that will be called when an
@ -830,7 +823,7 @@ XStatus init_dma(struct xemac_s *xemac)
(Xil_ExceptionHandler)XEmacPs_IntrHandler,
(void *)&xemacpsif->emacps);
#endif
// #endif
#endif
/*
* Enable the interrupt for emacps.
*/