forked from ROMEO/obsw
498 lines
16 KiB
C
498 lines
16 KiB
C
/******************************************************************************
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* Copyright (c) 2021 - 2022 Xilinx, Inc. All rights reserved.
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* SPDX-License-Identifier: MIT
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******************************************************************************/
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#ifndef XPARAMETERS_H /* prevent circular inclusions */
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#define XPARAMETERS_H /* by using protection macros */
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/* Definition for CPU ID */
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#define XPAR_CPU_ID 0U
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/* Definitions for peripheral PS7_CORTEXA9_0 */
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#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
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#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687
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/******************************************************************/
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#include "xparameters_ps.h"
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#define STDIN_BASEADDRESS 0xE0000000
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#define STDOUT_BASEADDRESS 0xE0000000
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/******************************************************************/
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/* Platform specific definitions */
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#define PLATFORM_ZYNQ
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/* Definitions for sleep timer configuration */
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#define XSLEEP_TIMER_IS_DEFAULT_TIMER
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/******************************************************************/
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/* Definitions for peripheral PS7_DDR_0 */
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#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
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#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
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/******************************************************************/
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/* Definitions for driver DEVCFG */
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#define XPAR_XDCFG_NUM_INSTANCES 1U
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/* Definitions for peripheral PS7_DEV_CFG_0 */
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#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0U
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#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000U
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#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF80070FFU
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
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#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
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#define XPAR_XDCFG_0_BASEADDR 0xF8007000U
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#define XPAR_XDCFG_0_HIGHADDR 0xF80070FFU
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/******************************************************************/
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/* Definitions for driver DMAPS */
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#define XPAR_XDMAPS_NUM_INSTANCES 2
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/* Definitions for peripheral PS7_DMA_NS */
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#define XPAR_PS7_DMA_NS_DEVICE_ID 0
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#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
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#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF
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/* Definitions for peripheral PS7_DMA_S */
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#define XPAR_PS7_DMA_S_DEVICE_ID 1
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#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
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#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_DMA_NS */
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#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
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#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
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#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF
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/* Canonical definitions for peripheral PS7_DMA_S */
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#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
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#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
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#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF
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/******************************************************************/
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/* Definitions for driver EMACPS */
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#define XPAR_XEMACPS_NUM_INSTANCES 1
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/* Definitions for peripheral PS7_ETHERNET_0 */
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#define XPAR_PS7_ETHERNET_0_DEVICE_ID 0
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#define XPAR_PS7_ETHERNET_0_BASEADDR 0xE000B000
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#define XPAR_PS7_ETHERNET_0_HIGHADDR 0xE000BFFF
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#define XPAR_PS7_ETHERNET_0_ENET_CLK_FREQ_HZ 125000000
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#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV0 8
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#define XPAR_PS7_ETHERNET_0_ENET_SLCR_1000MBPS_DIV1 1
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#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV0 8
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#define XPAR_PS7_ETHERNET_0_ENET_SLCR_100MBPS_DIV1 5
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#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV0 8
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#define XPAR_PS7_ETHERNET_0_ENET_SLCR_10MBPS_DIV1 50
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#define XPAR_PS7_ETHERNET_0_ENET_TSU_CLK_FREQ_HZ 0
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/******************************************************************/
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#define XPAR_PS7_ETHERNET_0_IS_CACHE_COHERENT 0
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#define XPAR_XEMACPS_0_IS_CACHE_COHERENT 0
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/* Canonical definitions for peripheral PS7_ETHERNET_0 */
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#define XPAR_XEMACPS_0_DEVICE_ID XPAR_PS7_ETHERNET_0_DEVICE_ID
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#define XPAR_XEMACPS_0_BASEADDR 0xE000B000
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#define XPAR_XEMACPS_0_HIGHADDR 0xE000BFFF
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#define XPAR_XEMACPS_0_ENET_CLK_FREQ_HZ 125000000
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#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV0 8
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#define XPAR_XEMACPS_0_ENET_SLCR_1000Mbps_DIV1 1
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#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV0 8
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#define XPAR_XEMACPS_0_ENET_SLCR_100Mbps_DIV1 5
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#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV0 8
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#define XPAR_XEMACPS_0_ENET_SLCR_10Mbps_DIV1 50
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#define XPAR_XEMACPS_0_ENET_TSU_CLK_FREQ_HZ 0
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/******************************************************************/
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/* Definitions for peripheral PS7_AFI_0 */
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#define XPAR_PS7_AFI_0_S_AXI_BASEADDR 0xF8008000
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#define XPAR_PS7_AFI_0_S_AXI_HIGHADDR 0xF8008FFF
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/* Definitions for peripheral PS7_AFI_1 */
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#define XPAR_PS7_AFI_1_S_AXI_BASEADDR 0xF8009000
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#define XPAR_PS7_AFI_1_S_AXI_HIGHADDR 0xF8009FFF
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/* Definitions for peripheral PS7_AFI_2 */
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#define XPAR_PS7_AFI_2_S_AXI_BASEADDR 0xF800A000
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#define XPAR_PS7_AFI_2_S_AXI_HIGHADDR 0xF800AFFF
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/* Definitions for peripheral PS7_AFI_3 */
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#define XPAR_PS7_AFI_3_S_AXI_BASEADDR 0xF800B000
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#define XPAR_PS7_AFI_3_S_AXI_HIGHADDR 0xF800BFFF
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/* Definitions for peripheral PS7_DDRC_0 */
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#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
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#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF
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/* Definitions for peripheral PS7_GLOBALTIMER_0 */
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#define XPAR_PS7_GLOBALTIMER_0_S_AXI_BASEADDR 0xF8F00200
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#define XPAR_PS7_GLOBALTIMER_0_S_AXI_HIGHADDR 0xF8F002FF
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/* Definitions for peripheral PS7_GPV_0 */
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#define XPAR_PS7_GPV_0_S_AXI_BASEADDR 0xF8900000
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#define XPAR_PS7_GPV_0_S_AXI_HIGHADDR 0xF89FFFFF
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/* Definitions for peripheral PS7_INTC_DIST_0 */
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#define XPAR_PS7_INTC_DIST_0_S_AXI_BASEADDR 0xF8F01000
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#define XPAR_PS7_INTC_DIST_0_S_AXI_HIGHADDR 0xF8F01FFF
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/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
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#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
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#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF
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/* Definitions for peripheral PS7_L2CACHEC_0 */
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#define XPAR_PS7_L2CACHEC_0_S_AXI_BASEADDR 0xF8F02000
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#define XPAR_PS7_L2CACHEC_0_S_AXI_HIGHADDR 0xF8F02FFF
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/* Definitions for peripheral PS7_OCMC_0 */
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#define XPAR_PS7_OCMC_0_S_AXI_BASEADDR 0xF800C000
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#define XPAR_PS7_OCMC_0_S_AXI_HIGHADDR 0xF800CFFF
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/* Definitions for peripheral PS7_PL310_0 */
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#define XPAR_PS7_PL310_0_S_AXI_BASEADDR 0xF8F02000
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#define XPAR_PS7_PL310_0_S_AXI_HIGHADDR 0xF8F02FFF
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/* Definitions for peripheral PS7_PMU_0 */
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#define XPAR_PS7_PMU_0_S_AXI_BASEADDR 0xF8891000
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#define XPAR_PS7_PMU_0_S_AXI_HIGHADDR 0xF8891FFF
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#define XPAR_PS7_PMU_0_PMU1_S_AXI_BASEADDR 0xF8893000
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#define XPAR_PS7_PMU_0_PMU1_S_AXI_HIGHADDR 0xF8893FFF
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/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
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#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
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#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF
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/* Definitions for peripheral PS7_RAM_0 */
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#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
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#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0003FFFF
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/* Definitions for peripheral PS7_RAM_1 */
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#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFC0000
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#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFFFF
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/* Definitions for peripheral PS7_SCUC_0 */
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#define XPAR_PS7_SCUC_0_S_AXI_BASEADDR 0xF8F00000
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#define XPAR_PS7_SCUC_0_S_AXI_HIGHADDR 0xF8F000FC
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/* Definitions for peripheral PS7_SLCR_0 */
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#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
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#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF
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/******************************************************************/
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/* Definitions for driver GPIOPS */
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#define XPAR_XGPIOPS_NUM_INSTANCES 1
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/* Definitions for peripheral PS7_GPIO_0 */
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#define XPAR_PS7_GPIO_0_DEVICE_ID 0
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#define XPAR_PS7_GPIO_0_BASEADDR 0xE000A000
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#define XPAR_PS7_GPIO_0_HIGHADDR 0xE000AFFF
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_GPIO_0 */
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#define XPAR_XGPIOPS_0_DEVICE_ID XPAR_PS7_GPIO_0_DEVICE_ID
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#define XPAR_XGPIOPS_0_BASEADDR 0xE000A000
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#define XPAR_XGPIOPS_0_HIGHADDR 0xE000AFFF
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/******************************************************************/
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/* Definitions for driver QSPIPS */
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#define XPAR_XQSPIPS_NUM_INSTANCES 1
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/* Definitions for peripheral PS7_QSPI_0 */
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#define XPAR_PS7_QSPI_0_DEVICE_ID 0
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#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
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#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
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#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000
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#define XPAR_PS7_QSPI_0_QSPI_MODE 0
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#define XPAR_PS7_QSPI_0_QSPI_BUS_WIDTH 2
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_QSPI_0 */
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#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
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#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
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#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
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#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000
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#define XPAR_XQSPIPS_0_QSPI_MODE 0
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#define XPAR_XQSPIPS_0_QSPI_BUS_WIDTH 2
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/******************************************************************/
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/* Definitions for driver SCUGIC */
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#define XPAR_XSCUGIC_NUM_INSTANCES 1U
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/* Definitions for peripheral PS7_SCUGIC_0 */
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#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0U
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#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100U
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#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FFU
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#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_SCUGIC_0 */
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#define XPAR_SCUGIC_0_DEVICE_ID 0U
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#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100U
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#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FFU
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#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000U
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/******************************************************************/
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/* Definitions for driver SCUTIMER */
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#define XPAR_XSCUTIMER_NUM_INSTANCES 1
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/* Definitions for peripheral PS7_SCUTIMER_0 */
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#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
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#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
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#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
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#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
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#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
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#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F
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/******************************************************************/
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/* Definitions for driver SCUWDT */
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#define XPAR_XSCUWDT_NUM_INSTANCES 1
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/* Definitions for peripheral PS7_SCUWDT_0 */
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#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
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#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
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#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_SCUWDT_0 */
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#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
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#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
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#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF
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/******************************************************************/
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/* Definitions for driver SDPS */
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#define XPAR_XSDPS_NUM_INSTANCES 1
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/* Definitions for peripheral PS7_SD_0 */
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#define XPAR_PS7_SD_0_DEVICE_ID 0
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#define XPAR_PS7_SD_0_BASEADDR 0xE0100000
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#define XPAR_PS7_SD_0_HIGHADDR 0xE0100FFF
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#define XPAR_PS7_SD_0_SDIO_CLK_FREQ_HZ 50000000
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#define XPAR_PS7_SD_0_HAS_CD 1
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#define XPAR_PS7_SD_0_HAS_WP 1
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#define XPAR_PS7_SD_0_BUS_WIDTH 0
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#define XPAR_PS7_SD_0_MIO_BANK 0
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#define XPAR_PS7_SD_0_HAS_EMIO 0
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#define XPAR_PS7_SD_0_SLOT_TYPE 0
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#define XPAR_PS7_SD_0_CLK_50_SDR_ITAP_DLY 0
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#define XPAR_PS7_SD_0_CLK_50_SDR_OTAP_DLY 0
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#define XPAR_PS7_SD_0_CLK_50_DDR_ITAP_DLY 0
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#define XPAR_PS7_SD_0_CLK_50_DDR_OTAP_DLY 0
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#define XPAR_PS7_SD_0_CLK_100_SDR_OTAP_DLY 0
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#define XPAR_PS7_SD_0_CLK_200_SDR_OTAP_DLY 0
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/******************************************************************/
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#define XPAR_PS7_SD_0_IS_CACHE_COHERENT 0
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/* Canonical definitions for peripheral PS7_SD_0 */
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#define XPAR_XSDPS_0_DEVICE_ID XPAR_PS7_SD_0_DEVICE_ID
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#define XPAR_XSDPS_0_BASEADDR 0xE0100000
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#define XPAR_XSDPS_0_HIGHADDR 0xE0100FFF
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#define XPAR_XSDPS_0_SDIO_CLK_FREQ_HZ 50000000
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#define XPAR_XSDPS_0_HAS_CD 1
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#define XPAR_XSDPS_0_HAS_WP 1
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#define XPAR_XSDPS_0_BUS_WIDTH 0
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#define XPAR_XSDPS_0_MIO_BANK 0
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#define XPAR_XSDPS_0_HAS_EMIO 0
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#define XPAR_XSDPS_0_SLOT_TYPE 0
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#define XPAR_XSDPS_0_IS_CACHE_COHERENT 0
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#define XPAR_XSDPS_0_CLK_50_SDR_ITAP_DLY 0
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#define XPAR_XSDPS_0_CLK_50_SDR_OTAP_DLY 0
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#define XPAR_XSDPS_0_CLK_50_DDR_ITAP_DLY 0
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#define XPAR_XSDPS_0_CLK_50_DDR_OTAP_DLY 0
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#define XPAR_XSDPS_0_CLK_100_SDR_OTAP_DLY 0
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#define XPAR_XSDPS_0_CLK_200_SDR_OTAP_DLY 0
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/******************************************************************/
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/* Definitions for driver TTCPS */
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#define XPAR_XTTCPS_NUM_INSTANCES 3U
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/* Definitions for peripheral PS7_TTC_0 */
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#define XPAR_PS7_TTC_0_DEVICE_ID 0U
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#define XPAR_PS7_TTC_0_BASEADDR 0XF8001000U
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#define XPAR_PS7_TTC_0_TTC_CLK_FREQ_HZ 111111115U
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#define XPAR_PS7_TTC_0_TTC_CLK_CLKSRC 0U
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#define XPAR_PS7_TTC_1_DEVICE_ID 1U
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#define XPAR_PS7_TTC_1_BASEADDR 0XF8001004U
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#define XPAR_PS7_TTC_1_TTC_CLK_FREQ_HZ 111111115U
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#define XPAR_PS7_TTC_1_TTC_CLK_CLKSRC 0U
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#define XPAR_PS7_TTC_2_DEVICE_ID 2U
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#define XPAR_PS7_TTC_2_BASEADDR 0XF8001008U
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#define XPAR_PS7_TTC_2_TTC_CLK_FREQ_HZ 111111115U
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#define XPAR_PS7_TTC_2_TTC_CLK_CLKSRC 0U
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_TTC_0 */
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#define XPAR_XTTCPS_0_DEVICE_ID XPAR_PS7_TTC_0_DEVICE_ID
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#define XPAR_XTTCPS_0_BASEADDR 0xF8001000U
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#define XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 111111115U
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#define XPAR_XTTCPS_0_TTC_CLK_CLKSRC 0U
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#define XPAR_XTTCPS_1_DEVICE_ID XPAR_PS7_TTC_1_DEVICE_ID
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#define XPAR_XTTCPS_1_BASEADDR 0xF8001004U
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#define XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 111111115U
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#define XPAR_XTTCPS_1_TTC_CLK_CLKSRC 0U
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#define XPAR_XTTCPS_2_DEVICE_ID XPAR_PS7_TTC_2_DEVICE_ID
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#define XPAR_XTTCPS_2_BASEADDR 0xF8001008U
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#define XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 111111115U
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#define XPAR_XTTCPS_2_TTC_CLK_CLKSRC 0U
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/******************************************************************/
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/* Canonical definitions for peripheral UARTLITE */
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#define XPAR_XUARTLITE_NUM_INSTANCES 1 /* Number of instances */
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#define XPAR_UARTLITE_0_DEVICE_ID 30 /* Device ID for instance */
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#define XPAR_UARTLITE_0_BASEADDR 0xA0020000 /* Device base address */
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#define XPAR_UARTLITE_0_BAUDRATE 19200 /* Baud rate */
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#define XPAR_UARTLITE_0_USE_PARITY FALSE /* Parity generator enabled */
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#define XPAR_UARTLITE_0_ODD_PARITY FALSE /* Type of parity generated */
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#define XPAR_UARTLITE_0_DATA_BITS 8 /* Data bits */
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/* Definitions for driver UARTPS */
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#define XPAR_XUARTPS_NUM_INSTANCES 1
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/* Definitions for peripheral PS7_UART_1 */
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#define XPAR_PS7_UART_1_DEVICE_ID 0
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#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
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#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
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#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
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#define XPAR_PS7_UART_1_HAS_MODEM 0
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_UART_1 */
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#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
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#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
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#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
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#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000
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#define XPAR_XUARTPS_0_HAS_MODEM 0
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/******************************************************************/
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/* Definitions for driver USBPS */
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#define XPAR_XUSBPS_NUM_INSTANCES 1
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/* Definitions for peripheral PS7_USB_0 */
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#define XPAR_PS7_USB_0_DEVICE_ID 0
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#define XPAR_PS7_USB_0_BASEADDR 0xE0002000
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#define XPAR_PS7_USB_0_HIGHADDR 0xE0002FFF
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_USB_0 */
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#define XPAR_XUSBPS_0_DEVICE_ID XPAR_PS7_USB_0_DEVICE_ID
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#define XPAR_XUSBPS_0_BASEADDR 0xE0002000
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#define XPAR_XUSBPS_0_HIGHADDR 0xE0002FFF
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/******************************************************************/
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/* Definitions for driver XADCPS */
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#define XPAR_XADCPS_NUM_INSTANCES 1
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/* Definitions for peripheral PS7_XADC_0 */
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#define XPAR_PS7_XADC_0_DEVICE_ID 0
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#define XPAR_PS7_XADC_0_BASEADDR 0xF8007100
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#define XPAR_PS7_XADC_0_HIGHADDR 0xF8007120
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/******************************************************************/
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/* Canonical definitions for peripheral PS7_XADC_0 */
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#define XPAR_XADCPS_0_DEVICE_ID XPAR_PS7_XADC_0_DEVICE_ID
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#define XPAR_XADCPS_0_BASEADDR 0xF8007100
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#define XPAR_XADCPS_0_HIGHADDR 0xF8007120
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/******************************************************************/
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/* Xilinx FAT File System Library (XilFFs) User Settings */
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#define FILE_SYSTEM_INTERFACE_SD
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#define FILE_SYSTEM_USE_MKFS
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#define FILE_SYSTEM_NUM_LOGIC_VOL 2
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#define FILE_SYSTEM_USE_STRFUNC 0
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#define FILE_SYSTEM_SET_FS_RPATH 0
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#define FILE_SYSTEM_WORD_ACCESS
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#endif /* end of protection macro */
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