forked from ROMEO/obsw
91 lines
3.0 KiB
C
91 lines
3.0 KiB
C
#include <stdint.h>
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#include "FreeRTOS.h"
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#include "queue.h"
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#include <xscugic.h>
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#include <xuartps.h>
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#undef XUARTPS_IXR_RXOVR
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#define XUARTPS_IXR_RXOVR 0x00000020U /**< Rx Overrun error interrupt */
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#define XUARTPS_IXR_RTRIG 0x00000001U /**< RX FIFO trigger interrupt. */
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extern XScuGic xInterruptController; /* Interrupt controller instance */
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uint8_t uart0_receive_buffer[1024 * 1];
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StaticQueue_t uart0_static_queue;
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QueueHandle_t uart0_receive_queue;
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/** this is based on XUartPs_InterruptHandler() in xuartps_intr.c*/
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void uart0_handle_interrupt(void *) {
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u32 IsrStatus;
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/*
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* Read the interrupt ID register to determine which
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* interrupt is active
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*/
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IsrStatus = XUartPs_ReadReg(XPS_UART0_BASEADDR, XUARTPS_IMR_OFFSET);
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IsrStatus &= XUartPs_ReadReg(XPS_UART0_BASEADDR, XUARTPS_ISR_OFFSET);
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// Onlx RX intterupts are enabled
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// We do not care which interrupt actually triggered, just get all bytes
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// available into the stack
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uint8_t RecievedByte;
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BaseType_t xHigherPriorityTaskWoken;
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while (XUartPs_IsReceiveData(STDIN_BASEADDRESS)) {
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RecievedByte = XUartPs_ReadReg(STDIN_BASEADDRESS, XUARTPS_FIFO_OFFSET);
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xQueueSendToBackFromISR(uart0_receive_queue, &RecievedByte,
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&xHigherPriorityTaskWoken);
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}
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/* Clear the interrupt status. */
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XUartPs_WriteReg(STDIN_BASEADDRESS, XUARTPS_ISR_OFFSET, IsrStatus);
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/* directly yield if sending to the queue woke something in ourselves */
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portYIELD_FROM_ISR(xHigherPriorityTaskWoken);
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}
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void uart0_enable_receiver() {
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uart0_receive_queue =
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xQueueCreateStatic(sizeof(uart0_receive_buffer), 1, uart0_receive_buffer,
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&uart0_static_queue);
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/* Install the UART Interrupt handler. */
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BaseType_t xStatus =
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XScuGic_Connect(&xInterruptController, XPAR_XUARTPS_0_INTR,
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(Xil_ExceptionHandler)uart0_handle_interrupt, NULL);
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configASSERT(xStatus == XST_SUCCESS);
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(void)xStatus; /* Remove compiler warning if configASSERT() is not defined. */
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// Set trigger level to 62 of 64 bytes, giving interrupt some time to react
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XUartPs_WriteReg(XPS_UART0_BASEADDR, XUARTPS_RXWM_OFFSET, 62);
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// Setting the rx timeout to n*4 -1 bits
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XUartPs_WriteReg(XPS_UART0_BASEADDR, XUARTPS_RXTOUT_OFFSET, 50);
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// enable UART Interrupts
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u32 mask = XUARTPS_IXR_RTRIG | XUARTPS_IXR_RXOVR | XUARTPS_IXR_RXFULL |
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XUARTPS_IXR_TOUT;
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/* Write the mask to the IER Register */
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XUartPs_WriteReg(XPS_UART0_BASEADDR, XUARTPS_IER_OFFSET, mask);
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/* Write the inverse of the Mask to the IDR register */
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XUartPs_WriteReg(XPS_UART0_BASEADDR, XUARTPS_IDR_OFFSET, (~mask));
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/* Enable the interrupt for the UART0 in the interrupt controller. */
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XScuGic_Enable(&xInterruptController, XPAR_XUARTPS_0_INTR);
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}
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int uart0_read(char *ptr, int len) {
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int received = 0;
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while (len > 0) {
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BaseType_t result = xQueueReceive(uart0_receive_queue, ptr, 0);
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if (result == pdFAIL) {
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return received;
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}
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received++;
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ptr++;
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len--;
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}
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return received;
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} |