266 lines
6.9 KiB
Rust
266 lines
6.9 KiB
Rust
//! # AXI UART Lite v2.0 driver
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//!
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//! This is a native Rust driver for the AMD AXI UART Lite v2.0 IP core.
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//!
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//! # Features
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//!
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//! If asynchronous TX operations are used, the number of wakers which defaults to 1 waker can
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//! also be configured. The [tx_async] module provides more details on the meaning of this number.
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//!
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//! - `1-waker` which is also a `default` feature
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//! - `2-wakers`
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//! - `4-wakers`
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//! - `8-wakers`
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//! - `16-wakers`
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//! - `32-wakers`
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#![no_std]
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#![cfg_attr(docsrs, feature(doc_cfg))]
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use core::convert::Infallible;
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use registers::Control;
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pub mod registers;
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pub mod tx;
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pub use tx::*;
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pub mod rx;
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pub use rx::*;
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pub mod tx_async;
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pub use tx_async::*;
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pub const FIFO_DEPTH: usize = 16;
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#[derive(Debug, Default, Copy, Clone, Eq, PartialEq)]
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pub struct RxErrorsCounted {
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parity: u8,
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frame: u8,
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overrun: u8,
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}
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impl RxErrorsCounted {
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pub const fn new() -> Self {
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Self {
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parity: 0,
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frame: 0,
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overrun: 0,
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}
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}
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pub const fn parity(&self) -> u8 {
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self.parity
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}
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pub const fn frame(&self) -> u8 {
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self.frame
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}
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pub const fn overrun(&self) -> u8 {
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self.overrun
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}
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pub fn has_errors(&self) -> bool {
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self.parity > 0 || self.frame > 0 || self.overrun > 0
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}
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}
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pub struct AxiUartlite {
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rx: Rx,
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tx: Tx,
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errors: RxErrorsCounted,
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}
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impl AxiUartlite {
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/// Create a new AXI UART Lite peripheral driver.
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///
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/// # Safety
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///
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/// - The `base_addr` must be a valid memory-mapped register address of an AXI UART Lite peripheral.
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/// - Dereferencing an invalid or misaligned address results in **undefined behavior**.
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/// - The caller must ensure that no other code concurrently modifies the same peripheral registers
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/// in an unsynchronized manner to prevent data races.
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/// - This function does not enforce uniqueness of driver instances. Creating multiple instances
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/// with the same `base_addr` can lead to unintended behavior if not externally synchronized.
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/// - The driver performs **volatile** reads and writes to the provided address.
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pub const unsafe fn new(base_addr: u32) -> Self {
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let regs = unsafe { registers::Registers::new_mmio_at(base_addr as usize) };
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Self {
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rx: Rx {
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regs: unsafe { regs.clone() },
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errors: None,
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},
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tx: Tx { regs, errors: None },
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errors: RxErrorsCounted::new(),
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}
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}
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#[inline(always)]
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pub const fn regs(&mut self) -> &mut registers::MmioRegisters<'static> {
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&mut self.tx.regs
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}
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/// Write into the UART Lite.
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///
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/// Returns [nb::Error::WouldBlock] if the TX FIFO is full.
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#[inline]
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pub fn write_fifo(&mut self, data: u8) -> nb::Result<(), Infallible> {
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self.tx.write_fifo(data).unwrap();
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if let Some(errors) = self.tx.errors {
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self.handle_status_reg_errors(errors);
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}
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Ok(())
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}
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/// Write into the FIFO without checking the FIFO fill status.
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///
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/// This can be useful to completely fill the FIFO if it is known to be empty.
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#[inline(always)]
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pub fn write_fifo_unchecked(&mut self, data: u8) {
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self.tx.write_fifo_unchecked(data);
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}
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#[inline]
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pub fn read_fifo(&mut self) -> nb::Result<u8, Infallible> {
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let val = self.rx.read_fifo().unwrap();
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if let Some(errors) = self.rx.errors {
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self.handle_status_reg_errors(errors);
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}
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Ok(val)
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}
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#[inline(always)]
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pub fn read_fifo_unchecked(&mut self) -> u8 {
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self.rx.read_fifo_unchecked()
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}
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// TODO: Make this non-mut as soon as pure reads are available
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#[inline(always)]
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pub fn tx_fifo_empty(&mut self) -> bool {
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self.tx.fifo_empty()
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}
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// TODO: Make this non-mut as soon as pure reads are available
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#[inline(always)]
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pub fn tx_fifo_full(&mut self) -> bool {
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self.tx.fifo_full()
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}
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// TODO: Make this non-mut as soon as pure reads are available
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#[inline(always)]
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pub fn rx_has_data(&mut self) -> bool {
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self.rx.has_data()
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}
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/// Read the error counters and also resets them.
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pub fn read_and_clear_errors(&mut self) -> RxErrorsCounted {
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let errors = self.errors;
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self.errors = RxErrorsCounted::new();
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errors
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}
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#[inline(always)]
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fn handle_status_reg_errors(&mut self, errors: RxErrors) {
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if errors.frame() {
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self.errors.frame = self.errors.frame.saturating_add(1);
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}
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if errors.parity() {
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self.errors.parity = self.errors.parity.saturating_add(1);
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}
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if errors.overrun() {
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self.errors.overrun = self.errors.overrun.saturating_add(1);
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}
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}
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#[inline]
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pub fn reset_rx_fifo(&mut self) {
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self.regs().write_ctrl_reg(
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Control::builder()
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.with_enable_interrupt(false)
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.with_reset_rx_fifo(true)
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.with_reset_tx_fifo(false)
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.build(),
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);
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}
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#[inline]
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pub fn reset_tx_fifo(&mut self) {
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self.regs().write_ctrl_reg(
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Control::builder()
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.with_enable_interrupt(false)
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.with_reset_rx_fifo(false)
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.with_reset_tx_fifo(true)
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.build(),
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);
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}
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#[inline]
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pub fn split(self) -> (Tx, Rx) {
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(self.tx, self.rx)
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}
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#[inline]
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pub fn enable_interrupt(&mut self) {
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self.regs().write_ctrl_reg(
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Control::builder()
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.with_enable_interrupt(true)
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.with_reset_rx_fifo(false)
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.with_reset_tx_fifo(false)
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.build(),
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);
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}
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#[inline]
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pub fn disable_interrupt(&mut self) {
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self.regs().write_ctrl_reg(
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Control::builder()
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.with_enable_interrupt(false)
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.with_reset_rx_fifo(false)
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.with_reset_tx_fifo(false)
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.build(),
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);
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}
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}
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impl embedded_hal_nb::serial::ErrorType for AxiUartlite {
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type Error = Infallible;
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}
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impl embedded_hal_nb::serial::Write for AxiUartlite {
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#[inline]
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fn write(&mut self, word: u8) -> nb::Result<(), Self::Error> {
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self.tx.write(word)
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}
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#[inline]
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fn flush(&mut self) -> nb::Result<(), Self::Error> {
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self.tx.flush()
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}
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}
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impl embedded_hal_nb::serial::Read for AxiUartlite {
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#[inline]
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fn read(&mut self) -> nb::Result<u8, Self::Error> {
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self.rx.read()
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}
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}
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impl embedded_io::ErrorType for AxiUartlite {
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type Error = Infallible;
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}
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impl embedded_io::Read for AxiUartlite {
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fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
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self.rx.read(buf)
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}
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}
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impl embedded_io::Write for AxiUartlite {
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fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
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self.tx.write(buf)
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}
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fn flush(&mut self) -> Result<(), Self::Error> {
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self.tx.flush()
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}
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}
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