120 lines
4.3 KiB
Plaintext
120 lines
4.3 KiB
Plaintext
/* Taken from https://github.com/stm32-rs/stm32h7xx-hal/pull/299, adapted slightly to work with */
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/* flip-link */
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MEMORY
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{
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/* This file is intended for parts in the STM32H743/743v/753/753v families (RM0433), */
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/* with the exception of the STM32H742/742v parts which have a different RAM layout. */
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/* - FLASH and RAM are mandatory memory sections. */
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/* - The sum of all non-FLASH sections must add to 1060K total device RAM. */
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/* - The FLASH section size must match your device, see table below. */
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/* FLASH */
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/* Flash is divided in two independent banks (except 750xB). */
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/* Select the appropriate FLASH size for your device. */
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/* - STM32H750xB 128K (only FLASH1) */
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/* - STM32H750xB 1M (512K + 512K) */
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/* - STM32H743xI/753xI 2M ( 1M + 1M) */
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FLASH1 : ORIGIN = 0x08000000, LENGTH = 1M
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FLASH2 : ORIGIN = 0x08100000, LENGTH = 1M
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/* Data TCM */
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/* - Two contiguous 64KB RAMs. */
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/* - Used for interrupt handlers, stacks and general RAM. */
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/* - Zero wait-states. */
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/* - The DTCM is taken as the origin of the base ram. (See below.) */
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/* This is also where the interrupt table and such will live, */
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/* which is required for deterministic performance. */
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/* Need a region called RAM */
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/* DTCM : ORIGIN = 0x20000000, LENGTH = 128K */
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RAM : ORIGIN = 0x20000000, LENGTH = 128K
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/* Instruction TCM */
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/* - Used for latency-critical interrupt handlers etc. */
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/* - Zero wait-states. */
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ITCM : ORIGIN = 0x00000000, LENGTH = 64K
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/* AXI SRAM */
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/* - AXISRAM is in D1 and accessible by all system masters except BDMA. */
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/* - Suitable for application data not stored in DTCM. */
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/* - Zero wait-states. */
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AXISRAM : ORIGIN = 0x24000000, LENGTH = 512K
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/* AHB SRAM */
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/* - SRAM1-3 are in D2 and accessible by all system masters except BDMA. */
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/* Suitable for use as DMA buffers. */
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/* - SRAM4 is in D3 and additionally accessible by the BDMA. Used for BDMA */
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/* buffers, for storing application data in lower-power modes. */
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/* - Zero wait-states. */
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SRAM1 : ORIGIN = 0x30000000, LENGTH = 128K
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SRAM2 : ORIGIN = 0x30020000, LENGTH = 128K
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SRAM3 : ORIGIN = 0x30040000, LENGTH = 32K
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SRAM4 : ORIGIN = 0x38000000, LENGTH = 64K
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/* Backup SRAM */
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BSRAM : ORIGIN = 0x38800000, LENGTH = 4K
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}
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/*
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/* Assign the memory regions defined above for use. */
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/*
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/* Provide the mandatory FLASH and RAM definitions for cortex-m-rt's linker script. */
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/* These do not work with flip-link */
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REGION_ALIAS(FLASH, FLASH1);
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/* REGION_ALIAS(RAM, DTCM); */
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/* The location of the stack can be overridden using the `_stack_start` symbol. */
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/* - Set the stack location at the end of RAM, using all remaining space. */
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_stack_start = ORIGIN(RAM) + LENGTH(RAM);
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/* The location of the .text section can be overridden using the */
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/* `_stext` symbol. By default it will place after .vector_table. */
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/* _stext = ORIGIN(FLASH) + 0x40c; */
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/* Define sections for placing symbols into the extra memory regions above. */
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/* This makes them accessible from code. */
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/* - ITCM, DTCM and AXISRAM connect to a 64-bit wide bus -> align to 8 bytes. */
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/* - All other memories connect to a 32-bit wide bus -> align to 4 bytes. */
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SECTIONS {
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.flash2 (NOLOAD) : ALIGN(4) {
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*(.flash2 .flash2.*);
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. = ALIGN(4);
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} > FLASH2
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.itcm (NOLOAD) : ALIGN(8) {
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*(.itcm .itcm.*);
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. = ALIGN(8);
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} > ITCM
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.axisram (NOLOAD) : ALIGN(8) {
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*(.axisram .axisram.*);
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. = ALIGN(8);
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} > AXISRAM
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.sram1 (NOLOAD) : ALIGN(8) {
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*(.sram1 .sram1.*);
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. = ALIGN(4);
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} > SRAM1
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.sram2 (NOLOAD) : ALIGN(8) {
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*(.sram2 .sram2.*);
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. = ALIGN(4);
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} > SRAM2
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.sram3 (NOLOAD) : ALIGN(4) {
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*(.sram3 .sram3.*);
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. = ALIGN(4);
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} > SRAM3
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.sram4 (NOLOAD) : ALIGN(4) {
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*(.sram4 .sram4.*);
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. = ALIGN(4);
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} > SRAM4
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.bsram (NOLOAD) : ALIGN(4) {
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*(.bsram .bsram.*);
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. = ALIGN(4);
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} > BSRAM
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};
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