Robin Mueller
fe970ad881
Add satrs::fdir::FaultCounter, an FSFW-style error threshold counter: counts faults, decrements over time when faults stop, and reports when a threshold is exceeded. Two variants for now, mirroring the hk.rs helper pattern: - FaultCounterStd, backed by std::time::Instant - FaultCounterEmbassy, backed by embassy_time::Instant (embassy-time feature), with an optional defmt::Format impl gated on the defmt feature Add satrs::health::HealthTableMapSync::default() for easy construction of a shared, global health table. Wire both into the example app's MGM device handler as the first real FDIR use case: - the minisim MGM model gains SpiFaultMode (None/AllZeros/AllOnes) and a SetSpiFault request, so a stuck SPI bus can be injected for testing, independent of switch state - MgmHandlerLis3Mdl::poll_sensor checks the SPI transfer result: a comm timeout or an all-1s stuck-bus reply (the same pattern the sim already uses for "device off") counts as a fault. Above threshold, the component is marked Faulty in a HealthTableMapSync shared from main.rs. This logic lives in the device handler, not the SPI comm layer, since deciding what a failed transfer means for FDIR is a handler concern. - an all-0s reply is deliberately not treated as a fault, since it collides with a legitimate zero-field reading
sat-rs minisim
This crate contains a mini-simulator based on the open-source discrete-event simulation framework asynchronix.
Right now, this crate is primarily used together with the
satrs-example application
to simulate the devices connected to the example application.
You can simply run this application using
cargo run
or
cargo run -p satrs-minisim
in the workspace. The mini simulator uses the UDP port 7303 to exchange simulation requests and simulation replies with any other application.
The simulator was designed in a modular way to be scalable and adaptable to other communication schemes. This might allow it to serve a mini-simulator for other example applications which still have similar device handlers.
The following graph shows the high-level architecture of the mini-simulator.
