Update GPIO code
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a463332d58
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021efc5a5a
156
src/gpio.rs
156
src/gpio.rs
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@ -1,4 +1,5 @@
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use crate::pac::SYSCONFIG;
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use cortex_m::singleton;
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use core::convert::Infallible;
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use core::marker::PhantomData;
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use embedded_hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin, ToggleableOutputPin};
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@ -10,18 +11,30 @@ pub trait GpioExt {
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type Parts;
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/// Splits the GPIO block into independent pins and registers.
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fn split(&mut self, syscfg: &mut SYSCONFIG) -> Self::Parts;
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fn split(&mut self, syscfg: &mut SYSCONFIG) -> Option<Self::Parts>;
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}
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#[derive(Debug, PartialEq)]
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pub enum PinModeError {
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InputDisabledForOutput,
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IsMasked,
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}
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#[derive(Debug, PartialEq)]
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pub enum PinState {
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Low = 0,
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High = 1,
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}
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enum PortId {
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A,
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B
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}
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trait GpioRegExt {
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fn is_low(&self, pos: u8) -> bool;
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fn is_set_low(&self, pos: usize, port_id: char) -> Result<bool, PinModeError>;
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fn input_enabled_for_output(&self, pos: usize, port_id: char) -> bool;
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fn is_set_low(&self, pos: usize, port_id: &PortId) -> Result<bool, PinModeError>;
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fn input_enabled_for_output(&self, pos: usize, port_id: &PortId) -> bool;
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fn set_high(&self, pos: u8);
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fn set_low(&self, pos: u8);
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fn toggle(&self, pos: u8);
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@ -85,7 +98,7 @@ pub enum FilterClkSel {
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/// Fully erased pin
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pub struct Pin<MODE> {
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i: u8,
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port_id: char,
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port_id: PortId,
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port: *const dyn GpioRegExt,
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_mode: PhantomData<MODE>,
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}
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@ -98,7 +111,7 @@ impl<MODE> StatefulOutputPin for Pin<Output<MODE>> {
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}
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#[inline(always)]
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fn is_set_low(&self) -> Result<bool, Self::Error> {
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unsafe { (*self.port).is_set_low(self.i.into(), self.port_id) }
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unsafe { (*self.port).is_set_low(self.i.into(), &self.port_id) }
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}
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}
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impl<MODE> OutputPin for Pin<Output<MODE>> {
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@ -155,7 +168,7 @@ impl GpioRegExt for crate::pac::porta::RegisterBlock {
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self.datainraw().read().bits() & (1 << pos) == 0
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}
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#[inline(always)]
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fn is_set_low(&self, pos: usize, port_id: char) -> Result<bool, PinModeError> {
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fn is_set_low(&self, pos: usize, port_id: &PortId) -> Result<bool, PinModeError> {
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if self.input_enabled_for_output(pos, port_id) {
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Ok(self.datainraw().read().bits() & (1 << pos) == 0)
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} else {
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@ -175,20 +188,19 @@ impl GpioRegExt for crate::pac::porta::RegisterBlock {
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unsafe { self.togout().write(|w| w.bits(1 << pos)) }
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}
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#[inline(always)]
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fn input_enabled_for_output(&self, pos: usize, port_id: char) -> bool {
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fn input_enabled_for_output(&self, pos: usize, port_id: &PortId) -> bool {
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unsafe {
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let iocfg = &(*IOCONFIG::ptr());
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match port_id {
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'A' => iocfg.porta[pos].read().iewo().bit_is_set(),
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'B' => iocfg.portb[pos].read().iewo().bit_is_set(),
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_ => iocfg.porta[pos].read().iewo().bit_is_set(),
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PortId::A => iocfg.porta[pos].read().iewo().bit_is_set(),
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PortId::B => iocfg.portb[pos].read().iewo().bit_is_set(),
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}
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}
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}
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}
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macro_rules! gpio {
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($PORTX:ident, $portx:ident, $port_id:expr, [
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($PORTX:ident, $portx:ident, $port_id:path, [
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$($PXi:ident: ($pxi:ident, $i:expr),)+
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]) => {
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pub mod $portx {
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@ -197,7 +209,7 @@ macro_rules! gpio {
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use super::{
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FUNSEL1, FUNSEL2, FUNSEL3, Floating, Funsel, GpioExt, Input, OpenDrain,
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PullUp, Output, FilterType, FilterClkSel, Pin, GpioRegExt, PushPull,
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PinModeError
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PinModeError, PinState, PortId, singleton
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};
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use crate::{pac::$PORTX, pac::SYSCONFIG, pac::IOCONFIG};
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use embedded_hal::digital::v2::{
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@ -209,20 +221,28 @@ macro_rules! gpio {
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)+
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}
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pub fn get_perid(port: &$PORTX) -> u32 {
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port.perid.read().bits()
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}
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impl GpioExt for $PORTX {
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type Parts = Parts;
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fn split(&mut self, syscfg: &mut SYSCONFIG) -> Parts {
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/// This function splits the PORT into the individual pins
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/// Should only be called once and returns None on subsequent calls
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fn split(&mut self, syscfg: &mut SYSCONFIG) -> Option<Parts> {
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let _: &'static mut bool = singleton!(: bool = false)?;
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syscfg.peripheral_clk_enable.modify(|_, w| {
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w.$portx().set_bit();
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w.gpio().set_bit();
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w.ioconfig().set_bit();
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w
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});
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Parts {
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Some(Parts {
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$(
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$pxi: $PXi { _mode : PhantomData },
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)+
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}
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})
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}
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}
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@ -252,8 +272,34 @@ macro_rules! gpio {
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_set_alternate_mode(iocfg, $i, 3);
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$PXi { _mode: PhantomData }
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}
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// Get DATAMASK bit for this particular pin
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#[inline(always)]
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pub fn datamask(&self, port: &$PORTX) -> bool {
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(port.datamask().read().bits() >> $i) == 1
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}
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/// Set DATAMASK bit for this particular pin. 1 is the default
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/// state of the bit and allows access of the corresponding bit
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#[inline(always)]
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pub fn set_datamask(self, port: &mut $PORTX) -> Self {
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unsafe {
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port.datamask().modify(|r, w| w.bits(r.bits() | (1 << $i)))
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}
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self
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}
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/// Clear DATAMASK bit for this particular pin. This prevents access
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/// of the corresponding bit for output and input operations
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#[inline(always)]
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pub fn clear_datamask(self, port: &mut $PORTX) -> Self {
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unsafe {
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port.datamask().modify(|r, w| w.bits(r.bits() & !(1 << $i)))
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}
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self
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}
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pub fn into_floating_input(
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self, iocfg: &mut IOCONFIG
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self, iocfg: &mut IOCONFIG, port: &mut $PORTX
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) -> $PXi<Input<Floating>> {
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unsafe {
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iocfg.$portx[$i].modify(|_, w| {
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@ -261,8 +307,7 @@ macro_rules! gpio {
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w.pen().clear_bit();
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w.opendrn().clear_bit()
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});
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let port_reg = &(*$PORTX::ptr());
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port_reg.dir().modify(|r,w| w.bits(r.bits() & !(1 << $i)));
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port.dir().modify(|r,w| w.bits(r.bits() & !(1 << $i)));
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}
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$PXi { _mode: PhantomData }
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}
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@ -320,6 +365,7 @@ macro_rules! gpio {
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w.opendrn().clear_bit()
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});
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port_reg.dir().modify(|r,w| w.bits(r.bits() | (1 << $i)));
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port_reg.clrout().write(|w| w.bits(1 << $i))
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}
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$PXi { _mode: PhantomData }
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}
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@ -346,6 +392,22 @@ macro_rules! gpio {
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}
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self
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}
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/// This function takes account for the data mask register
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#[inline(always)]
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pub fn is_high_masked(&self, port: &$PORTX) -> Result<bool, PinModeError> {
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self.is_low_masked(port).map(|v| !v)
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}
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/// This function takes account for the data mask register
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#[inline(always)]
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pub fn is_low_masked(&self, port: &$PORTX) -> Result<bool, PinModeError> {
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if ((port.datamask().read().bits() >> $i) & 1) == 0 {
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Err(PinModeError::IsMasked)
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} else {
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Ok(port.datain().read().bits() & (1 << $i) == 0)
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}
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}
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}
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impl<MODE> $PXi<Output<MODE>> {
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@ -422,6 +484,58 @@ macro_rules! gpio {
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_mode: self._mode,
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}
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}
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/// This function takes account for the data mask register
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#[inline(always)]
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pub fn set_low_masked(&self, port: &$PORTX) -> Result<(), PinModeError> {
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if ((port.datamask().read().bits() >> $i) & 1) == 0 {
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Err(PinModeError::IsMasked)
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} else {
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Ok(unsafe { (*$PORTX::ptr()).set_low($i) })
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}
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}
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/// This function takes account for the data mask register
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#[inline(always)]
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pub fn set_high_masked(&self, port: &$PORTX) -> Result<(), PinModeError> {
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if ((port.datamask().read().bits() >> $i) & 1) == 0 {
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Err(PinModeError::IsMasked)
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} else {
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Ok(unsafe { (*$PORTX::ptr()).set_high($i) })
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}
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}
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pub fn pulse_mode(self, port: &mut $PORTX, enable: bool, default_state: PinState) -> Self {
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unsafe {
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if enable {
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port.pulse().modify(|r, w| w.bits(r.bits() | (1 << $i)));
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} else {
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port.pulse().modify(|r, w| w.bits(r.bits() & !(1 << $i)));
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}
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if default_state == PinState::Low {
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port.pulsebase().modify(|r,w| w.bits(r.bits() & !(1 << $i)));
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}
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else {
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port.pulsebase().modify(|r,w| w.bits(r.bits() | (1 << $i)));
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}
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}
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self
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}
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pub fn delay(self, port: &mut $PORTX, delay_1: bool, delay_2: bool) -> Self {
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unsafe {
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if delay_1 {
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port.delay1().modify(|r, w| w.bits(r.bits() | (1 << $i)));
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} else {
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port.delay1().modify(|r, w| w.bits(r.bits() & !(1 << $i)));
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}
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if delay_2 {
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port.delay2().modify(|r, w| w.bits(r.bits() | (1 << $i)));
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} else {
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port.delay2().modify(|r, w| w.bits(r.bits() & !(1 << $i)));
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}
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}
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self
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}
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}
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impl<MODE> StatefulOutputPin for $PXi<Output<MODE>> {
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@ -432,7 +546,7 @@ macro_rules! gpio {
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#[inline(always)]
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fn is_set_low(&self) -> Result<bool, Self::Error> {
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unsafe {
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(*$PORTX::ptr()).is_set_low($i, $port_id)
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(*$PORTX::ptr()).is_set_low($i, &$port_id)
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}
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}
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}
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@ -484,7 +598,7 @@ macro_rules! gpio {
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}
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}
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gpio!(PORTA, porta, 'A', [
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gpio!(PORTA, porta, PortId::A, [
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PA0: (pa0, 0),
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PA1: (pa1, 1),
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PA2: (pa2, 2),
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@ -519,7 +633,7 @@ gpio!(PORTA, porta, 'A', [
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PA31: (pa31, 31),
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]);
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gpio!(PORTB, portb, 'B', [
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gpio!(PORTB, portb, PortId::B, [
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PB0: (pb0, 0),
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PB1: (pb1, 1),
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PB2: (pb2, 2),
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