add Eq auto-derives

src/clock.rs

@@ -11,7 +11,7 @@ static SYS_CLOCK: Mutex<OnceCell<Hertz>> = Mutex::new(OnceCell::new());
 
 pub type PeripheralClocks = PeripheralSelect;
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum FilterClkSel {
     SysClk = 0,
     Clk1 = 1,

src/gpio/dynpins.rs

@@ -143,7 +143,7 @@ pub const DYN_ALT_FUNC_3: DynPinMode = DynPinMode::Alternate(DynAlternate::Funse
 //==================================================================================================
 
 /// Value-level `enum` for pin groups
-#[derive(PartialEq, Clone, Copy)]
+#[derive(PartialEq, Eq, Clone, Copy)]
 pub enum DynGroup {
     A,
     B,

src/gpio/pins.rs

@@ -106,27 +106,27 @@ use paste::paste;
 //  Errors and Definitions
 //==================================================================================================
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum InterruptEdge {
     HighToLow,
     LowToHigh,
     BothEdges,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum InterruptLevel {
     Low = 0,
     High = 1,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum PinState {
     Low = 0,
     High = 1,
 }
 
 /// GPIO error type
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum PinError {
     /// The pin did not have the correct ID or mode for the requested operation.
     /// [`DynPin`](crate::gpio::DynPin)s are not tracked and verified at compile-time, so run-time
@@ -182,7 +182,7 @@ pub struct Input<C: InputConfig> {
 
 impl<C: InputConfig> Sealed for Input<C> {}
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum FilterType {
     SystemClock = 0,
     DirectInputWithSynchronization = 1,

src/i2c.rs

@@ -18,13 +18,13 @@ pub use embedded_hal::blocking::i2c::{SevenBitAddress, TenBitAddress};
 // Defintions
 //==================================================================================================
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum FifoEmptyMode {
     Stall = 0,
     EndTransaction = 1,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum Error {
     InvalidTimingParams,
     ArbitrationLost,
@@ -46,19 +46,19 @@ enum I2cCmd {
     Cancel = 0b100,
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum I2cSpeed {
     Regular100khz = 0,
     Fast400khz = 1,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum I2cDirection {
     Send = 0,
     Read = 1,
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum I2cAddress {
     Regular(u8),
     TenBit(u16),

src/spi.rs

@@ -25,7 +25,7 @@ use embedded_hal::{
 // Defintions
 //==================================================================================================
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum HwChipSelectId {
     Id0 = 0,
     Id1 = 1,
@@ -38,7 +38,7 @@ pub enum HwChipSelectId {
     Invalid = 0xff,
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum WordSize {
     OneBit = 0x00,
     FourBits = 0x03,

src/time.rs

@@ -6,7 +6,7 @@
 //! allowing it to be converted into frequencies.
 
 /// Bits per second
-#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
 pub struct Bps(pub u32);
 
 /// Hertz
@@ -25,7 +25,7 @@ pub struct Bps(pub u32);
 ///
 /// let freq = 60.hz();
 /// ```
-#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
 pub struct Hertz(pub u32);
 
 /// Kilohertz
@@ -47,7 +47,7 @@ pub struct Hertz(pub u32);
 ///
 /// let freq = 100.khz();
 /// ```
-#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
 pub struct KiloHertz(pub u32);
 
 /// Megahertz
@@ -68,14 +68,14 @@ pub struct KiloHertz(pub u32);
 ///
 /// let freq = 8.mhz();
 /// ```
-#[derive(Clone, Copy, PartialEq, PartialOrd, Debug)]
+#[derive(Clone, Copy, PartialEq, Eq, PartialOrd, Debug)]
 pub struct MegaHertz(pub u32);
 
 /// Time unit
-#[derive(PartialEq, PartialOrd, Clone, Copy)]
+#[derive(PartialEq, Eq, PartialOrd, Clone, Copy)]
 pub struct MilliSeconds(pub u32);
 
-#[derive(PartialEq, PartialOrd, Clone, Copy)]
+#[derive(PartialEq, Eq, PartialOrd, Clone, Copy)]
 pub struct MicroSeconds(pub u32);
 
 /// Extension trait that adds convenience methods to the `u32` type

src/timer.rs

@@ -45,7 +45,7 @@ pub enum Event {
     TimeOut,
 }
 
-#[derive(Default, Debug, PartialEq, Copy, Clone)]
+#[derive(Default, Debug, PartialEq, Eq, Copy, Clone)]
 pub struct CascadeCtrl {
     /// Enable Cascade 0 signal active as a requirement for counting
     pub enb_start_src_csd0: bool,
@@ -74,7 +74,7 @@ pub struct CascadeCtrl {
     pub trg_csd2: bool,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum CascadeSel {
     Csd0 = 0,
     Csd1 = 1,
@@ -82,7 +82,7 @@ pub enum CascadeSel {
 }
 
 /// The numbers are the base numbers for bundles like PORTA, PORTB or TIM
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum CascadeSource {
     PortABase = 0,
     PortBBase = 32,
@@ -95,7 +95,7 @@ pub enum CascadeSource {
     ClockDividerBase = 120,
 }
 
-#[derive(Debug, PartialEq)]
+#[derive(Debug, PartialEq, Eq)]
 pub enum TimerErrors {
     Canceled,
     /// Invalid input for Cascade source

src/uart.rs

@@ -60,7 +60,7 @@ pub enum Error {
     IrqError,
 }
 
-#[derive(Debug, PartialEq, Copy, Clone)]
+#[derive(Debug, PartialEq, Eq, Copy, Clone)]
 pub enum Event {
     // Receiver FIFO interrupt enable. Generates interrupt
     // when FIFO is at least half full. Half full is defined as FIFO
@@ -84,20 +84,20 @@ pub enum Event {
     TxCts,
 }
 
-#[derive(Copy, Clone, PartialEq)]
+#[derive(Copy, Clone, PartialEq, Eq)]
 pub enum Parity {
     None,
     Odd,
     Even,
 }
 
-#[derive(Copy, Clone, PartialEq)]
+#[derive(Copy, Clone, PartialEq, Eq)]
 pub enum StopBits {
     One = 0,
     Two = 1,
 }
 
-#[derive(Copy, Clone, PartialEq)]
+#[derive(Copy, Clone, PartialEq, Eq)]
 pub enum WordSize {
     Five = 0,
     Six = 1,

src/utility.rs

@@ -6,7 +6,7 @@
 use crate::pac;
 use va108xx::{IOCONFIG, SYSCONFIG};
 
-#[derive(PartialEq, Debug)]
+#[derive(PartialEq, Eq, Debug)]
 pub enum UtilityError {
     InvalidCounterResetVal,
     InvalidPin,
@@ -19,13 +19,13 @@ pub enum Funsel {
     Funsel3 = 0b11,
 }
 
-#[derive(Debug, Copy, Clone, PartialEq)]
+#[derive(Debug, Copy, Clone, PartialEq, Eq)]
 pub enum PortSel {
     PortA,
     PortB,
 }
 
-#[derive(Copy, Clone, PartialEq)]
+#[derive(Copy, Clone, PartialEq, Eq)]
 pub enum PeripheralSelect {
     PortA = 0,
     PortB = 1,
@@ -46,7 +46,7 @@ pub enum PeripheralSelect {
 /// use the IRQSEL register to route an interrupt, and whether the IRQ will be unmasked in the
 /// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might perform
 /// this steps themselves
-#[derive(Debug, PartialEq, Clone, Copy)]
+#[derive(Debug, PartialEq, Eq, Clone, Copy)]
 pub struct IrqCfg {
     /// Interrupt target vector. Should always be set, might be required for disabling IRQs
     pub irq: pac::Interrupt,