SPI improvements / Clock passing update
1. Using `impl Into<Hertz>` instead of Hertz now to increase usability for users 2. Update for SPI API to increase usability
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@ -13,6 +13,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- DelayUs and DelayMs trait implementations for timer
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- SPI implementation for blocking API, supports blockmode as well
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### Changed
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- API which expects values in Hertz now uses `impl Into<Hertz>` as input parameter
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## [0.2.1]
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### Added
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@ -62,10 +62,10 @@ fn main() -> ! {
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pinsa.pa29.into_funsel_1(),
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);
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spia_ref.borrow_mut().replace(
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Spi::spia::<NoneT>(
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Spi::spia(
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dp.SPIA,
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(sck, miso, mosi),
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50.mhz().into(),
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50.mhz(),
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spi_cfg,
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Some(&mut dp.SYSCONFIG),
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None,
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@ -80,10 +80,10 @@ fn main() -> ! {
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pinsb.pb7.into_funsel_2(),
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);
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spia_ref.borrow_mut().replace(
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Spi::spia::<NoneT>(
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Spi::spia(
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dp.SPIA,
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(sck, miso, mosi),
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50.mhz().into(),
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50.mhz(),
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spi_cfg,
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Some(&mut dp.SYSCONFIG),
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None,
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@ -98,10 +98,10 @@ fn main() -> ! {
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pinsb.pb3.into_funsel_1(),
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);
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spib_ref.borrow_mut().replace(
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Spi::spib::<NoneT>(
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Spi::spib(
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dp.SPIB,
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(sck, miso, mosi),
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50.mhz().into(),
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50.mhz(),
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spi_cfg,
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Some(&mut dp.SYSCONFIG),
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None,
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@ -114,10 +114,9 @@ fn main() -> ! {
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match SPI_BUS_SEL {
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SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
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if let Some(ref mut spi) = *spia_ref.borrow_mut() {
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let transfer_cfg = TransferConfig::<NoneT>::new(
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let transfer_cfg = TransferConfig::new_no_hw_cs(
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SPI_SPEED_KHZ.khz().into(),
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SPI_MODE,
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None,
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BLOCKMODE,
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false,
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);
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@ -40,9 +40,9 @@ pub enum FilterClkSel {
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/// The Vorago in powered by an external clock which might have different frequencies.
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/// The clock can be set here so it can be used by other software components as well.
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/// The clock can be set exactly once
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pub fn set_sys_clock(freq: Hertz) {
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pub fn set_sys_clock(freq: impl Into<Hertz>) {
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interrupt::free(|cs| {
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SYS_CLOCK.borrow(cs).set(freq).ok();
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SYS_CLOCK.borrow(cs).set(freq.into()).ok();
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})
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}
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72
src/spi.rs
72
src/spi.rs
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@ -54,26 +54,28 @@ pub trait PinSck<SPI>: Sealed {}
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pub trait PinMosi<SPI>: Sealed {}
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pub trait PinMiso<SPI>: Sealed {}
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pub trait OptionalHwCs<SPI>: Sealed {
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pub trait HwCs: Sealed {
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const CS_ID: HwChipSelectId;
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}
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pub trait OptionalHwCs<SPI>: HwCs + Sealed {}
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macro_rules! hw_cs_pin {
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($SPIx:ident, $PXx:ident, $AFx:ident, $HwCsIdent:path, $typedef:ident) => {
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impl OptionalHwCs<$SPIx> for Pin<$PXx, $AFx> {
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impl HwCs for Pin<$PXx, $AFx> {
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const CS_ID: HwChipSelectId = $HwCsIdent;
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}
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impl OptionalHwCs<$SPIx> for Pin<$PXx, $AFx> {}
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pub type $typedef = Pin<$PXx, $AFx>;
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};
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}
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impl OptionalHwCs<SPIA> for NoneT {
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const CS_ID: HwChipSelectId = HwChipSelectId::Invalid;
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}
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impl OptionalHwCs<SPIB> for NoneT {
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impl HwCs for NoneT {
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const CS_ID: HwChipSelectId = HwChipSelectId::Invalid;
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}
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impl OptionalHwCs<SPIA> for NoneT {}
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impl OptionalHwCs<SPIB> for NoneT {}
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// SPIA
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impl PinSck<SPIA> for Pin<PA31, AltFunc1> {}
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@ -183,6 +185,7 @@ pub trait GenericTransferConfig {
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fn blockmode(&mut self, blockmode: bool);
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fn mode(&mut self, mode: Mode);
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fn frequency(&mut self, spi_clk: Hertz);
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fn hw_cs_id(&self) -> u8;
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}
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/// This struct contains all configuration parameter which are transfer specific
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@ -201,7 +204,32 @@ pub struct TransferConfig<HWCS> {
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pub blockmode: bool,
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}
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impl<HWCS> TransferConfig<HWCS> {
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/// Type erased variant of the transfer configuration. This is required to avoid generics in
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/// the SPI constructor.
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pub struct ReducedTransferConfig {
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pub spi_clk: Hertz,
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pub mode: Mode,
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pub sod: bool,
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/// If this is enabled, all data in the FIFO is transmitted in a single frame unless
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/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
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/// duration of multiple data words
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pub blockmode: bool,
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pub hw_cs: HwChipSelectId,
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}
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impl TransferConfig<NoneT> {
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pub fn new_no_hw_cs(spi_clk: Hertz, mode: Mode, blockmode: bool, sod: bool) -> Self {
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TransferConfig {
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spi_clk,
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mode,
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hw_cs: None,
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sod,
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blockmode,
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}
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}
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}
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impl<HWCS: HwCs> TransferConfig<HWCS> {
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pub fn new(
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spi_clk: Hertz,
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mode: Mode,
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@ -217,9 +245,19 @@ impl<HWCS> TransferConfig<HWCS> {
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blockmode,
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}
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}
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pub fn downgrade(self) -> ReducedTransferConfig {
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ReducedTransferConfig {
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spi_clk: self.spi_clk,
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mode: self.mode,
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sod: self.sod,
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blockmode: self.blockmode,
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hw_cs: HWCS::CS_ID,
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}
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}
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}
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impl<HWCS> GenericTransferConfig for TransferConfig<HWCS> {
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impl<HWCS: HwCs> GenericTransferConfig for TransferConfig<HWCS> {
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/// Slave Output Disable
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fn sod(&mut self, sod: bool) {
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self.sod = sod;
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@ -236,6 +274,10 @@ impl<HWCS> GenericTransferConfig for TransferConfig<HWCS> {
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fn frequency(&mut self, spi_clk: Hertz) {
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self.spi_clk = spi_clk;
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}
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fn hw_cs_id(&self) -> u8 {
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HWCS::CS_ID as u8
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}
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}
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#[derive(Default)]
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@ -341,13 +383,13 @@ macro_rules! spi {
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/// If only one device is connected, this configuration only needs to be done
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/// once.
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/// * `syscfg` - Can be passed optionally to enable the peripheral clock
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pub fn $spix<HwCs: OptionalHwCs<$SPIX>>(
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pub fn $spix(
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spi: $SPIX,
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pins: (Sck, Miso, Mosi),
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sys_clk: Hertz,
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sys_clk: impl Into<Hertz> + Copy,
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spi_cfg: SpiConfig,
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syscfg: Option<&mut SYSCONFIG>,
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transfer_cfg: Option<&TransferConfig<HwCs>>,
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transfer_cfg: Option<&ReducedTransferConfig>,
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) -> Self {
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if let Some(syscfg) = syscfg {
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enable_peripheral_clock(syscfg, $clk_enb);
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@ -365,9 +407,9 @@ macro_rules! spi {
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let mut init_blockmode = false;
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if let Some(transfer_cfg) = transfer_cfg {
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mode = transfer_cfg.mode;
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clk_prescale = sys_clk.0 / (transfer_cfg.spi_clk.0 * (scrdv as u32 + 1));
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if transfer_cfg.hw_cs.is_some() {
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ss = HwCs::CS_ID as u8;
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clk_prescale = sys_clk.into().0 / (transfer_cfg.spi_clk.0 * (scrdv as u32 + 1));
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if transfer_cfg.hw_cs != HwChipSelectId::Invalid {
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ss = transfer_cfg.hw_cs as u8;
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}
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init_blockmode = transfer_cfg.blockmode;
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}
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@ -408,7 +450,7 @@ macro_rules! spi {
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spi_base: SpiBase {
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spi,
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cfg: spi_cfg,
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sys_clk,
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sys_clk: sys_clk.into(),
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blockmode: init_blockmode,
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_word: PhantomData,
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},
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@ -46,7 +46,7 @@ pub enum Error {
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BreakCondition,
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}
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#[derive(Copy, Clone, PartialEq)]
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#[derive(Debug, PartialEq, Copy, Clone)]
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pub enum Event {
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// Receiver FIFO interrupt enable. Generates interrupt
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// when FIFO is at least half full. Half full is defined as FIFO
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