Replaced Hertz by impl Into<Hertz> completely
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This commit is contained in:
2021-12-09 23:19:21 +01:00
parent 5f6914a93a
commit 659b7e8f27
7 changed files with 27 additions and 22 deletions

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@ -218,9 +218,9 @@ pub struct ReducedTransferConfig {
}
impl TransferConfig<NoneT> {
pub fn new_no_hw_cs(spi_clk: Hertz, mode: Mode, blockmode: bool, sod: bool) -> Self {
pub fn new_no_hw_cs(spi_clk: impl Into<Hertz>, mode: Mode, blockmode: bool, sod: bool) -> Self {
TransferConfig {
spi_clk,
spi_clk: spi_clk.into(),
mode,
hw_cs: None,
sod,
@ -231,14 +231,14 @@ impl TransferConfig<NoneT> {
impl<HWCS: HwCs> TransferConfig<HWCS> {
pub fn new(
spi_clk: Hertz,
spi_clk: impl Into<Hertz>,
mode: Mode,
hw_cs: Option<HWCS>,
blockmode: bool,
sod: bool,
) -> Self {
TransferConfig {
spi_clk,
spi_clk: spi_clk.into(),
mode,
hw_cs,
sod,
@ -452,7 +452,7 @@ macro_rules! spi {
}
#[inline]
pub fn cfg_clock(&mut self, spi_clk: Hertz) {
pub fn cfg_clock(&mut self, spi_clk: impl Into<Hertz>) {
self.spi_base.cfg_clock(spi_clk);
}
@ -482,8 +482,8 @@ macro_rules! spi {
impl<WORD: Word> SpiBase<$SPIX, WORD> {
#[inline]
pub fn cfg_clock(&mut self, spi_clk: Hertz) {
let clk_prescale = self.sys_clk.0 / (spi_clk.0 * (self.cfg.scrdv as u32 + 1));
pub fn cfg_clock(&mut self, spi_clk: impl Into<Hertz>) {
let clk_prescale = self.sys_clk.0 / (spi_clk.into().0 * (self.cfg.scrdv as u32 + 1));
self.spi
.clkprescale
.write(|w| unsafe { w.bits(clk_prescale) });