Merge remote-tracking branch 'origin/main' into develop
This commit is contained in:
commit
7dae33e7ca
|
|
@ -8,6 +8,15 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
|
|||
|
||||
## [unreleased]
|
||||
|
||||
### Added
|
||||
|
||||
- DelayUs and DelayMs trait implementations for timer
|
||||
- SPI implementation for blocking API, supports blockmode as well
|
||||
|
||||
### Changed
|
||||
|
||||
- API which expects values in Hertz now uses `impl Into<Hertz>` as input parameter
|
||||
|
||||
## [0.2.1]
|
||||
|
||||
### Added
|
||||
|
|
|
|||
|
|
@ -43,3 +43,7 @@ opt-level = "s"
|
|||
[[example]]
|
||||
name = "timer-ticks"
|
||||
required-features = ["rt"]
|
||||
|
||||
[[example]]
|
||||
name = "tests"
|
||||
required-features = ["rt"]
|
||||
|
|
|
|||
|
|
@ -0,0 +1,189 @@
|
|||
//! SPI example application
|
||||
#![no_main]
|
||||
#![no_std]
|
||||
|
||||
use core::cell::RefCell;
|
||||
|
||||
use cortex_m_rt::entry;
|
||||
use embedded_hal::spi::{Mode, MODE_0};
|
||||
use panic_rtt_target as _;
|
||||
use rtt_target::{rprintln, rtt_init_print};
|
||||
use va108xx_hal::{
|
||||
gpio::{PinsA, PinsB},
|
||||
pac::{self, SPIA, SPIB},
|
||||
prelude::*,
|
||||
spi::{self, NoneT, Spi, SpiBase, TransferConfig},
|
||||
timer::CountDownTimer,
|
||||
};
|
||||
|
||||
#[derive(PartialEq, Debug)]
|
||||
pub enum ExampleSelect {
|
||||
// Enter loopback mode. It is not necessary to tie MOSI/MISO together for this
|
||||
Loopback,
|
||||
// Send a test buffer and print everything received
|
||||
TestBuffer,
|
||||
}
|
||||
|
||||
#[derive(PartialEq, Debug)]
|
||||
pub enum SpiBusSelect {
|
||||
SpiAPortA,
|
||||
SpiAPortB,
|
||||
SpiBPortB,
|
||||
}
|
||||
|
||||
const EXAMPLE_SEL: ExampleSelect = ExampleSelect::TestBuffer;
|
||||
const SPI_BUS_SEL: SpiBusSelect = SpiBusSelect::SpiBPortB;
|
||||
const SPI_SPEED_KHZ: u32 = 1000;
|
||||
const SPI_MODE: Mode = MODE_0;
|
||||
const BLOCKMODE: bool = true;
|
||||
|
||||
#[entry]
|
||||
fn main() -> ! {
|
||||
rtt_init_print!();
|
||||
rprintln!("-- VA108xx SPI example application--");
|
||||
let mut dp = pac::Peripherals::take().unwrap();
|
||||
|
||||
let spia_ref: RefCell<Option<SpiBase<SPIA, u8>>> = RefCell::new(None);
|
||||
let spib_ref: RefCell<Option<SpiBase<SPIB, u8>>> = RefCell::new(None);
|
||||
let pinsa = PinsA::new(&mut dp.SYSCONFIG, None, dp.PORTA);
|
||||
let pinsb = PinsB::new(&mut dp.SYSCONFIG, Some(dp.IOCONFIG), dp.PORTB);
|
||||
|
||||
let mut spi_cfg = spi::SpiConfig::default();
|
||||
if EXAMPLE_SEL == ExampleSelect::Loopback {
|
||||
spi_cfg = spi_cfg.loopback(true)
|
||||
}
|
||||
|
||||
// Set up the SPI peripheral
|
||||
match SPI_BUS_SEL {
|
||||
SpiBusSelect::SpiAPortA => {
|
||||
let (sck, mosi, miso) = (
|
||||
pinsa.pa31.into_funsel_1(),
|
||||
pinsa.pa30.into_funsel_1(),
|
||||
pinsa.pa29.into_funsel_1(),
|
||||
);
|
||||
spia_ref.borrow_mut().replace(
|
||||
Spi::spia(
|
||||
dp.SPIA,
|
||||
(sck, miso, mosi),
|
||||
50.mhz(),
|
||||
spi_cfg,
|
||||
Some(&mut dp.SYSCONFIG),
|
||||
None,
|
||||
)
|
||||
.downgrade(),
|
||||
);
|
||||
}
|
||||
SpiBusSelect::SpiAPortB => {
|
||||
let (sck, mosi, miso) = (
|
||||
pinsb.pb9.into_funsel_2(),
|
||||
pinsb.pb8.into_funsel_2(),
|
||||
pinsb.pb7.into_funsel_2(),
|
||||
);
|
||||
spia_ref.borrow_mut().replace(
|
||||
Spi::spia(
|
||||
dp.SPIA,
|
||||
(sck, miso, mosi),
|
||||
50.mhz(),
|
||||
spi_cfg,
|
||||
Some(&mut dp.SYSCONFIG),
|
||||
None,
|
||||
)
|
||||
.downgrade(),
|
||||
);
|
||||
}
|
||||
SpiBusSelect::SpiBPortB => {
|
||||
let (sck, mosi, miso) = (
|
||||
pinsb.pb5.into_funsel_1(),
|
||||
pinsb.pb4.into_funsel_1(),
|
||||
pinsb.pb3.into_funsel_1(),
|
||||
);
|
||||
spib_ref.borrow_mut().replace(
|
||||
Spi::spib(
|
||||
dp.SPIB,
|
||||
(sck, miso, mosi),
|
||||
50.mhz(),
|
||||
spi_cfg,
|
||||
Some(&mut dp.SYSCONFIG),
|
||||
None,
|
||||
)
|
||||
.downgrade(),
|
||||
);
|
||||
}
|
||||
}
|
||||
// Configure transfer specific properties here
|
||||
match SPI_BUS_SEL {
|
||||
SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
|
||||
if let Some(ref mut spi) = *spia_ref.borrow_mut() {
|
||||
let transfer_cfg = TransferConfig::new_no_hw_cs(
|
||||
SPI_SPEED_KHZ.khz().into(),
|
||||
SPI_MODE,
|
||||
BLOCKMODE,
|
||||
false,
|
||||
);
|
||||
spi.cfg_transfer(&transfer_cfg);
|
||||
}
|
||||
}
|
||||
SpiBusSelect::SpiBPortB => {
|
||||
if let Some(ref mut spi) = *spib_ref.borrow_mut() {
|
||||
let hw_cs_pin = pinsb.pb2.into_funsel_1();
|
||||
let transfer_cfg = TransferConfig::new(
|
||||
SPI_SPEED_KHZ.khz().into(),
|
||||
SPI_MODE,
|
||||
Some(hw_cs_pin),
|
||||
BLOCKMODE,
|
||||
false,
|
||||
);
|
||||
spi.cfg_transfer(&transfer_cfg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// Application logic
|
||||
let mut delay_tim = CountDownTimer::tim1(&mut dp.SYSCONFIG, 50.mhz().into(), dp.TIM1);
|
||||
loop {
|
||||
match SPI_BUS_SEL {
|
||||
SpiBusSelect::SpiAPortA | SpiBusSelect::SpiAPortB => {
|
||||
if let Some(ref mut spi) = *spia_ref.borrow_mut() {
|
||||
if EXAMPLE_SEL == ExampleSelect::Loopback {
|
||||
nb::block!(spi.send(0x42_u8)).unwrap();
|
||||
let word = nb::block!(spi.read()).unwrap();
|
||||
assert_eq!(word, 0x42);
|
||||
delay_tim.delay_ms(500_u32);
|
||||
|
||||
let mut send_buf: [u8; 3] = [0x03, 0x02, 0x01];
|
||||
let reply = spi.transfer(&mut send_buf).unwrap();
|
||||
rprintln!("Received reply: {}, {}, {}", reply[0], reply[1], reply[2]);
|
||||
assert_eq!(reply, &[0x03, 0x02, 0x01]);
|
||||
delay_tim.delay_ms(500_u32);
|
||||
} else {
|
||||
let mut send_buf: [u8; 3] = [0x01, 0x02, 0x03];
|
||||
let reply = spi.transfer(&mut send_buf).unwrap();
|
||||
rprintln!("Received reply: {}, {}, {}", reply[0], reply[1], reply[2]);
|
||||
delay_tim.delay_ms(1000_u32);
|
||||
}
|
||||
}
|
||||
}
|
||||
SpiBusSelect::SpiBPortB => {
|
||||
if let Some(ref mut spi) = *spib_ref.borrow_mut() {
|
||||
if EXAMPLE_SEL == ExampleSelect::Loopback {
|
||||
nb::block!(spi.send(0x42_u8)).unwrap();
|
||||
let word = nb::block!(spi.read()).unwrap();
|
||||
assert_eq!(word, 0x42);
|
||||
delay_tim.delay_ms(500_u32);
|
||||
|
||||
let mut send_buf: [u8; 3] = [0x03, 0x02, 0x01];
|
||||
let reply = spi.transfer(&mut send_buf).unwrap();
|
||||
rprintln!("Received reply: {}, {}, {}", reply[0], reply[1], reply[2]);
|
||||
assert_eq!(reply, &[0x03, 0x02, 0x01]);
|
||||
delay_tim.delay_ms(500_u32);
|
||||
} else {
|
||||
let mut send_buf: [u8; 3] = [0x01, 0x02, 0x03];
|
||||
let reply = spi.transfer(&mut send_buf).unwrap();
|
||||
rprintln!("Received reply: {}, {}, {}", reply[0], reply[1], reply[2]);
|
||||
delay_tim.delay_ms(1000_u32);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -9,7 +9,13 @@ use cortex_m_rt::entry;
|
|||
use embedded_hal::digital::v2::{InputPin, OutputPin, ToggleableOutputPin};
|
||||
use panic_rtt_target as _;
|
||||
use rtt_target::{rprintln, rtt_init_print};
|
||||
use va108xx_hal::gpio::{PinState, PinsA, PinsB};
|
||||
use va108xx_hal::{
|
||||
gpio::{PinState, PinsA, PinsB},
|
||||
pac::{self, interrupt},
|
||||
prelude::*,
|
||||
time::Hertz,
|
||||
timer::{default_ms_irq_handler, set_up_ms_timer, CountDownTimer, Delay},
|
||||
};
|
||||
|
||||
#[allow(dead_code)]
|
||||
#[derive(Debug)]
|
||||
|
|
@ -25,7 +31,8 @@ enum TestCase {
|
|||
// Tie PA0 to an oscilloscope and configure pulse detection
|
||||
Pulse,
|
||||
// Tie PA0, PA1 and PA3 to an oscilloscope
|
||||
Delay,
|
||||
DelayGpio,
|
||||
DelayMs,
|
||||
}
|
||||
|
||||
#[entry]
|
||||
|
|
@ -33,10 +40,11 @@ fn main() -> ! {
|
|||
rtt_init_print!();
|
||||
rprintln!("-- VA108xx Test Application --");
|
||||
let mut dp = va108xx::Peripherals::take().unwrap();
|
||||
let cp = cortex_m::Peripherals::take().unwrap();
|
||||
let pinsa = PinsA::new(&mut dp.SYSCONFIG, None, dp.PORTA);
|
||||
let pinsb = PinsB::new(&mut dp.SYSCONFIG, Some(dp.IOCONFIG), dp.PORTB);
|
||||
let mut led1 = pinsa.pa10.into_push_pull_output();
|
||||
let test_case = TestCase::Delay;
|
||||
let test_case = TestCase::DelayGpio;
|
||||
|
||||
match test_case {
|
||||
TestCase::TestBasic
|
||||
|
|
@ -125,7 +133,7 @@ fn main() -> ! {
|
|||
cortex_m::asm::delay(25_000_000);
|
||||
}
|
||||
}
|
||||
TestCase::Delay => {
|
||||
TestCase::DelayGpio => {
|
||||
let mut out_0 = pinsa.pa0.into_push_pull_output().delay(true, false);
|
||||
let mut out_1 = pinsa.pa1.into_push_pull_output().delay(false, true);
|
||||
let mut out_2 = pinsa.pa3.into_push_pull_output().delay(true, true);
|
||||
|
|
@ -136,6 +144,47 @@ fn main() -> ! {
|
|||
cortex_m::asm::delay(25_000_000);
|
||||
}
|
||||
}
|
||||
TestCase::DelayMs => {
|
||||
let ms_timer = set_up_ms_timer(
|
||||
&mut dp.SYSCONFIG,
|
||||
&mut dp.IRQSEL,
|
||||
50.mhz().into(),
|
||||
dp.TIM0,
|
||||
pac::Interrupt::OC0,
|
||||
);
|
||||
unsafe {
|
||||
cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC0);
|
||||
}
|
||||
let mut delay = Delay::new(ms_timer);
|
||||
for _ in 0..5 {
|
||||
led1.toggle().ok();
|
||||
delay.delay_ms(500);
|
||||
led1.toggle().ok();
|
||||
delay.delay_ms(500);
|
||||
}
|
||||
|
||||
let mut delay_timer = CountDownTimer::tim1(&mut dp.SYSCONFIG, 50.mhz().into(), dp.TIM1);
|
||||
let mut pa0 = pinsa.pa0.into_push_pull_output();
|
||||
for _ in 0..5 {
|
||||
led1.toggle().ok();
|
||||
delay_timer.delay_ms(200_u32);
|
||||
led1.toggle().ok();
|
||||
delay_timer.delay_ms(200_u32);
|
||||
}
|
||||
let ahb_freq: Hertz = 50.mhz().into();
|
||||
let mut syst_delay = cortex_m::delay::Delay::new(cp.SYST, ahb_freq.0);
|
||||
// Test usecond delay using both TIM peripheral and SYST
|
||||
loop {
|
||||
pa0.toggle().ok();
|
||||
delay_timer.delay_us(50_u32);
|
||||
pa0.toggle().ok();
|
||||
delay_timer.delay_us(50_u32);
|
||||
pa0.toggle().ok();
|
||||
syst_delay.delay_us(50);
|
||||
pa0.toggle().ok();
|
||||
syst_delay.delay_us(50);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
rprintln!("Test success");
|
||||
|
|
@ -144,3 +193,8 @@ fn main() -> ! {
|
|||
cortex_m::asm::delay(25_000_000);
|
||||
}
|
||||
}
|
||||
|
||||
#[interrupt]
|
||||
fn OC0() {
|
||||
default_ms_irq_handler()
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ use va108xx_hal::{
|
|||
pac::{self, interrupt},
|
||||
prelude::*,
|
||||
time::Hertz,
|
||||
timer::{set_up_ms_timer, CountDownTimer, Event},
|
||||
timer::{default_ms_irq_handler, set_up_ms_timer, CountDownTimer, Event, MS_COUNTER},
|
||||
};
|
||||
|
||||
#[allow(dead_code)]
|
||||
|
|
@ -21,7 +21,6 @@ enum LibType {
|
|||
Hal,
|
||||
}
|
||||
|
||||
static MS_COUNTER: Mutex<Cell<u32>> = Mutex::new(Cell::new(0));
|
||||
static SEC_COUNTER: Mutex<Cell<u32>> = Mutex::new(Cell::new(0));
|
||||
|
||||
#[entry]
|
||||
|
|
@ -105,11 +104,7 @@ fn unmask_irqs() {
|
|||
|
||||
#[interrupt]
|
||||
fn OC0() {
|
||||
cortex_m::interrupt::free(|cs| {
|
||||
let mut ms = MS_COUNTER.borrow(cs).get();
|
||||
ms += 1;
|
||||
MS_COUNTER.borrow(cs).set(ms);
|
||||
});
|
||||
default_ms_irq_handler()
|
||||
}
|
||||
|
||||
#[interrupt]
|
||||
|
|
|
|||
|
|
@ -40,9 +40,9 @@ pub enum FilterClkSel {
|
|||
/// The Vorago in powered by an external clock which might have different frequencies.
|
||||
/// The clock can be set here so it can be used by other software components as well.
|
||||
/// The clock can be set exactly once
|
||||
pub fn set_sys_clock(freq: Hertz) {
|
||||
pub fn set_sys_clock(freq: impl Into<Hertz>) {
|
||||
interrupt::free(|cs| {
|
||||
SYS_CLOCK.borrow(cs).set(freq).ok();
|
||||
SYS_CLOCK.borrow(cs).set(freq.into()).ok();
|
||||
})
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -55,7 +55,7 @@
|
|||
//! `Error = core::convert::Infallible`, the value-level API can return a real
|
||||
//! error. If the [`DynPin`] is not in the correct [`DynPinMode`] for the
|
||||
//! operation, the trait functions will return
|
||||
//! [`InvalidPinType`](Error::InvalidPinType).
|
||||
//! [`InvalidPinType`](PinError::InvalidPinType).
|
||||
|
||||
use super::pins::{
|
||||
common_reg_if_functions, FilterType, InterruptEdge, InterruptLevel, Pin, PinError, PinId,
|
||||
|
|
|
|||
|
|
@ -3,8 +3,8 @@
|
|||
//! The implementation of this GPIO module is heavily based on the
|
||||
//! [ATSAMD HAL implementation](https://docs.rs/atsamd-hal/0.13.0/atsamd_hal/gpio/v2/index.html).
|
||||
//!
|
||||
//! This API provides two different submodules, [`pins`] and [`dynpins`],
|
||||
//! representing two different ways to handle GPIO pins. The default, [`pins`],
|
||||
//! This API provides two different submodules, [`mod@pins`] and [`dynpins`],
|
||||
//! representing two different ways to handle GPIO pins. The default, [`mod@pins`],
|
||||
//! is a type-level API that tracks the state of each pin at compile-time. The
|
||||
//! alternative, [`dynpins`] is a type-erased, value-level API that tracks the
|
||||
//! state of each pin at run-time.
|
||||
|
|
|
|||
|
|
@ -26,16 +26,17 @@
|
|||
//! }
|
||||
//! ```
|
||||
//!
|
||||
//! A `PinId` identifies a pin by it's group (A, B) and pin number. Each
|
||||
//! `PinId` instance is named according to its datasheet identifier, e.g.
|
||||
//! [`PA02`].
|
||||
//! A [`PinId`] identifies a pin by it's group (A, B) and pin number. Each
|
||||
//! [`PinId`] instance is named according to its datasheet identifier, e.g.
|
||||
//! PA02.
|
||||
//!
|
||||
//! A `PinMode` represents the various pin modes. The available `PinMode`
|
||||
//! variants are [`Input`], [`Output`] and [`Alternate`], each with its own corresponding
|
||||
//! configurations.
|
||||
//!
|
||||
//! It is not possible for users to create new instances of a [`Pin`]. Singleton
|
||||
//! instances of each pin are made available to users through the [`Pins`]
|
||||
//! instances of each pin are made available to users through the [`PinsA`] and
|
||||
//! [`PinsB`]
|
||||
//! struct.
|
||||
//!
|
||||
//! To create the [`PinsA`] or [`PinsB`] struct, users must supply the PAC
|
||||
|
|
@ -84,7 +85,8 @@
|
|||
//! This module also provides additional, type-level tools to work with GPIO
|
||||
//! pins.
|
||||
//!
|
||||
//! The [`AnyPin`] trait defines an [`AnyKind`] type class
|
||||
//! The [`AnyPin`] trait defines an
|
||||
//! [`AnyKind`](https://docs.rs/atsamd-hal/0.13.0/atsamd_hal/typelevel/index.html) type class
|
||||
//! for all `Pin` types.
|
||||
|
||||
use super::dynpins::{DynAlternate, DynGroup, DynInput, DynOutput, DynPinId, DynPinMode};
|
||||
|
|
@ -229,7 +231,8 @@ impl OutputConfig for ReadableOpenDrain {
|
|||
|
||||
/// Type-level variant of [`PinMode`] for output modes
|
||||
///
|
||||
/// Type `C` is one of two output configurations: [`PushPull`] or [`Readable`]
|
||||
/// Type `C` is one of four output configurations: [`PushPull`], [`OpenDrain`] or
|
||||
/// their respective readable versions
|
||||
pub struct Output<C: OutputConfig> {
|
||||
cfg: PhantomData<C>,
|
||||
}
|
||||
|
|
@ -543,7 +546,8 @@ pub type SpecificPin<P> = Pin<<P as AnyPin>::Id, <P as AnyPin>::Mode>;
|
|||
|
||||
/// Type class for [`Pin`] types
|
||||
///
|
||||
/// This trait uses the [`AnyKind`] trait pattern to create a [type class] for
|
||||
/// This trait uses the [`AnyKind`](https://docs.rs/atsamd-hal/0.13.0/atsamd_hal/typelevel/index.html)
|
||||
/// trait pattern to create a [type class] for
|
||||
/// [`Pin`] types. See the `AnyKind` documentation for more details on the
|
||||
/// pattern.
|
||||
pub trait AnyPin: Is<Type = SpecificPin<Self>> {
|
||||
|
|
|
|||
|
|
@ -1,17 +1,17 @@
|
|||
#![no_std]
|
||||
|
||||
pub use va108xx;
|
||||
pub use va108xx as pac;
|
||||
|
||||
pub mod clock;
|
||||
pub mod gpio;
|
||||
pub mod prelude;
|
||||
pub mod spi;
|
||||
pub mod time;
|
||||
pub mod timer;
|
||||
pub mod typelevel;
|
||||
pub mod uart;
|
||||
|
||||
pub use va108xx as pac;
|
||||
|
||||
mod private {
|
||||
/// Super trait used to mark traits with an exhaustive set of
|
||||
/// implementations
|
||||
|
|
|
|||
|
|
@ -0,0 +1,770 @@
|
|||
//! API for the SPI peripheral
|
||||
//!
|
||||
//! ## Examples
|
||||
//!
|
||||
//! - [Blocking SPI example](https://github.com/robamu-org/va108xx-hal-rs/blob/main/examples/spi.rs)
|
||||
use crate::Sealed;
|
||||
use crate::{
|
||||
clock::{enable_peripheral_clock, PeripheralClocks},
|
||||
gpio::pins::{
|
||||
AltFunc1, AltFunc2, AltFunc3, Pin, PA10, PA11, PA12, PA13, PA14, PA15, PA16, PA17, PA18,
|
||||
PA19, PA20, PA21, PA22, PA23, PA24, PA25, PA26, PA27, PA28, PA29, PA30, PA31, PB0, PB1,
|
||||
PB10, PB11, PB12, PB13, PB14, PB15, PB16, PB17, PB18, PB19, PB2, PB22, PB23, PB3, PB4, PB5,
|
||||
PB6, PB7, PB8, PB9,
|
||||
},
|
||||
pac::{SPIA, SPIB, SPIC, SYSCONFIG},
|
||||
time::Hertz,
|
||||
};
|
||||
use core::{convert::Infallible, fmt::Debug, marker::PhantomData};
|
||||
use embedded_hal::{
|
||||
blocking,
|
||||
spi::{FullDuplex, Mode, MODE_0, MODE_1, MODE_2, MODE_3},
|
||||
};
|
||||
|
||||
//==================================================================================================
|
||||
// Defintions
|
||||
//==================================================================================================
|
||||
|
||||
#[derive(Debug, PartialEq, Copy, Clone)]
|
||||
pub enum HwChipSelectId {
|
||||
Id0 = 0,
|
||||
Id1 = 1,
|
||||
Id2 = 2,
|
||||
Id3 = 3,
|
||||
Id4 = 4,
|
||||
Id5 = 5,
|
||||
Id6 = 6,
|
||||
Id7 = 7,
|
||||
Invalid = 0xff,
|
||||
}
|
||||
|
||||
#[derive(Debug, PartialEq, Copy, Clone)]
|
||||
pub enum WordSize {
|
||||
OneBit = 0x00,
|
||||
FourBits = 0x03,
|
||||
EightBits = 0x07,
|
||||
SixteenBits = 0x0f,
|
||||
}
|
||||
|
||||
//==================================================================================================
|
||||
// Pin type definitions
|
||||
//==================================================================================================
|
||||
|
||||
pub trait PinSck<SPI>: Sealed {}
|
||||
pub trait PinMosi<SPI>: Sealed {}
|
||||
pub trait PinMiso<SPI>: Sealed {}
|
||||
|
||||
pub trait HwCs: Sealed {
|
||||
const CS_ID: HwChipSelectId;
|
||||
}
|
||||
pub trait OptionalHwCs<SPI>: HwCs + Sealed {}
|
||||
|
||||
macro_rules! hw_cs_pin {
|
||||
($SPIx:ident, $PXx:ident, $AFx:ident, $HwCsIdent:path, $typedef:ident) => {
|
||||
impl HwCs for Pin<$PXx, $AFx> {
|
||||
const CS_ID: HwChipSelectId = $HwCsIdent;
|
||||
}
|
||||
impl OptionalHwCs<$SPIx> for Pin<$PXx, $AFx> {}
|
||||
pub type $typedef = Pin<$PXx, $AFx>;
|
||||
};
|
||||
}
|
||||
|
||||
impl HwCs for NoneT {
|
||||
const CS_ID: HwChipSelectId = HwChipSelectId::Invalid;
|
||||
}
|
||||
|
||||
impl OptionalHwCs<SPIA> for NoneT {}
|
||||
impl OptionalHwCs<SPIB> for NoneT {}
|
||||
|
||||
// SPIA
|
||||
|
||||
impl PinSck<SPIA> for Pin<PA31, AltFunc1> {}
|
||||
impl PinMosi<SPIA> for Pin<PA30, AltFunc1> {}
|
||||
impl PinMiso<SPIA> for Pin<PA29, AltFunc1> {}
|
||||
|
||||
pub type SpiAPortASck = Pin<PA31, AltFunc1>;
|
||||
pub type SpiAPortAMosi = Pin<PA30, AltFunc1>;
|
||||
pub type SpiAPortAMiso = Pin<PA29, AltFunc1>;
|
||||
|
||||
impl PinSck<SPIA> for Pin<PB9, AltFunc2> {}
|
||||
impl PinMosi<SPIA> for Pin<PB8, AltFunc2> {}
|
||||
impl PinMiso<SPIA> for Pin<PB7, AltFunc2> {}
|
||||
|
||||
pub type SpiAPortBSck = Pin<PB9, AltFunc2>;
|
||||
pub type SpiAPortBMosi = Pin<PB8, AltFunc2>;
|
||||
pub type SpiAPortBMiso = Pin<PB7, AltFunc2>;
|
||||
|
||||
hw_cs_pin!(SPIA, PA28, AltFunc1, HwChipSelectId::Id0, HwCs0SpiAPortA);
|
||||
hw_cs_pin!(SPIA, PA27, AltFunc1, HwChipSelectId::Id1, HwCs1SpiAPortA);
|
||||
hw_cs_pin!(SPIA, PA26, AltFunc1, HwChipSelectId::Id2, HwCs2SpiAPortA);
|
||||
hw_cs_pin!(SPIA, PA25, AltFunc1, HwChipSelectId::Id3, HwCs3SpiAPortA);
|
||||
hw_cs_pin!(SPIA, PA24, AltFunc1, HwChipSelectId::Id4, HwCs4SpiAPortA);
|
||||
hw_cs_pin!(SPIA, PA23, AltFunc1, HwChipSelectId::Id5, HwCs5SpiAPortA);
|
||||
hw_cs_pin!(SPIA, PA22, AltFunc1, HwChipSelectId::Id6, HwCs6SpiAPortA);
|
||||
hw_cs_pin!(SPIA, PA21, AltFunc1, HwChipSelectId::Id7, HwCs7SpiAPortA);
|
||||
|
||||
hw_cs_pin!(SPIA, PB6, AltFunc2, HwChipSelectId::Id0, HwCs0SpiAPortB);
|
||||
hw_cs_pin!(SPIA, PB5, AltFunc2, HwChipSelectId::Id6, HwCs6SpiAPortB);
|
||||
hw_cs_pin!(SPIA, PB4, AltFunc2, HwChipSelectId::Id5, HwCs5SpiAPortB);
|
||||
hw_cs_pin!(SPIA, PB3, AltFunc2, HwChipSelectId::Id4, HwCs4SpiAPortB);
|
||||
hw_cs_pin!(SPIA, PB2, AltFunc2, HwChipSelectId::Id3, HwCs3SpiAPortB);
|
||||
hw_cs_pin!(SPIA, PB1, AltFunc2, HwChipSelectId::Id2, HwCs2SpiAPortB);
|
||||
hw_cs_pin!(SPIA, PB0, AltFunc2, HwChipSelectId::Id1, HwCs1SpiAPortB);
|
||||
|
||||
// SPIB
|
||||
|
||||
impl PinSck<SPIB> for Pin<PA20, AltFunc2> {}
|
||||
impl PinMosi<SPIB> for Pin<PA19, AltFunc2> {}
|
||||
impl PinMiso<SPIB> for Pin<PA18, AltFunc2> {}
|
||||
|
||||
pub type SpiBPortASck = Pin<PA20, AltFunc2>;
|
||||
pub type SpiBPortAMosi = Pin<PA19, AltFunc2>;
|
||||
pub type SpiBPortAMiso = Pin<PA18, AltFunc2>;
|
||||
|
||||
impl PinSck<SPIB> for Pin<PB19, AltFunc1> {}
|
||||
impl PinMosi<SPIB> for Pin<PB18, AltFunc1> {}
|
||||
impl PinMiso<SPIB> for Pin<PB17, AltFunc1> {}
|
||||
|
||||
impl PinSck<SPIB> for Pin<PB5, AltFunc1> {}
|
||||
impl PinMosi<SPIB> for Pin<PB4, AltFunc1> {}
|
||||
impl PinMiso<SPIB> for Pin<PB3, AltFunc1> {}
|
||||
|
||||
hw_cs_pin!(SPIB, PB16, AltFunc1, HwChipSelectId::Id0, HwCs0SpiBPortB0);
|
||||
hw_cs_pin!(SPIB, PB15, AltFunc1, HwChipSelectId::Id1, HwCs1SpiBPortB0);
|
||||
hw_cs_pin!(SPIB, PB14, AltFunc1, HwChipSelectId::Id2, HwCs2SpiBPortB0);
|
||||
hw_cs_pin!(SPIB, PB13, AltFunc1, HwChipSelectId::Id3, HwCs3SpiBPortB);
|
||||
hw_cs_pin!(SPIB, PB12, AltFunc1, HwChipSelectId::Id4, HwCs4SpiBPortB);
|
||||
hw_cs_pin!(SPIB, PB11, AltFunc1, HwChipSelectId::Id5, HwCs5SpiBPortB);
|
||||
hw_cs_pin!(SPIB, PB10, AltFunc1, HwChipSelectId::Id6, HwCs6SpiBPortB);
|
||||
|
||||
hw_cs_pin!(SPIB, PB2, AltFunc1, HwChipSelectId::Id0, HwCs0SpiBPortB1);
|
||||
hw_cs_pin!(SPIB, PB1, AltFunc1, HwChipSelectId::Id1, HwCs1SpiBPortB1);
|
||||
hw_cs_pin!(SPIB, PB0, AltFunc1, HwChipSelectId::Id2, HwCs2SpiBPortB1);
|
||||
|
||||
hw_cs_pin!(SPIB, PB12, AltFunc2, HwChipSelectId::Id0, HwCs0SpiBPortB2);
|
||||
hw_cs_pin!(SPIB, PB11, AltFunc2, HwChipSelectId::Id1, HwCs1SpiBPortB2);
|
||||
hw_cs_pin!(SPIB, PB10, AltFunc2, HwChipSelectId::Id2, HwCs2SpiBPortB2);
|
||||
|
||||
hw_cs_pin!(SPIB, PA17, AltFunc2, HwChipSelectId::Id0, HwCs0SpiBPortA);
|
||||
hw_cs_pin!(SPIB, PA16, AltFunc2, HwChipSelectId::Id1, HwCs1SpiBPortA);
|
||||
hw_cs_pin!(SPIB, PA15, AltFunc2, HwChipSelectId::Id2, HwCs2SpiBPortA);
|
||||
hw_cs_pin!(SPIB, PA14, AltFunc2, HwChipSelectId::Id3, HwCs3SpiBPortA);
|
||||
hw_cs_pin!(SPIB, PA13, AltFunc2, HwChipSelectId::Id4, HwCs4SpiBPortA);
|
||||
hw_cs_pin!(SPIB, PA12, AltFunc2, HwChipSelectId::Id5, HwCs5SpiBPortA0);
|
||||
hw_cs_pin!(SPIB, PA11, AltFunc2, HwChipSelectId::Id6, HwCs6SpiBPortA0);
|
||||
hw_cs_pin!(SPIB, PA10, AltFunc2, HwChipSelectId::Id7, HwCs7SpiBPortA0);
|
||||
|
||||
hw_cs_pin!(SPIB, PA23, AltFunc2, HwChipSelectId::Id5, HwCs5SpiBPortA1);
|
||||
hw_cs_pin!(SPIB, PA22, AltFunc2, HwChipSelectId::Id6, HwCs6SpiBPortA1);
|
||||
hw_cs_pin!(SPIB, PA21, AltFunc2, HwChipSelectId::Id7, HwCs7SpiBPortA1);
|
||||
|
||||
// SPIC
|
||||
|
||||
hw_cs_pin!(SPIC, PB9, AltFunc3, HwChipSelectId::Id1, HwCs1SpiCPortB0);
|
||||
hw_cs_pin!(SPIC, PB8, AltFunc3, HwChipSelectId::Id2, HwCs2SpiCPortB0);
|
||||
hw_cs_pin!(SPIC, PB7, AltFunc3, HwChipSelectId::Id3, HwCs3SpiCPortB);
|
||||
|
||||
hw_cs_pin!(SPIC, PB22, AltFunc3, HwChipSelectId::Id1, HwCs1SpiCPortB1);
|
||||
hw_cs_pin!(SPIC, PB23, AltFunc3, HwChipSelectId::Id2, HwCs2SpiCPortB1);
|
||||
|
||||
hw_cs_pin!(SPIC, PA20, AltFunc1, HwChipSelectId::Id1, HwCs1SpiCPortA0);
|
||||
hw_cs_pin!(SPIC, PA19, AltFunc1, HwChipSelectId::Id2, HwCs2SpiCPortA0);
|
||||
hw_cs_pin!(SPIC, PB18, AltFunc1, HwChipSelectId::Id3, HwCs3SpiCPortA0);
|
||||
|
||||
hw_cs_pin!(SPIC, PA23, AltFunc3, HwChipSelectId::Id1, HwCs1SpiCPortA1);
|
||||
hw_cs_pin!(SPIC, PA22, AltFunc3, HwChipSelectId::Id2, HwCs2SpiCPortA1);
|
||||
hw_cs_pin!(SPIC, PA21, AltFunc3, HwChipSelectId::Id3, HwCs3SpiCPortA1);
|
||||
hw_cs_pin!(SPIC, PA20, AltFunc3, HwChipSelectId::Id4, HwCs4SpiCPortA);
|
||||
|
||||
//==================================================================================================
|
||||
// Config
|
||||
//==================================================================================================
|
||||
|
||||
pub trait GenericTransferConfig {
|
||||
fn sod(&mut self, sod: bool);
|
||||
fn blockmode(&mut self, blockmode: bool);
|
||||
fn mode(&mut self, mode: Mode);
|
||||
fn frequency(&mut self, spi_clk: Hertz);
|
||||
fn hw_cs_id(&self) -> u8;
|
||||
}
|
||||
|
||||
/// This struct contains all configuration parameter which are transfer specific
|
||||
/// and might change for transfers to different SPI slaves
|
||||
#[derive(Copy, Clone)]
|
||||
pub struct TransferConfig<HWCS> {
|
||||
pub spi_clk: Hertz,
|
||||
pub mode: Mode,
|
||||
/// This only works if the Slave Output Disable (SOD) bit of the [`SpiConfig`] is set to
|
||||
/// false
|
||||
pub hw_cs: Option<HWCS>,
|
||||
pub sod: bool,
|
||||
/// If this is enabled, all data in the FIFO is transmitted in a single frame unless
|
||||
/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
|
||||
/// duration of multiple data words
|
||||
pub blockmode: bool,
|
||||
}
|
||||
|
||||
/// Type erased variant of the transfer configuration. This is required to avoid generics in
|
||||
/// the SPI constructor.
|
||||
pub struct ReducedTransferConfig {
|
||||
pub spi_clk: Hertz,
|
||||
pub mode: Mode,
|
||||
pub sod: bool,
|
||||
/// If this is enabled, all data in the FIFO is transmitted in a single frame unless
|
||||
/// the BMSTOP bit is set on a dataword. A frame is defined as CSn being active for the
|
||||
/// duration of multiple data words
|
||||
pub blockmode: bool,
|
||||
pub hw_cs: HwChipSelectId,
|
||||
}
|
||||
|
||||
impl TransferConfig<NoneT> {
|
||||
pub fn new_no_hw_cs(spi_clk: Hertz, mode: Mode, blockmode: bool, sod: bool) -> Self {
|
||||
TransferConfig {
|
||||
spi_clk,
|
||||
mode,
|
||||
hw_cs: None,
|
||||
sod,
|
||||
blockmode,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<HWCS: HwCs> TransferConfig<HWCS> {
|
||||
pub fn new(
|
||||
spi_clk: Hertz,
|
||||
mode: Mode,
|
||||
hw_cs: Option<HWCS>,
|
||||
blockmode: bool,
|
||||
sod: bool,
|
||||
) -> Self {
|
||||
TransferConfig {
|
||||
spi_clk,
|
||||
mode,
|
||||
hw_cs,
|
||||
sod,
|
||||
blockmode,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn downgrade(self) -> ReducedTransferConfig {
|
||||
ReducedTransferConfig {
|
||||
spi_clk: self.spi_clk,
|
||||
mode: self.mode,
|
||||
sod: self.sod,
|
||||
blockmode: self.blockmode,
|
||||
hw_cs: HWCS::CS_ID,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<HWCS: HwCs> GenericTransferConfig for TransferConfig<HWCS> {
|
||||
/// Slave Output Disable
|
||||
fn sod(&mut self, sod: bool) {
|
||||
self.sod = sod;
|
||||
}
|
||||
|
||||
fn blockmode(&mut self, blockmode: bool) {
|
||||
self.blockmode = blockmode;
|
||||
}
|
||||
|
||||
fn mode(&mut self, mode: Mode) {
|
||||
self.mode = mode;
|
||||
}
|
||||
|
||||
fn frequency(&mut self, spi_clk: Hertz) {
|
||||
self.spi_clk = spi_clk;
|
||||
}
|
||||
|
||||
fn hw_cs_id(&self) -> u8 {
|
||||
HWCS::CS_ID as u8
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Default)]
|
||||
/// Configuration options for the whole SPI bus. See Programmer Guide p.92 for more details
|
||||
pub struct SpiConfig {
|
||||
/// Serial clock rate divider. Together with the CLKPRESCALE register, it determines
|
||||
/// the SPI clock rate in master mode. 0 by default. Specifying a higher value
|
||||
/// limits the maximum attainable SPI speed
|
||||
pub scrdv: u8,
|
||||
/// By default, configure SPI for master mode (ms == false)
|
||||
ms: bool,
|
||||
/// Slave output disable. Useful if separate GPIO pins or decoders are used for CS control
|
||||
sod: bool,
|
||||
/// Loopback mode. If you use this, don't connect MISO to MOSI, they will be tied internally
|
||||
lbm: bool,
|
||||
/// Enable Master Delayer Capture Mode. See Programmers Guide p.92 for more details
|
||||
pub mdlycap: bool,
|
||||
}
|
||||
|
||||
impl SpiConfig {
|
||||
pub fn loopback(mut self, enable: bool) -> Self {
|
||||
self.lbm = enable;
|
||||
self
|
||||
}
|
||||
|
||||
pub fn master_mode(mut self, master: bool) -> Self {
|
||||
self.ms = !master;
|
||||
self
|
||||
}
|
||||
|
||||
pub fn slave_output_disable(mut self, sod: bool) -> Self {
|
||||
self.sod = sod;
|
||||
self
|
||||
}
|
||||
}
|
||||
|
||||
//==================================================================================================
|
||||
// Word Size
|
||||
//==================================================================================================
|
||||
|
||||
/// Configuration trait for the Word Size
|
||||
/// used by the SPI peripheral
|
||||
pub trait Word {
|
||||
fn word_reg() -> u8;
|
||||
}
|
||||
|
||||
impl Word for u8 {
|
||||
fn word_reg() -> u8 {
|
||||
0x07
|
||||
}
|
||||
}
|
||||
|
||||
impl Word for u16 {
|
||||
fn word_reg() -> u8 {
|
||||
0x0f
|
||||
}
|
||||
}
|
||||
|
||||
//==================================================================================================
|
||||
// Spi
|
||||
//==================================================================================================
|
||||
|
||||
pub struct SpiBase<SPI, Word = u8> {
|
||||
spi: SPI,
|
||||
cfg: SpiConfig,
|
||||
sys_clk: Hertz,
|
||||
blockmode: bool,
|
||||
_word: PhantomData<Word>,
|
||||
}
|
||||
pub struct Spi<SPI, PINS, Word = u8> {
|
||||
spi_base: SpiBase<SPI, Word>,
|
||||
pins: PINS,
|
||||
}
|
||||
|
||||
// Re-export this so it can be used for the constructor
|
||||
pub use crate::typelevel::NoneT;
|
||||
|
||||
macro_rules! spi {
|
||||
($($SPIX:ident: ($spix:ident, $clk_enb:path) => ($($WORD:ident),+),)+) => {
|
||||
$(
|
||||
impl<Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>,
|
||||
WORD: Word> Spi<$SPIX, (Sck, Miso, Mosi), WORD>
|
||||
{
|
||||
/// Create a new SPI struct
|
||||
///
|
||||
/// You can delete the pin type information by calling the
|
||||
/// [`downgrade`](Self::downgrade) function
|
||||
///
|
||||
/// ## Arguments
|
||||
/// * `spi` - SPI bus to use
|
||||
/// * `pins` - Pins to be used for SPI transactions. These pins are consumed
|
||||
/// to ensure the pins can not be used for other purposes anymore
|
||||
/// * `spi_cfg` - Configuration specific to the SPI bus
|
||||
/// * `transfer_cfg` - Optional initial transfer configuration which includes
|
||||
/// configuration which can change across individual SPI transfers like SPI mode
|
||||
/// or SPI clock. If only one device is connected, this configuration only needs
|
||||
/// to be done once.
|
||||
/// * `syscfg` - Can be passed optionally to enable the peripheral clock
|
||||
pub fn $spix(
|
||||
spi: $SPIX,
|
||||
pins: (Sck, Miso, Mosi),
|
||||
sys_clk: impl Into<Hertz> + Copy,
|
||||
spi_cfg: SpiConfig,
|
||||
syscfg: Option<&mut SYSCONFIG>,
|
||||
transfer_cfg: Option<&ReducedTransferConfig>,
|
||||
) -> Self {
|
||||
if let Some(syscfg) = syscfg {
|
||||
enable_peripheral_clock(syscfg, $clk_enb);
|
||||
}
|
||||
let SpiConfig {
|
||||
scrdv,
|
||||
ms,
|
||||
sod,
|
||||
lbm,
|
||||
mdlycap,
|
||||
} = spi_cfg;
|
||||
let mut mode = MODE_0;
|
||||
let mut clk_prescale = 0x02;
|
||||
let mut ss = 0;
|
||||
let mut init_blockmode = false;
|
||||
if let Some(transfer_cfg) = transfer_cfg {
|
||||
mode = transfer_cfg.mode;
|
||||
clk_prescale = sys_clk.into().0 / (transfer_cfg.spi_clk.0 * (scrdv as u32 + 1));
|
||||
if transfer_cfg.hw_cs != HwChipSelectId::Invalid {
|
||||
ss = transfer_cfg.hw_cs as u8;
|
||||
}
|
||||
init_blockmode = transfer_cfg.blockmode;
|
||||
}
|
||||
|
||||
let (cpo_bit, cph_bit) = match mode {
|
||||
MODE_0 => (false, false),
|
||||
MODE_1 => (false, true),
|
||||
MODE_2 => (true, false),
|
||||
MODE_3 => (true, true),
|
||||
};
|
||||
spi.ctrl0.write(|w| {
|
||||
unsafe {
|
||||
w.size().bits(WORD::word_reg());
|
||||
w.scrdv().bits(scrdv);
|
||||
// Clear clock phase and polarity. Will be set to correct value for each
|
||||
// transfer
|
||||
w.spo().bit(cpo_bit);
|
||||
w.sph().bit(cph_bit)
|
||||
}
|
||||
});
|
||||
spi.ctrl1.write(|w| {
|
||||
w.lbm().bit(lbm);
|
||||
w.sod().bit(sod);
|
||||
w.ms().bit(ms);
|
||||
w.mdlycap().bit(mdlycap);
|
||||
unsafe { w.ss().bits(ss) }
|
||||
});
|
||||
|
||||
spi.fifo_clr.write(|w| {
|
||||
w.rxfifo().set_bit();
|
||||
w.txfifo().set_bit()
|
||||
});
|
||||
spi.clkprescale.write(|w| unsafe { w.bits(clk_prescale) });
|
||||
// Enable the peripheral as the last step as recommended in the
|
||||
// programmers guide
|
||||
spi.ctrl1.modify(|_, w| w.enable().set_bit());
|
||||
Spi {
|
||||
spi_base: SpiBase {
|
||||
spi,
|
||||
cfg: spi_cfg,
|
||||
sys_clk: sys_clk.into(),
|
||||
blockmode: init_blockmode,
|
||||
_word: PhantomData,
|
||||
},
|
||||
pins,
|
||||
}
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_clock(&mut self, spi_clk: Hertz) {
|
||||
self.spi_base.cfg_clock(spi_clk);
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_mode(&mut self, mode: Mode) {
|
||||
self.spi_base.cfg_mode(mode);
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn perid(&self) -> u32 {
|
||||
self.spi_base.perid()
|
||||
}
|
||||
|
||||
pub fn cfg_transfer<HwCs: OptionalHwCs<$SPIX>>(&mut self, transfer_cfg: &TransferConfig<HwCs>) {
|
||||
self.spi_base.cfg_transfer(transfer_cfg);
|
||||
}
|
||||
|
||||
/// Releases the SPI peripheral and associated pins
|
||||
pub fn release(self) -> ($SPIX, (Sck, Miso, Mosi), SpiConfig) {
|
||||
(self.spi_base.spi, self.pins, self.spi_base.cfg)
|
||||
}
|
||||
|
||||
pub fn downgrade(self) -> SpiBase<$SPIX, WORD> {
|
||||
self.spi_base
|
||||
}
|
||||
}
|
||||
|
||||
impl<WORD: Word> SpiBase<$SPIX, WORD> {
|
||||
#[inline]
|
||||
pub fn cfg_clock(&mut self, spi_clk: Hertz) {
|
||||
let clk_prescale = self.sys_clk.0 / (spi_clk.0 * (self.cfg.scrdv as u32 + 1));
|
||||
self.spi
|
||||
.clkprescale
|
||||
.write(|w| unsafe { w.bits(clk_prescale) });
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn cfg_mode(&mut self, mode: Mode) {
|
||||
let (cpo_bit, cph_bit) = match mode {
|
||||
MODE_0 => (false, false),
|
||||
MODE_1 => (false, true),
|
||||
MODE_2 => (true, false),
|
||||
MODE_3 => (true, true),
|
||||
};
|
||||
self.spi.ctrl0.modify(|_, w| {
|
||||
w.spo().bit(cpo_bit);
|
||||
w.sph().bit(cph_bit)
|
||||
});
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn perid(&self) -> u32 {
|
||||
self.spi.perid.read().bits()
|
||||
}
|
||||
|
||||
pub fn cfg_transfer<HwCs: OptionalHwCs<$SPIX>>(&mut self, transfer_cfg: &TransferConfig<HwCs>) {
|
||||
self.cfg_clock(transfer_cfg.spi_clk);
|
||||
self.cfg_mode(transfer_cfg.mode);
|
||||
self.blockmode = transfer_cfg.blockmode;
|
||||
self.spi.ctrl1.modify(|_, w| {
|
||||
if transfer_cfg.sod {
|
||||
w.sod().set_bit();
|
||||
} else if transfer_cfg.hw_cs.is_some() {
|
||||
w.sod().clear_bit();
|
||||
unsafe {
|
||||
w.ss().bits(HwCs::CS_ID as u8);
|
||||
}
|
||||
} else {
|
||||
w.sod().clear_bit();
|
||||
}
|
||||
if transfer_cfg.blockmode {
|
||||
w.blockmode().set_bit();
|
||||
} else {
|
||||
w.blockmode().clear_bit();
|
||||
}
|
||||
w
|
||||
});
|
||||
}
|
||||
}
|
||||
|
||||
/// Changing the word size also requires a type conversion
|
||||
impl <Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>>
|
||||
From<Spi<$SPIX, (Sck, Miso, Mosi), u8>> for Spi<$SPIX, (Sck, Miso, Mosi), u16>
|
||||
{
|
||||
fn from(
|
||||
old_spi: Spi<$SPIX, (Sck, Miso, Mosi), u8>
|
||||
) -> Self {
|
||||
old_spi.spi_base.spi.ctrl0.modify(|_, w| {
|
||||
unsafe {
|
||||
w.size().bits(WordSize::SixteenBits as u8)
|
||||
}
|
||||
});
|
||||
Spi {
|
||||
spi_base: SpiBase {
|
||||
spi: old_spi.spi_base.spi,
|
||||
cfg: old_spi.spi_base.cfg,
|
||||
blockmode: old_spi.spi_base.blockmode,
|
||||
sys_clk: old_spi.spi_base.sys_clk,
|
||||
_word: PhantomData,
|
||||
},
|
||||
pins: old_spi.pins,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Changing the word size also requires a type conversion
|
||||
impl <Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>>
|
||||
From<Spi<$SPIX, (Sck, Miso, Mosi), u16>> for
|
||||
Spi<$SPIX, (Sck, Miso, Mosi), u8>
|
||||
{
|
||||
fn from(
|
||||
old_spi: Spi<$SPIX, (Sck, Miso, Mosi), u16>
|
||||
) -> Self {
|
||||
old_spi.spi_base.spi.ctrl0.modify(|_, w| {
|
||||
unsafe {
|
||||
w.size().bits(WordSize::EightBits as u8)
|
||||
}
|
||||
});
|
||||
Spi {
|
||||
spi_base: SpiBase {
|
||||
spi: old_spi.spi_base.spi,
|
||||
cfg: old_spi.spi_base.cfg,
|
||||
blockmode: old_spi.spi_base.blockmode,
|
||||
sys_clk: old_spi.spi_base.sys_clk,
|
||||
_word: PhantomData,
|
||||
},
|
||||
pins: old_spi.pins,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
$(
|
||||
|
||||
impl FullDuplex<$WORD> for SpiBase<$SPIX, $WORD>
|
||||
{
|
||||
type Error = Infallible;
|
||||
|
||||
/// Sends a word to the slave
|
||||
#[inline(always)]
|
||||
fn send(&mut self, word: $WORD) -> nb::Result<(), Self::Error> {
|
||||
if self.spi.status.read().tnf().bit_is_clear() {
|
||||
return Err(nb::Error::WouldBlock);
|
||||
}
|
||||
self.spi.data.write(|w| unsafe { w.bits(word as u32) });
|
||||
Ok(())
|
||||
}
|
||||
|
||||
/// Read a word from the slave. Must be preceeded by a [`send`](Self::send) call
|
||||
#[inline(always)]
|
||||
fn read(&mut self) -> nb::Result<$WORD, Self::Error> {
|
||||
if self.spi.status.read().rne().bit_is_clear() {
|
||||
return Err(nb::Error::WouldBlock);
|
||||
}
|
||||
Ok((self.spi.data.read().bits() & 0xffff) as $WORD)
|
||||
}
|
||||
}
|
||||
|
||||
impl<Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>>
|
||||
FullDuplex<$WORD> for Spi<$SPIX, (Sck, Miso, Mosi), $WORD>
|
||||
{
|
||||
type Error = Infallible;
|
||||
|
||||
#[inline(always)]
|
||||
fn read(&mut self) -> nb::Result<$WORD, Self::Error> {
|
||||
self.spi_base.read()
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn send(&mut self, word: $WORD) -> nb::Result<(), Self::Error> {
|
||||
self.spi_base.send(word)
|
||||
}
|
||||
}
|
||||
|
||||
impl SpiBase<$SPIX, $WORD>
|
||||
where SpiBase<$SPIX, $WORD>: FullDuplex<$WORD>
|
||||
{
|
||||
/// Internal implementation for blocking::spi::Transfer and
|
||||
/// blocking::spi::Write using the FIFO
|
||||
fn transfer_internal<'w>(
|
||||
&mut self,
|
||||
write_words: &'w [$WORD],
|
||||
read_words: Option<&'w mut [$WORD]>,
|
||||
) -> Result<(), Infallible> {
|
||||
// FIFO has a depth of 16.
|
||||
const FIFO_WORDS: usize = 12;
|
||||
|
||||
if self.blockmode {
|
||||
self.spi.ctrl1.modify(|_, w| {
|
||||
w.mtxpause().set_bit()
|
||||
})
|
||||
}
|
||||
// Fill the first half of the write FIFO
|
||||
let len = write_words.len();
|
||||
let mut write = write_words.iter();
|
||||
for _ in 0..core::cmp::min(FIFO_WORDS, len) {
|
||||
nb::block!(self.send(*write.next().unwrap())).ok().unwrap();
|
||||
}
|
||||
if self.blockmode {
|
||||
self.spi.ctrl1.modify(|_, w| {
|
||||
w.mtxpause().clear_bit()
|
||||
})
|
||||
}
|
||||
if let Some(read) = read_words {
|
||||
let mut read = read.iter_mut();
|
||||
|
||||
// Continue filling write FIFO and emptying read FIFO
|
||||
for word in write {
|
||||
nb::block!(self.send(*word)).ok().unwrap();
|
||||
*read.next().unwrap() = nb::block!(self.read()).ok().unwrap();
|
||||
}
|
||||
|
||||
// Finish emptying the read FIFO
|
||||
for word in read {
|
||||
*word = nb::block!(self.read()).ok().unwrap();
|
||||
}
|
||||
} else {
|
||||
// Continue filling write FIFO and emptying read FIFO
|
||||
for word in write {
|
||||
nb::block!(self.send(*word)).ok().unwrap();
|
||||
let _ = nb::block!(self.read()).ok().unwrap();
|
||||
}
|
||||
|
||||
// Dummy read from the read FIFO
|
||||
for _ in 0..core::cmp::min(FIFO_WORDS, len) {
|
||||
let _ = nb::block!(self.read()).ok().unwrap();
|
||||
}
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
impl<Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>>
|
||||
Spi<$SPIX, (Sck, Miso, Mosi), $WORD>
|
||||
where Spi<$SPIX, (Sck, Miso, Mosi), $WORD>: FullDuplex<$WORD>
|
||||
{
|
||||
/// Internal implementation for blocking::spi::Transfer and
|
||||
/// blocking::spi::Write using the FIFO
|
||||
fn transfer_internal<'w>(
|
||||
&mut self,
|
||||
write_words: &'w [$WORD],
|
||||
read_words: Option<&'w mut [$WORD]>,
|
||||
) -> Result<(), Infallible> {
|
||||
return self.spi_base.transfer_internal(write_words, read_words)
|
||||
}
|
||||
}
|
||||
|
||||
impl blocking::spi::Transfer<$WORD> for SpiBase<$SPIX, $WORD>
|
||||
where
|
||||
SpiBase<$SPIX, $WORD>: FullDuplex<$WORD>
|
||||
{
|
||||
type Error = Infallible;
|
||||
|
||||
fn transfer<'w>(
|
||||
&mut self,
|
||||
words: &'w mut [$WORD]
|
||||
) -> Result<&'w [$WORD], Self::Error> {
|
||||
if words.is_empty() {
|
||||
return Ok(words);
|
||||
}
|
||||
// SAFETY: transfer_internal always writes out bytes
|
||||
// before modifying them
|
||||
let write = unsafe {
|
||||
core::slice::from_raw_parts(words.as_ptr(), words.len())
|
||||
};
|
||||
self.transfer_internal(write, Some(words))?;
|
||||
Ok(words)
|
||||
}
|
||||
}
|
||||
|
||||
impl<Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>>
|
||||
blocking::spi::Transfer<$WORD> for Spi<$SPIX, (Sck, Miso, Mosi), $WORD>
|
||||
where
|
||||
Spi<$SPIX, (Sck, Miso, Mosi), $WORD>: FullDuplex<$WORD>,
|
||||
{
|
||||
type Error = Infallible;
|
||||
|
||||
fn transfer<'w>(
|
||||
&mut self,
|
||||
words: &'w mut [$WORD]
|
||||
) -> Result<&'w [$WORD], Self::Error> {
|
||||
self.spi_base.transfer(words)
|
||||
}
|
||||
}
|
||||
|
||||
impl blocking::spi::Write<$WORD> for SpiBase<$SPIX, $WORD>
|
||||
where
|
||||
SpiBase<$SPIX, $WORD>: FullDuplex<$WORD>
|
||||
{
|
||||
type Error = Infallible;
|
||||
fn write(&mut self, words: &[$WORD]) -> Result<(), Self::Error> {
|
||||
self.transfer_internal(words, None)
|
||||
}
|
||||
}
|
||||
|
||||
impl<Sck: PinSck<$SPIX>, Miso: PinMiso<$SPIX>, Mosi: PinMosi<$SPIX>>
|
||||
blocking::spi::Write<$WORD> for Spi<$SPIX, (Sck, Miso, Mosi), $WORD>
|
||||
where
|
||||
Spi<$SPIX, (Sck, Miso, Mosi), $WORD>: FullDuplex<$WORD>,
|
||||
{
|
||||
type Error = Infallible;
|
||||
fn write(&mut self, words: &[$WORD]) -> Result<(), Self::Error> {
|
||||
self.transfer_internal(words, None)
|
||||
}
|
||||
}
|
||||
)+
|
||||
|
||||
)+
|
||||
}
|
||||
}
|
||||
|
||||
spi!(
|
||||
SPIA: (spia, PeripheralClocks::Spi0) => (u8, u16),
|
||||
SPIB: (spib, PeripheralClocks::Spi1) => (u8, u16),
|
||||
SPIC: (spic, PeripheralClocks::Spi2) => (u8, u16),
|
||||
);
|
||||
144
src/timer.rs
144
src/timer.rs
|
|
@ -10,17 +10,26 @@ use crate::{
|
|||
time::Hertz,
|
||||
timer,
|
||||
};
|
||||
use embedded_hal::timer::{Cancel, CountDown, Periodic};
|
||||
use core::cell::Cell;
|
||||
use cortex_m::interrupt::Mutex;
|
||||
use embedded_hal::{
|
||||
blocking::delay,
|
||||
timer::{Cancel, CountDown, Periodic},
|
||||
};
|
||||
use va108xx::{Interrupt, IRQSEL, SYSCONFIG};
|
||||
use void::Void;
|
||||
|
||||
const IRQ_DST_NONE: u32 = 0xffffffff;
|
||||
pub static MS_COUNTER: Mutex<Cell<u32>> = Mutex::new(Cell::new(0));
|
||||
|
||||
/// Hardware timers
|
||||
pub struct CountDownTimer<TIM> {
|
||||
tim: TIM,
|
||||
curr_freq: Hertz,
|
||||
sys_clk: Hertz,
|
||||
rst_val: u32,
|
||||
last_cnt: u32,
|
||||
listening: bool,
|
||||
}
|
||||
|
||||
/// Interrupt events
|
||||
|
|
@ -57,6 +66,9 @@ macro_rules! timers {
|
|||
CountDownTimer {
|
||||
tim,
|
||||
sys_clk,
|
||||
rst_val: 0,
|
||||
curr_freq: 0.hz(),
|
||||
listening: false,
|
||||
last_cnt: 0,
|
||||
}
|
||||
}
|
||||
|
|
@ -76,6 +88,7 @@ macro_rules! timers {
|
|||
enable_peripheral_clock(syscfg, PeripheralClocks::Irqsel);
|
||||
irqsel.tim[$i].write(|w| unsafe { w.bits(interrupt as u32) });
|
||||
self.tim.ctrl.modify(|_, w| w.irq_enb().set_bit());
|
||||
self.listening = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -88,6 +101,7 @@ macro_rules! timers {
|
|||
enable_peripheral_clock(syscfg, PeripheralClocks::Irqsel);
|
||||
irqsel.tim[$i].write(|w| unsafe { w.bits(IRQ_DST_NONE) });
|
||||
self.tim.ctrl.modify(|_, w| w.irq_enb().clear_bit());
|
||||
self.listening = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -117,6 +131,14 @@ macro_rules! timers {
|
|||
}
|
||||
self
|
||||
}
|
||||
|
||||
pub fn curr_freq(&self) -> Hertz {
|
||||
self.curr_freq
|
||||
}
|
||||
|
||||
pub fn listening(&self) -> bool {
|
||||
self.listening
|
||||
}
|
||||
}
|
||||
|
||||
/// CountDown implementation for TIMx
|
||||
|
|
@ -127,21 +149,28 @@ macro_rules! timers {
|
|||
where
|
||||
T: Into<Hertz>,
|
||||
{
|
||||
self.last_cnt = self.sys_clk.0 / timeout.into().0 - 1;
|
||||
self.tim.ctrl.modify(|_, w| w.enable().clear_bit());
|
||||
self.curr_freq = timeout.into();
|
||||
self.rst_val = self.sys_clk.0 / self.curr_freq.0;
|
||||
unsafe {
|
||||
self.tim.rst_value.write(|w| w.bits(self.last_cnt));
|
||||
self.tim.cnt_value.write(|w| w.bits(self.last_cnt));
|
||||
self.tim.rst_value.write(|w| w.bits(self.rst_val));
|
||||
self.tim.cnt_value.write(|w| w.bits(self.rst_val));
|
||||
}
|
||||
self.tim.ctrl.modify(|_, w| w.enable().set_bit());
|
||||
}
|
||||
|
||||
/// Return `Ok` if the timer has wrapped
|
||||
/// Automatically clears the flag and restarts the time
|
||||
/// Return `Ok` if the timer has wrapped. Peripheral will automatically clear the
|
||||
/// flag and restart the time if configured correctly
|
||||
fn wait(&mut self) -> nb::Result<(), Void> {
|
||||
let cnt = self.tim.cnt_value.read().bits();
|
||||
if cnt == 0 || cnt < self.last_cnt {
|
||||
self.last_cnt = cnt;
|
||||
if cnt > self.last_cnt {
|
||||
self.last_cnt = self.rst_val;
|
||||
Ok(())
|
||||
} else if cnt == 0 {
|
||||
self.last_cnt = self.rst_val;
|
||||
Ok(())
|
||||
} else {
|
||||
self.last_cnt = cnt;
|
||||
Err(nb::Error::WouldBlock)
|
||||
}
|
||||
}
|
||||
|
|
@ -159,6 +188,60 @@ macro_rules! timers {
|
|||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
/// Delay for microseconds.
|
||||
///
|
||||
/// For delays less than 100 us, an assembly delay will be used.
|
||||
/// For larger delays, the timer peripheral will be used.
|
||||
/// Please note that the delay using the peripheral might not
|
||||
/// work properly in debug mode.
|
||||
impl delay::DelayUs<u32> for CountDownTimer<$TIM> {
|
||||
fn delay_us(&mut self, us: u32) {
|
||||
if(us < 100) {
|
||||
cortex_m::asm::delay(us * (self.sys_clk.0 / 2_000_000));
|
||||
} else {
|
||||
// Configuring the peripheral for higher frequencies is unstable
|
||||
self.start(1000.khz());
|
||||
// The subtracted value is an empirical value measures by using tests with
|
||||
// an oscilloscope.
|
||||
for _ in 0..us - 7 {
|
||||
nb::block!(self.wait()).unwrap();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
/// Forwards call to u32 variant of delay
|
||||
impl delay::DelayUs<u16> for CountDownTimer<$TIM> {
|
||||
fn delay_us(&mut self, us: u16) {
|
||||
self.delay_us(u32::from(us));
|
||||
}
|
||||
}
|
||||
/// Forwards call to u32 variant of delay
|
||||
impl delay::DelayUs<u8> for CountDownTimer<$TIM> {
|
||||
fn delay_us(&mut self, us: u8) {
|
||||
self.delay_us(u32::from(us));
|
||||
}
|
||||
}
|
||||
|
||||
impl delay::DelayMs<u32> for CountDownTimer<$TIM> {
|
||||
fn delay_ms(&mut self, ms: u32) {
|
||||
self.start(1000.hz());
|
||||
for _ in 0..ms {
|
||||
nb::block!(self.wait()).unwrap();
|
||||
}
|
||||
}
|
||||
}
|
||||
impl delay::DelayMs<u16> for CountDownTimer<$TIM> {
|
||||
fn delay_ms(&mut self, ms: u16) {
|
||||
self.delay_ms(u32::from(ms));
|
||||
}
|
||||
}
|
||||
impl embedded_hal::blocking::delay::DelayMs<u8> for CountDownTimer<$TIM> {
|
||||
fn delay_ms(&mut self, ms: u8) {
|
||||
self.delay_ms(u32::from(ms));
|
||||
}
|
||||
}
|
||||
|
||||
)+
|
||||
}
|
||||
}
|
||||
|
|
@ -171,10 +254,26 @@ pub fn set_up_ms_timer(
|
|||
sys_clk: Hertz,
|
||||
tim0: TIM0,
|
||||
irq: pac::Interrupt,
|
||||
) {
|
||||
) -> CountDownTimer<TIM0> {
|
||||
let mut ms_timer = CountDownTimer::tim0(syscfg, sys_clk, tim0);
|
||||
ms_timer.listen(timer::Event::TimeOut, syscfg, irqsel, irq);
|
||||
ms_timer.start(1000.hz());
|
||||
ms_timer
|
||||
}
|
||||
|
||||
/// This function can be called in a specified interrupt handler to increment
|
||||
/// the MS counter
|
||||
pub fn default_ms_irq_handler() {
|
||||
cortex_m::interrupt::free(|cs| {
|
||||
let mut ms = MS_COUNTER.borrow(cs).get();
|
||||
ms += 1;
|
||||
MS_COUNTER.borrow(cs).set(ms);
|
||||
});
|
||||
}
|
||||
|
||||
/// Get the current MS tick count
|
||||
pub fn get_ms_ticks() -> u32 {
|
||||
cortex_m::interrupt::free(|cs| MS_COUNTER.borrow(cs).get())
|
||||
}
|
||||
|
||||
timers! {
|
||||
|
|
@ -203,3 +302,30 @@ timers! {
|
|||
TIM22: (tim22, 22),
|
||||
TIM23: (tim23, 23),
|
||||
}
|
||||
|
||||
//==================================================================================================
|
||||
// Delay implementations
|
||||
//==================================================================================================
|
||||
|
||||
pub struct Delay {
|
||||
cd_tim: CountDownTimer<TIM0>,
|
||||
}
|
||||
|
||||
impl Delay {
|
||||
pub fn new(tim0: CountDownTimer<TIM0>) -> Self {
|
||||
Delay { cd_tim: tim0 }
|
||||
}
|
||||
}
|
||||
|
||||
/// This assumes that the user has already set up a MS tick timer in TIM0 as a system tick
|
||||
impl embedded_hal::blocking::delay::DelayMs<u32> for Delay {
|
||||
fn delay_ms(&mut self, ms: u32) {
|
||||
if self.cd_tim.curr_freq() != 1000.hz() || !self.cd_tim.listening() {
|
||||
return;
|
||||
}
|
||||
let start_time = get_ms_ticks();
|
||||
while get_ms_ticks() - start_time < ms {
|
||||
cortex_m::asm::nop();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -12,8 +12,8 @@ impl Sealed for NoneT {}
|
|||
|
||||
/// Marker trait for type identity
|
||||
///
|
||||
/// This trait is used as part of the [`AnyKind`] trait pattern. It represents
|
||||
/// the concept of type identity, because all implementors have
|
||||
/// This trait is used as part of the [`AnyKind`](https://docs.rs/atsamd-hal/0.13.0/atsamd_hal/typelevel/index.html)
|
||||
/// trait pattern. It represents the concept of type identity, because all implementors have
|
||||
/// `<Self as Is>::Type == Self`. When used as a trait bound with a specific
|
||||
/// type, it guarantees that the corresponding type parameter is exactly the
|
||||
/// specific type. Stated differently, it guarantees that `T == Specific` in
|
||||
|
|
|
|||
28
src/uart.rs
28
src/uart.rs
|
|
@ -11,8 +11,8 @@ use crate::clock::enable_peripheral_clock;
|
|||
use crate::{
|
||||
clock,
|
||||
gpio::pins::{
|
||||
Alternate, Funsel1, Funsel2, Funsel3, Pin, PA16, PA17, PA18, PA19, PA2, PA26, PA27, PA3,
|
||||
PA30, PA31, PA8, PA9, PB18, PB19, PB20, PB21, PB22, PB23, PB6, PB7, PB8, PB9,
|
||||
AltFunc1, AltFunc2, AltFunc3, Pin, PA16, PA17, PA18, PA19, PA2, PA26, PA27, PA3, PA30,
|
||||
PA31, PA8, PA9, PB18, PB19, PB20, PB21, PB22, PB23, PB6, PB7, PB8, PB9,
|
||||
},
|
||||
pac::{uarta as uart_base, SYSCONFIG, UARTA, UARTB},
|
||||
prelude::*,
|
||||
|
|
@ -23,20 +23,20 @@ use embedded_hal::{blocking, serial};
|
|||
|
||||
pub trait Pins<UART> {}
|
||||
|
||||
impl Pins<UARTA> for (Pin<PA9, Alternate<Funsel2>>, Pin<PA8, Alternate<Funsel2>>) {}
|
||||
impl Pins<UARTA> for (Pin<PA17, Alternate<Funsel3>>, Pin<PA16, Alternate<Funsel3>>) {}
|
||||
impl Pins<UARTA> for (Pin<PA31, Alternate<Funsel3>>, Pin<PA30, Alternate<Funsel3>>) {}
|
||||
impl Pins<UARTA> for (Pin<PA9, AltFunc2>, Pin<PA8, AltFunc2>) {}
|
||||
impl Pins<UARTA> for (Pin<PA17, AltFunc3>, Pin<PA16, AltFunc3>) {}
|
||||
impl Pins<UARTA> for (Pin<PA31, AltFunc3>, Pin<PA30, AltFunc3>) {}
|
||||
|
||||
impl Pins<UARTA> for (Pin<PB9, Alternate<Funsel1>>, Pin<PB8, Alternate<Funsel1>>) {}
|
||||
impl Pins<UARTA> for (Pin<PB23, Alternate<Funsel1>>, Pin<PB22, Alternate<Funsel1>>) {}
|
||||
impl Pins<UARTA> for (Pin<PB9, AltFunc1>, Pin<PB8, AltFunc1>) {}
|
||||
impl Pins<UARTA> for (Pin<PB23, AltFunc1>, Pin<PB22, AltFunc1>) {}
|
||||
|
||||
impl Pins<UARTB> for (Pin<PA3, Alternate<Funsel2>>, Pin<PA2, Alternate<Funsel2>>) {}
|
||||
impl Pins<UARTB> for (Pin<PA19, Alternate<Funsel3>>, Pin<PA18, Alternate<Funsel3>>) {}
|
||||
impl Pins<UARTB> for (Pin<PA27, Alternate<Funsel3>>, Pin<PA26, Alternate<Funsel3>>) {}
|
||||
impl Pins<UARTB> for (Pin<PA3, AltFunc2>, Pin<PA2, AltFunc2>) {}
|
||||
impl Pins<UARTB> for (Pin<PA19, AltFunc3>, Pin<PA18, AltFunc3>) {}
|
||||
impl Pins<UARTB> for (Pin<PA27, AltFunc3>, Pin<PA26, AltFunc3>) {}
|
||||
|
||||
impl Pins<UARTB> for (Pin<PB7, Alternate<Funsel1>>, Pin<PB6, Alternate<Funsel1>>) {}
|
||||
impl Pins<UARTB> for (Pin<PB19, Alternate<Funsel2>>, Pin<PB18, Alternate<Funsel2>>) {}
|
||||
impl Pins<UARTB> for (Pin<PB21, Alternate<Funsel1>>, Pin<PB20, Alternate<Funsel1>>) {}
|
||||
impl Pins<UARTB> for (Pin<PB7, AltFunc1>, Pin<PB6, AltFunc1>) {}
|
||||
impl Pins<UARTB> for (Pin<PB19, AltFunc2>, Pin<PB18, AltFunc2>) {}
|
||||
impl Pins<UARTB> for (Pin<PB21, AltFunc1>, Pin<PB20, AltFunc1>) {}
|
||||
|
||||
#[derive(Debug)]
|
||||
pub enum Error {
|
||||
|
|
@ -46,7 +46,7 @@ pub enum Error {
|
|||
BreakCondition,
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone, PartialEq)]
|
||||
#[derive(Debug, PartialEq, Copy, Clone)]
|
||||
pub enum Event {
|
||||
// Receiver FIFO interrupt enable. Generates interrupt
|
||||
// when FIFO is at least half full. Half full is defined as FIFO
|
||||
|
|
|
|||
Loading…
Reference in New Issue