Major refactoring
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- Improved IRQ handling, which makes most unsafe unmask operations in user code absolete - Add first UART RX handlers which use an IRQ
This commit is contained in:
parent
dc2426a905
commit
f376a43f41
16
Cargo.toml
16
Cargo.toml
@ -45,19 +45,3 @@ opt-level = "s"
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# [profile.release-lto]
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# inherits = "release"
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# lto = true
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[[example]]
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name = "timer-ticks"
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required-features = ["rt"]
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[[example]]
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name = "tests"
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required-features = ["rt"]
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[[example]]
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name = "pwm"
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required-features = ["rt"]
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[[example]]
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name = "cascade"
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required-features = ["rt"]
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@ -9,7 +9,7 @@
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use cortex_m_rt::entry;
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use embedded_hal::digital::v2::ToggleableOutputPin;
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use panic_halt as _;
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use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::set_up_ms_timer};
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use va108xx_hal::{gpio::PinsA, pac, prelude::*, timer::CountDownTimer};
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#[entry]
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fn main() -> ! {
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@ -18,13 +18,7 @@ fn main() -> ! {
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let mut led1 = porta.pa10.into_push_pull_output();
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let mut led2 = porta.pa7.into_push_pull_output();
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let mut led3 = porta.pa6.into_push_pull_output();
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let mut delay = set_up_ms_timer(
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&mut dp.SYSCONFIG,
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&mut dp.IRQSEL,
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50.mhz().into(),
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dp.TIM0,
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pac::Interrupt::OC0,
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);
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let mut delay = CountDownTimer::new(&mut dp.SYSCONFIG, 50.mhz(), dp.TIM0);
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for _ in 0..10 {
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led1.set_low().ok();
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led2.set_low().ok();
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@ -14,8 +14,8 @@ use va108xx_hal::{
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pac::{self, interrupt, TIM4, TIM5},
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prelude::*,
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timer::{
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default_ms_irq_handler, set_up_ms_timer, CascadeCtrl, CascadeSource, CountDownTimer, Delay,
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Event,
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default_ms_irq_handler, set_up_ms_delay_provider, CascadeCtrl, CascadeSource,
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CountDownTimer, Event, IrqCfg,
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},
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};
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@ -28,23 +28,16 @@ fn main() -> ! {
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rprintln!("-- VA108xx Cascade example application--");
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let mut dp = pac::Peripherals::take().unwrap();
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let timer = set_up_ms_timer(
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&mut dp.SYSCONFIG,
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&mut dp.IRQSEL,
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50.mhz().into(),
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dp.TIM0,
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pac::Interrupt::OC0,
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);
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let mut delay = Delay::new(timer);
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let mut delay = set_up_ms_delay_provider(&mut dp.SYSCONFIG, 50.mhz(), dp.TIM0);
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// Will be started periodically to trigger a cascade
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let mut cascade_triggerer =
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CountDownTimer::new(&mut dp.SYSCONFIG, 50.mhz(), dp.TIM3).auto_disable(true);
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cascade_triggerer.listen(
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Event::TimeOut,
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&mut dp.SYSCONFIG,
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&mut dp.IRQSEL,
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va108xx::Interrupt::OC1,
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IrqCfg::new(va108xx::Interrupt::OC1, true, false),
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Some(&mut dp.IRQSEL),
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Some(&mut dp.SYSCONFIG),
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);
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// First target for cascade
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@ -63,9 +56,9 @@ fn main() -> ! {
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// the timer expires
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cascade_target_1.listen(
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Event::TimeOut,
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&mut dp.SYSCONFIG,
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&mut dp.IRQSEL,
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va108xx::Interrupt::OC2,
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IrqCfg::new(va108xx::Interrupt::OC2, true, false),
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Some(&mut dp.IRQSEL),
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Some(&mut dp.SYSCONFIG),
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);
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// The counter will only activate when the cascade signal is coming in so
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// it is okay to call start here to set the reset value
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@ -89,9 +82,9 @@ fn main() -> ! {
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// the timer expires
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cascade_target_2.listen(
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Event::TimeOut,
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&mut dp.SYSCONFIG,
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&mut dp.IRQSEL,
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va108xx::Interrupt::OC3,
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IrqCfg::new(va108xx::Interrupt::OC3, true, false),
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Some(&mut dp.IRQSEL),
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Some(&mut dp.SYSCONFIG),
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);
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// The counter will only activate when the cascade signal is coming in so
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// it is okay to call start here to set the reset value
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@ -112,7 +105,7 @@ fn main() -> ! {
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loop {
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rprintln!("-- Triggering cascade in 0.5 seconds --");
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cascade_triggerer.start(2.hz());
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delay.delay_ms(5000);
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delay.delay_ms(5000_u16);
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}
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}
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@ -8,10 +8,10 @@ use panic_rtt_target as _;
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use rtt_target::{rprintln, rtt_init_print};
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use va108xx_hal::{
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gpio::PinsA,
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pac::{self, interrupt},
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pac,
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prelude::*,
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pwm::{self, get_duty_from_percent, ReducedPwmPin, PWMA, PWMB},
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timer::{default_ms_irq_handler, set_up_ms_timer, Delay},
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timer::set_up_ms_delay_provider,
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};
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#[entry]
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@ -26,17 +26,7 @@ fn main() -> ! {
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&mut dp.SYSCONFIG,
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10.hz(),
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);
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let timer = set_up_ms_timer(
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&mut dp.SYSCONFIG,
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&mut dp.IRQSEL,
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50.mhz().into(),
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dp.TIM0,
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pac::Interrupt::OC0,
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);
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let mut delay = Delay::new(timer);
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unsafe {
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cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC0);
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}
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let mut delay = set_up_ms_delay_provider(&mut dp.SYSCONFIG, 50.mhz(), dp.TIM0);
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let mut current_duty_cycle = 0.0;
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PwmPin::set_duty(&mut pwm, get_duty_from_percent(current_duty_cycle));
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PwmPin::enable(&mut pwm);
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@ -46,7 +36,7 @@ fn main() -> ! {
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loop {
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// Increase duty cycle continuously
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while current_duty_cycle < 1.0 {
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delay.delay_ms(200);
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delay.delay_ms(200_u16);
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current_duty_cycle += 0.02;
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PwmPin::set_duty(&mut reduced_pin, get_duty_from_percent(current_duty_cycle));
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}
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@ -60,7 +50,7 @@ fn main() -> ! {
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pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit));
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pwmb.set_pwmb_upper_limit(get_duty_from_percent(upper_limit));
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while lower_limit < 0.5 {
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delay.delay_ms(200);
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delay.delay_ms(200_u16);
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lower_limit += 0.01;
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upper_limit -= 0.01;
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pwmb.set_pwmb_lower_limit(get_duty_from_percent(lower_limit));
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@ -71,8 +61,3 @@ fn main() -> ! {
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reduced_pin = ReducedPwmPin::<PWMA>::from(pwmb);
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}
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}
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#[interrupt]
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fn OC0() {
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default_ms_irq_handler()
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}
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@ -14,7 +14,7 @@ use va108xx_hal::{
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pac::{self, interrupt},
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prelude::*,
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time::Hertz,
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timer::{default_ms_irq_handler, set_up_ms_timer, CountDownTimer, Delay},
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timer::{default_ms_irq_handler, set_up_ms_timer, CountDownTimer, Delay, IrqCfg},
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};
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#[allow(dead_code)]
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@ -146,15 +146,12 @@ fn main() -> ! {
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}
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TestCase::DelayMs => {
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let ms_timer = set_up_ms_timer(
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IrqCfg::new(pac::Interrupt::OC0, true, true),
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&mut dp.SYSCONFIG,
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&mut dp.IRQSEL,
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50.mhz().into(),
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Some(&mut dp.IRQSEL),
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50.mhz(),
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dp.TIM0,
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pac::Interrupt::OC0,
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);
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unsafe {
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cortex_m::peripheral::NVIC::unmask(pac::Interrupt::OC0);
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}
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let mut delay = Delay::new(ms_timer);
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for _ in 0..5 {
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led1.toggle().ok();
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@ -163,7 +160,7 @@ fn main() -> ! {
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delay.delay_ms(500);
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}
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let mut delay_timer = CountDownTimer::new(&mut dp.SYSCONFIG, 50.mhz().into(), dp.TIM1);
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let mut delay_timer = CountDownTimer::new(&mut dp.SYSCONFIG, 50.mhz(), dp.TIM1);
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let mut pa0 = pinsa.pa0.into_push_pull_output();
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for _ in 0..5 {
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led1.toggle().ok();
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@ -12,7 +12,7 @@ use va108xx_hal::{
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pac::{self, interrupt},
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prelude::*,
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time::Hertz,
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timer::{default_ms_irq_handler, set_up_ms_timer, CountDownTimer, Event, MS_COUNTER},
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timer::{default_ms_irq_handler, set_up_ms_timer, CountDownTimer, Event, IrqCfg, MS_COUNTER},
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};
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#[allow(dead_code)]
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@ -65,22 +65,21 @@ fn main() -> ! {
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}
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LibType::Hal => {
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set_up_ms_timer(
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IrqCfg::new(interrupt::OC0, true, true),
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&mut dp.SYSCONFIG,
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&mut dp.IRQSEL,
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50.mhz().into(),
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Some(&mut dp.IRQSEL),
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50.mhz(),
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dp.TIM0,
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interrupt::OC0,
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);
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let mut second_timer =
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CountDownTimer::new(&mut dp.SYSCONFIG, get_sys_clock().unwrap(), dp.TIM1);
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second_timer.listen(
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Event::TimeOut,
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&mut dp.SYSCONFIG,
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&mut dp.IRQSEL,
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interrupt::OC1,
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IrqCfg::new(interrupt::OC1, true, true),
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Some(&mut dp.IRQSEL),
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Some(&mut dp.SYSCONFIG),
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);
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second_timer.start(1.hz());
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unmask_irqs();
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}
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}
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loop {
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44
examples/uart-irq.rs
Normal file
44
examples/uart-irq.rs
Normal file
@ -0,0 +1,44 @@
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//! UART example application. Sends a test string over a UART and then enters
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//! echo mode
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#![no_main]
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#![no_std]
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use core::fmt::Write;
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use cortex_m_rt::entry;
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use panic_rtt_target as _;
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use rtt_target::{rprintln, rtt_init_print};
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use va108xx_hal::{gpio::PinsB, pac, prelude::*, uart};
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#[entry]
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fn main() -> ! {
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rtt_init_print!();
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rprintln!("-- VA108xx UART example application--");
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let mut dp = pac::Peripherals::take().unwrap();
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let gpiob = PinsB::new(&mut dp.SYSCONFIG, Some(dp.IOCONFIG), dp.PORTB);
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let tx = gpiob.pb21.into_funsel_1();
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let rx = gpiob.pb20.into_funsel_1();
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let uartb = uart::Uart::uartb(
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dp.UARTB,
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(tx, rx),
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115200.bps(),
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&mut dp.SYSCONFIG,
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50.mhz(),
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);
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let (mut tx, mut rx) = uartb.split();
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writeln!(tx, "Hello World\r").unwrap();
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loop {
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// Echo what is received on the serial link.
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match rx.read() {
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Ok(recv) => {
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nb::block!(tx.write(recv)).expect("TX send error");
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}
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Err(nb::Error::WouldBlock) => (),
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Err(nb::Error::Other(uart_error)) => {
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rprintln!("UART receive error {:?}", uart_error);
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}
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}
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}
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}
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@ -66,8 +66,8 @@ use super::{
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};
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use crate::{
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clock::FilterClkSel,
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pac::{self, IRQSEL, SYSCONFIG},
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utility::Funsel,
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pac::{IRQSEL, SYSCONFIG},
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utility::{IrqCfg, Funsel},
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};
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use embedded_hal::digital::v2::{InputPin, OutputPin, ToggleableOutputPin};
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use paste::paste;
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@ -344,14 +344,14 @@ impl DynPin {
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pub fn interrupt_edge(
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mut self,
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edge_type: InterruptEdge,
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irq_cfg: IrqCfg,
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syscfg: Option<&mut SYSCONFIG>,
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irqsel: &mut IRQSEL,
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interrupt: pac::Interrupt,
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irqsel: Option<&mut IRQSEL>
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) -> Result<Self, PinError> {
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match self.mode {
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DynPinMode::Input(_) | DynPinMode::Output(_) => {
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self._irq_enb(syscfg, irqsel, interrupt);
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self.regs.interrupt_edge(edge_type);
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self.irq_enb(irq_cfg, syscfg, irqsel);
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Ok(self)
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}
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_ => Err(PinError::InvalidPinType),
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@ -361,14 +361,14 @@ impl DynPin {
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pub fn interrupt_level(
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mut self,
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level_type: InterruptLevel,
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irq_cfg: IrqCfg,
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syscfg: Option<&mut SYSCONFIG>,
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irqsel: &mut IRQSEL,
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interrupt: crate::pac::Interrupt,
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irqsel: Option<&mut IRQSEL>
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) -> Result<Self, PinError> {
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match self.mode {
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DynPinMode::Input(_) | DynPinMode::Output(_) => {
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self._irq_enb(syscfg, irqsel, interrupt);
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self.regs.interrupt_level(level_type);
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self.irq_enb(irq_cfg, syscfg, irqsel);
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Ok(self)
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}
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_ => Err(PinError::InvalidPinType),
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@ -92,9 +92,10 @@
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use super::dynpins::{DynAlternate, DynGroup, DynInput, DynOutput, DynPinId, DynPinMode};
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use super::reg::RegisterInterface;
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use crate::{
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pac::{self, IOCONFIG, IRQSEL, PORTA, PORTB, SYSCONFIG},
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pac::{IOCONFIG, IRQSEL, PORTA, PORTB, SYSCONFIG},
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typelevel::Is,
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Sealed,
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utility::IrqCfg
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};
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use core::convert::Infallible;
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use core::marker::PhantomData;
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@ -360,6 +361,7 @@ impl<I: PinId, M: PinMode> AnyPin for Pin<I, M> {
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macro_rules! common_reg_if_functions {
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() => {
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paste!(
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#[inline]
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pub fn datamask(&self) -> bool {
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self.regs.datamask()
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@ -397,11 +399,11 @@ macro_rules! common_reg_if_functions {
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self.regs.write_pin_masked(false)
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}
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fn _irq_enb(
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fn irq_enb(
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&mut self,
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irq_cfg: crate::utility::IrqCfg,
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syscfg: Option<&mut va108xx::SYSCONFIG>,
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irqsel: &mut va108xx::IRQSEL,
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interrupt: va108xx::Interrupt,
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irqsel: Option<&mut va108xx::IRQSEL>
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) {
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if syscfg.is_some() {
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crate::clock::enable_peripheral_clock(
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@ -410,15 +412,19 @@ macro_rules! common_reg_if_functions {
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);
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}
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self.regs.enable_irq();
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if let Some(irqsel) = irqsel {
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if irq_cfg.route {
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match self.regs.id().group {
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// Set the correct interrupt number in the IRQSEL register
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DynGroup::A => {
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irqsel.porta[self.regs.id().num as usize]
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.write(|w| unsafe { w.bits(interrupt as u32) });
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.write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
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}
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DynGroup::B => {
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irqsel.portb[self.regs.id().num as usize]
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.write(|w| unsafe { w.bits(interrupt as u32) });
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.write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
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}
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}
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}
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}
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}
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@ -577,24 +583,24 @@ impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
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pub fn interrupt_edge(
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mut self,
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edge_type: InterruptEdge,
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irq_cfg: IrqCfg,
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syscfg: Option<&mut SYSCONFIG>,
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irqsel: &mut IRQSEL,
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interrupt: pac::Interrupt,
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irqsel: Option<&mut IRQSEL>
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) -> Self {
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self._irq_enb(syscfg, irqsel, interrupt);
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self.regs.interrupt_edge(edge_type);
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self.irq_enb(irq_cfg, syscfg, irqsel);
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self
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}
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pub fn interrupt_level(
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mut self,
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level_type: InterruptLevel,
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irq_cfg: IrqCfg,
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syscfg: Option<&mut SYSCONFIG>,
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irqsel: &mut IRQSEL,
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interrupt: pac::Interrupt,
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irqsel: Option<&mut IRQSEL>
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) -> Self {
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self._irq_enb(syscfg, irqsel, interrupt);
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self.regs.interrupt_level(level_type);
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self.irq_enb(irq_cfg, syscfg, irqsel);
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self
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}
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}
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@ -622,24 +628,24 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
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pub fn interrupt_edge(
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mut self,
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edge_type: InterruptEdge,
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irq_cfg: IrqCfg,
|
||||
syscfg: Option<&mut SYSCONFIG>,
|
||||
irqsel: &mut IRQSEL,
|
||||
interrupt: pac::Interrupt,
|
||||
irqsel: Option<&mut IRQSEL>
|
||||
) -> Self {
|
||||
self._irq_enb(syscfg, irqsel, interrupt);
|
||||
self.regs.interrupt_edge(edge_type);
|
||||
self.irq_enb(irq_cfg, syscfg, irqsel);
|
||||
self
|
||||
}
|
||||
|
||||
pub fn interrupt_level(
|
||||
mut self,
|
||||
level_type: InterruptLevel,
|
||||
irq_cfg: IrqCfg,
|
||||
syscfg: Option<&mut SYSCONFIG>,
|
||||
irqsel: &mut IRQSEL,
|
||||
interrupt: pac::Interrupt,
|
||||
irqsel: Option<&mut IRQSEL>
|
||||
) -> Self {
|
||||
self._irq_enb(syscfg, irqsel, interrupt);
|
||||
self.regs.interrupt_level(level_type);
|
||||
self.irq_enb(irq_cfg, syscfg, irqsel);
|
||||
self
|
||||
}
|
||||
}
|
||||
|
||||
66
src/timer.rs
66
src/timer.rs
@ -4,8 +4,10 @@
|
||||
//!
|
||||
//! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/timer-ticks.rs)
|
||||
//! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal/src/branch/main/examples/cascade.rs)
|
||||
pub use crate::utility::IrqCfg;
|
||||
use crate::{
|
||||
clock::{enable_peripheral_clock, PeripheralClocks},
|
||||
utility::unmask_irq,
|
||||
gpio::{
|
||||
AltFunc1, AltFunc2, AltFunc3, DynPinId, Pin, PinId, PA0, PA1, PA10, PA11, PA12, PA13, PA14,
|
||||
PA15, PA2, PA24, PA25, PA26, PA27, PA28, PA29, PA3, PA30, PA31, PA4, PA5, PA6, PA7, PA8,
|
||||
@ -27,7 +29,7 @@ use embedded_hal::{
|
||||
blocking::delay,
|
||||
timer::{Cancel, CountDown, Periodic},
|
||||
};
|
||||
use va108xx::{Interrupt, IRQSEL, SYSCONFIG};
|
||||
use va108xx::{IRQSEL, SYSCONFIG};
|
||||
use void::Void;
|
||||
|
||||
const IRQ_DST_NONE: u32 = 0xffffffff;
|
||||
@ -386,6 +388,7 @@ unsafe impl TimPinInterface for TimDynRegister {
|
||||
pub struct CountDownTimer<TIM: ValidTim> {
|
||||
tim: TimRegister<TIM>,
|
||||
curr_freq: Hertz,
|
||||
irq_cfg: Option<IrqCfg>,
|
||||
sys_clk: Hertz,
|
||||
rst_val: u32,
|
||||
last_cnt: u32,
|
||||
@ -482,6 +485,7 @@ impl<TIM: ValidTim> CountDownTimer<TIM> {
|
||||
let cd_timer = CountDownTimer {
|
||||
tim: unsafe { TimRegister::new(tim) },
|
||||
sys_clk: sys_clk.into(),
|
||||
irq_cfg: None,
|
||||
rst_val: 0,
|
||||
curr_freq: 0.hz(),
|
||||
listening: false,
|
||||
@ -491,21 +495,28 @@ impl<TIM: ValidTim> CountDownTimer<TIM> {
|
||||
cd_timer
|
||||
}
|
||||
|
||||
/// Listen for events. This also actives the IRQ in the IRQSEL register
|
||||
/// for the provided interrupt. It also actives the peripheral clock for
|
||||
/// IRQSEL
|
||||
/// Listen for events. Depending on the IRQ configuration, this also activates the IRQ in the
|
||||
/// IRQSEL peripheral for the provided interrupt and unmasks the interrupt
|
||||
pub fn listen(
|
||||
&mut self,
|
||||
event: Event,
|
||||
syscfg: &mut SYSCONFIG,
|
||||
irqsel: &mut IRQSEL,
|
||||
interrupt: Interrupt,
|
||||
irq_cfg: IrqCfg,
|
||||
irq_sel: Option<&mut IRQSEL>,
|
||||
sys_cfg: Option<&mut SYSCONFIG>,
|
||||
) {
|
||||
match event {
|
||||
Event::TimeOut => {
|
||||
enable_peripheral_clock(syscfg, PeripheralClocks::Irqsel);
|
||||
irqsel.tim[TIM::TIM_ID as usize].write(|w| unsafe { w.bits(interrupt as u32) });
|
||||
self.enable_interrupt();
|
||||
cortex_m::peripheral::NVIC::mask(irq_cfg.irq);
|
||||
self.irq_cfg = Some(irq_cfg);
|
||||
if irq_cfg.route {
|
||||
if let Some(sys_cfg) = sys_cfg {
|
||||
enable_peripheral_clock(sys_cfg, PeripheralClocks::Irqsel);
|
||||
}
|
||||
if let Some(irq_sel) = irq_sel {
|
||||
irq_sel.tim[TIM::TIM_ID as usize]
|
||||
.write(|w| unsafe { w.bits(irq_cfg.irq as u32) });
|
||||
}
|
||||
}
|
||||
self.listening = true;
|
||||
}
|
||||
}
|
||||
@ -554,6 +565,12 @@ impl<TIM: ValidTim> CountDownTimer<TIM> {
|
||||
#[inline(always)]
|
||||
pub fn enable(&mut self) {
|
||||
self.tim.reg().ctrl.modify(|_, w| w.enable().set_bit());
|
||||
if let Some(irq_cfg) = self.irq_cfg {
|
||||
self.enable_interrupt();
|
||||
if irq_cfg.enable {
|
||||
unmask_irq(irq_cfg.irq);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
@ -720,19 +737,29 @@ impl<TIM: ValidTim> embedded_hal::blocking::delay::DelayMs<u8> for CountDownTime
|
||||
|
||||
// Set up a millisecond timer on TIM0. Please note that you still need to unmask the related IRQ
|
||||
// and provide an IRQ handler yourself
|
||||
pub fn set_up_ms_timer(
|
||||
syscfg: &mut pac::SYSCONFIG,
|
||||
irqsel: &mut pac::IRQSEL,
|
||||
sys_clk: Hertz,
|
||||
tim0: TIM0,
|
||||
irq: pac::Interrupt,
|
||||
) -> CountDownTimer<TIM0> {
|
||||
let mut ms_timer = CountDownTimer::new(syscfg, sys_clk, tim0);
|
||||
ms_timer.listen(timer::Event::TimeOut, syscfg, irqsel, irq);
|
||||
pub fn set_up_ms_timer<TIM: ValidTim>(
|
||||
irq_cfg: IrqCfg,
|
||||
sys_cfg: &mut pac::SYSCONFIG,
|
||||
irq_sel: Option<&mut pac::IRQSEL>,
|
||||
sys_clk: impl Into<Hertz>,
|
||||
tim0: TIM,
|
||||
) -> CountDownTimer<TIM> {
|
||||
let mut ms_timer = CountDownTimer::new(sys_cfg, sys_clk, tim0);
|
||||
ms_timer.listen(timer::Event::TimeOut, irq_cfg, irq_sel, Some(sys_cfg));
|
||||
ms_timer.start(1000.hz());
|
||||
ms_timer
|
||||
}
|
||||
|
||||
pub fn set_up_ms_delay_provider<TIM: ValidTim>(
|
||||
sys_cfg: &mut pac::SYSCONFIG,
|
||||
sys_clk: impl Into<Hertz>,
|
||||
tim: TIM,
|
||||
) -> CountDownTimer<TIM> {
|
||||
let mut provider = CountDownTimer::new(sys_cfg, sys_clk, tim);
|
||||
provider.start(1000.hz());
|
||||
provider
|
||||
}
|
||||
|
||||
/// This function can be called in a specified interrupt handler to increment
|
||||
/// the MS counter
|
||||
pub fn default_ms_irq_handler() {
|
||||
@ -763,6 +790,7 @@ impl Delay {
|
||||
}
|
||||
|
||||
/// This assumes that the user has already set up a MS tick timer in TIM0 as a system tick
|
||||
/// with [`set_up_ms_delay_provider`]
|
||||
impl embedded_hal::blocking::delay::DelayMs<u32> for Delay {
|
||||
fn delay_ms(&mut self, ms: u32) {
|
||||
if self.cd_tim.curr_freq() != 1000.hz() || !self.cd_tim.listening() {
|
||||
|
||||
299
src/uart.rs
299
src/uart.rs
@ -8,19 +8,25 @@ use core::{marker::PhantomData, ops::Deref};
|
||||
use libm::floorf;
|
||||
|
||||
use crate::clock::enable_peripheral_clock;
|
||||
pub use crate::utility::IrqCfg;
|
||||
use crate::{
|
||||
clock,
|
||||
gpio::pins::{
|
||||
AltFunc1, AltFunc2, AltFunc3, Pin, PA16, PA17, PA18, PA19, PA2, PA26, PA27, PA3, PA30,
|
||||
PA31, PA8, PA9, PB18, PB19, PB20, PB21, PB22, PB23, PB6, PB7, PB8, PB9,
|
||||
},
|
||||
pac::{uarta as uart_base, SYSCONFIG, UARTA, UARTB},
|
||||
pac::{uarta as uart_base, IRQSEL, SYSCONFIG, UARTA, UARTB},
|
||||
utility::unmask_irq,
|
||||
prelude::*,
|
||||
time::{Bps, Hertz},
|
||||
};
|
||||
|
||||
use embedded_hal::{blocking, serial};
|
||||
|
||||
//==================================================================================================
|
||||
// Type-Level support
|
||||
//==================================================================================================
|
||||
|
||||
pub trait Pins<UART> {}
|
||||
|
||||
impl Pins<UARTA> for (Pin<PA9, AltFunc2>, Pin<PA8, AltFunc2>) {}
|
||||
@ -38,12 +44,18 @@ impl Pins<UARTB> for (Pin<PB7, AltFunc1>, Pin<PB6, AltFunc1>) {}
|
||||
impl Pins<UARTB> for (Pin<PB19, AltFunc2>, Pin<PB18, AltFunc2>) {}
|
||||
impl Pins<UARTB> for (Pin<PB21, AltFunc1>, Pin<PB20, AltFunc1>) {}
|
||||
|
||||
//==================================================================================================
|
||||
// Regular Definitions
|
||||
//==================================================================================================
|
||||
|
||||
#[derive(Debug)]
|
||||
pub enum Error {
|
||||
Overrun,
|
||||
FramingError,
|
||||
ParityError,
|
||||
BreakCondition,
|
||||
TransferPending,
|
||||
BufferTooShort,
|
||||
}
|
||||
|
||||
#[derive(Debug, PartialEq, Copy, Clone)]
|
||||
@ -160,6 +172,106 @@ impl From<Bps> for Config {
|
||||
}
|
||||
}
|
||||
|
||||
//==================================================================================================
|
||||
// IRQ Definitions
|
||||
//==================================================================================================
|
||||
|
||||
pub struct IrqInfo {
|
||||
rx_len: usize,
|
||||
rx_idx: usize,
|
||||
irq_cfg: IrqCfg,
|
||||
mode: IrqReceptionMode,
|
||||
}
|
||||
|
||||
pub enum IrqResultMask {
|
||||
Complete = 0,
|
||||
Overflow = 1,
|
||||
FramingError = 2,
|
||||
ParityError = 3,
|
||||
Break = 4,
|
||||
Timeout = 5,
|
||||
Addr9 = 6,
|
||||
}
|
||||
pub struct IrqResult {
|
||||
raw_res: u32,
|
||||
pub bytes_read: usize,
|
||||
}
|
||||
|
||||
impl IrqResult {
|
||||
#[inline]
|
||||
pub fn raw_result(&self) -> u32 {
|
||||
self.raw_res
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub(crate) fn clear_result(&mut self) {
|
||||
self.raw_res = 0;
|
||||
}
|
||||
#[inline]
|
||||
pub(crate) fn set_result(&mut self, flag: IrqResultMask) {
|
||||
self.raw_res |= 1 << flag as u32;
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn complete(&self) -> bool {
|
||||
if ((self.raw_res >> IrqResultMask::Complete as u32) & 0x01) == 0x00 {
|
||||
return true;
|
||||
}
|
||||
false
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn error(&self) -> bool {
|
||||
if self.overflow_error() || self.framing_error() || self.parity_error() {
|
||||
return true;
|
||||
}
|
||||
false
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn overflow_error(&self) -> bool {
|
||||
if ((self.raw_res >> IrqResultMask::Overflow as u32) & 0x01) == 0x01 {
|
||||
return true;
|
||||
}
|
||||
false
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn framing_error(&self) -> bool {
|
||||
if ((self.raw_res >> IrqResultMask::FramingError as u32) & 0x01) == 0x01 {
|
||||
return true;
|
||||
}
|
||||
false
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn parity_error(&self) -> bool {
|
||||
if ((self.raw_res >> IrqResultMask::ParityError as u32) & 0x01) == 0x01 {
|
||||
return true;
|
||||
}
|
||||
false
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn timeout(&self) -> bool {
|
||||
if ((self.raw_res >> IrqResultMask::Timeout as u32) & 0x01) == 0x01 {
|
||||
return true;
|
||||
}
|
||||
false
|
||||
}
|
||||
}
|
||||
|
||||
#[derive(Debug, PartialEq)]
|
||||
pub enum IrqReceptionMode {
|
||||
Idle,
|
||||
FixedLen,
|
||||
VarLen,
|
||||
}
|
||||
|
||||
//==================================================================================================
|
||||
// UART implementation
|
||||
//==================================================================================================
|
||||
|
||||
/// Serial abstraction
|
||||
pub struct Uart<UART, PINS> {
|
||||
uart: UART,
|
||||
@ -168,6 +280,11 @@ pub struct Uart<UART, PINS> {
|
||||
rx: Rx<UART>,
|
||||
}
|
||||
|
||||
pub struct UartWithIrq<UART, PINS> {
|
||||
uart_base: Uart<UART, PINS>,
|
||||
irq_info: IrqInfo,
|
||||
}
|
||||
|
||||
/// Serial receiver
|
||||
pub struct Rx<UART> {
|
||||
_usart: PhantomData<UART>,
|
||||
@ -247,6 +364,46 @@ where
|
||||
self
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn enable_rx(&mut self) {
|
||||
self.uart.enable.write(|w| w.rxenable().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn disable_rx(&mut self) {
|
||||
self.uart.enable.write(|w| w.rxenable().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn enable_tx(&mut self) {
|
||||
self.uart.enable.write(|w| w.txenable().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn disable_tx(&mut self) {
|
||||
self.uart.enable.write(|w| w.txenable().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn clear_rx_fifo(&mut self) {
|
||||
self.uart.fifo_clr.write(|w| w.rxfifo().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn clear_tx_fifo(&mut self) {
|
||||
self.uart.fifo_clr.write(|w| w.txfifo().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn clear_rx_status(&mut self) {
|
||||
self.uart.fifo_clr.write(|w| w.rxsts().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn clear_tx_status(&mut self) {
|
||||
self.uart.fifo_clr.write(|w| w.txsts().set_bit());
|
||||
}
|
||||
|
||||
pub fn listen(self, event: Event) -> Self {
|
||||
self.uart.irq_enb.modify(|_, w| match event {
|
||||
Event::RxError => w.irq_rx_status().set_bit(),
|
||||
@ -319,6 +476,146 @@ macro_rules! uart_impl {
|
||||
}
|
||||
}
|
||||
|
||||
impl<PINS> Uart<UARTA, PINS> {
|
||||
pub fn into_uart_with_irq(self, irq_cfg: IrqCfg) -> UartWithIrq<UARTA, PINS> {
|
||||
UartWithIrq {
|
||||
uart_base: self,
|
||||
irq_info: IrqInfo {
|
||||
rx_len: 0,
|
||||
rx_idx: 0,
|
||||
irq_cfg,
|
||||
mode: IrqReceptionMode::Idle,
|
||||
},
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<PINS> UartWithIrq<UARTA, PINS> {
|
||||
pub fn read_fixed_len_using_irq(
|
||||
&mut self,
|
||||
max_len: usize,
|
||||
enb_timeout_irq: bool,
|
||||
irqsel: Option<&mut IRQSEL>,
|
||||
) -> Result<(), Error> {
|
||||
if self.irq_info.mode != IrqReceptionMode::Idle {
|
||||
return Err(Error::TransferPending);
|
||||
}
|
||||
self.irq_info.rx_idx = 0;
|
||||
self.irq_info.rx_len = max_len;
|
||||
self.enable_rx_irq_sources(enb_timeout_irq);
|
||||
if let Some(irqsel) = irqsel {
|
||||
if self.irq_info.irq_cfg.route {
|
||||
irqsel.uart[0].write(|w| unsafe { w.bits(self.irq_info.irq_cfg.irq as u32) });
|
||||
}
|
||||
}
|
||||
if self.irq_info.irq_cfg.enable {
|
||||
unmask_irq(self.irq_info.irq_cfg.irq);
|
||||
}
|
||||
Ok(())
|
||||
}
|
||||
|
||||
#[inline]
|
||||
fn enable_rx_irq_sources(&mut self, timeout: bool) {
|
||||
self.uart_base.uart.irq_enb.modify(|_, w| {
|
||||
if timeout {
|
||||
w.irq_rx_to().set_bit();
|
||||
}
|
||||
w.irq_rx_status().set_bit();
|
||||
w.irq_rx().set_bit()
|
||||
});
|
||||
}
|
||||
|
||||
#[inline]
|
||||
fn disable_rx_irq_sources(&mut self) {
|
||||
self.uart_base.uart.irq_enb.modify(|_, w| {
|
||||
w.irq_rx_to().clear_bit();
|
||||
w.irq_rx_status().clear_bit();
|
||||
w.irq_rx().clear_bit()
|
||||
});
|
||||
}
|
||||
|
||||
pub fn cancel_transfer(&mut self) {
|
||||
// Disable IRQ
|
||||
cortex_m::peripheral::NVIC::mask(self.irq_info.irq_cfg.irq);
|
||||
self.disable_rx_irq_sources();
|
||||
self.uart_base.clear_tx_fifo();
|
||||
self.irq_info.rx_idx = 0;
|
||||
self.irq_info.rx_len = 0;
|
||||
}
|
||||
|
||||
pub fn irq_handler(&mut self, res: &mut IrqResult, buf: &mut [u8]) -> Result<(), Error> {
|
||||
if buf.len() < self.irq_info.rx_len {
|
||||
return Err(Error::BufferTooShort);
|
||||
}
|
||||
|
||||
let mut rx_status = self.uart_base.uart.rxstatus.read();
|
||||
let _tx_status = self.uart_base.uart.txstatus.read();
|
||||
let irq_end = self.uart_base.uart.irq_end.read();
|
||||
|
||||
let enb_status = self.uart_base.uart.enable.read();
|
||||
let rx_enabled = enb_status.rxenable().bit_is_set();
|
||||
let _tx_enabled = enb_status.txenable().bit_is_set();
|
||||
res.clear_result();
|
||||
if irq_end.irq_rx().bit_is_set() && rx_status.rdavl().bit_is_set() {
|
||||
let mut rd_avl = rx_status.rdavl();
|
||||
// While there is data in the FIFO, write it into the reception buffer
|
||||
while self.irq_info.rx_idx < self.irq_info.rx_len && rd_avl.bit_is_set() {
|
||||
buf[self.irq_info.rx_idx] = nb::block!(self.uart_base.read()).unwrap();
|
||||
rd_avl = self.uart_base.uart.rxstatus.read().rdavl();
|
||||
self.irq_info.rx_idx += 1;
|
||||
if self.irq_info.rx_idx == self.irq_info.rx_len {
|
||||
self.disable_rx_irq_sources();
|
||||
res.bytes_read = self.irq_info.rx_len;
|
||||
res.set_result(IrqResultMask::Complete);
|
||||
self.irq_info.rx_idx = 0;
|
||||
self.irq_info.rx_len = 0;
|
||||
return Ok(());
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// RX transfer not complete, check for RX errors
|
||||
if (self.irq_info.rx_idx < self.irq_info.rx_len) && rx_enabled {
|
||||
// Read status register again, might have changed since reading received data
|
||||
rx_status = self.uart_base.uart.rxstatus.read();
|
||||
if rx_status.rxovr().bit_is_set() {
|
||||
res.set_result(IrqResultMask::Overflow);
|
||||
}
|
||||
if rx_status.rxfrm().bit_is_set() {
|
||||
res.set_result(IrqResultMask::FramingError);
|
||||
}
|
||||
if rx_status.rxpar().bit_is_set() {
|
||||
res.set_result(IrqResultMask::ParityError);
|
||||
}
|
||||
if rx_status.rxbrk().bit_is_set() {
|
||||
res.set_result(IrqResultMask::Break);
|
||||
}
|
||||
if rx_status.rxto().bit_is_set() {
|
||||
// A timeout has occured but there might be some leftover data in the FIFO,
|
||||
// so read that data as well
|
||||
while self.irq_info.rx_idx < self.irq_info.rx_len && rx_status.rdavl().bit_is_set()
|
||||
{
|
||||
buf[self.irq_info.rx_idx] = nb::block!(self.uart_base.read()).unwrap();
|
||||
self.irq_info.rx_idx += 1;
|
||||
}
|
||||
res.bytes_read = self.irq_info.rx_idx;
|
||||
res.set_result(IrqResultMask::Timeout);
|
||||
res.set_result(IrqResultMask::Complete);
|
||||
}
|
||||
|
||||
if res.raw_res != 0 {
|
||||
self.disable_rx_irq_sources();
|
||||
}
|
||||
}
|
||||
|
||||
self.uart_base
|
||||
.uart
|
||||
.irq_clr
|
||||
.write(|w| unsafe { w.bits(irq_end.bits()) });
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
|
||||
uart_impl! {
|
||||
UARTA: (uarta, clock::PeripheralClocks::Uart0),
|
||||
UARTB: (uartb, clock::PeripheralClocks::Uart1),
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
//! Some more information about the recommended scrub rates can be found on the
|
||||
//! [Vorago White Paper website](https://www.voragotech.com/resources) in the
|
||||
//! application note AN1212
|
||||
use crate::pac;
|
||||
use va108xx::{IOCONFIG, SYSCONFIG};
|
||||
|
||||
#[derive(PartialEq, Debug)]
|
||||
@ -41,6 +42,26 @@ pub enum PeripheralSelect {
|
||||
Gpio = 24,
|
||||
}
|
||||
|
||||
/// Generic IRQ config which can be used to specify whether the HAL driver will
|
||||
/// use the IRQSEL register to route an interrupt, and whether the IRQ will be unmasked in the
|
||||
/// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might perform
|
||||
/// this steps themselves
|
||||
#[derive(Debug, PartialEq, Clone, Copy)]
|
||||
pub struct IrqCfg {
|
||||
/// Interrupt target vector. Should always be set, might be required for disabling IRQs
|
||||
pub irq: pac::Interrupt,
|
||||
/// Specfiy whether IRQ should be routed to an IRQ vector using the IRQSEL peripheral
|
||||
pub route: bool,
|
||||
/// Specify whether the IRQ is unmasked in the Cortex-M NVIC
|
||||
pub enable: bool,
|
||||
}
|
||||
|
||||
impl IrqCfg {
|
||||
pub fn new(irq: pac::Interrupt, route: bool, enable: bool) -> Self {
|
||||
IrqCfg { irq, route, enable }
|
||||
}
|
||||
}
|
||||
|
||||
/// Enable scrubbing for the ROM
|
||||
///
|
||||
/// Returns [`UtilityError::InvalidCounterResetVal`] if the scrub rate is 0
|
||||
@ -111,3 +132,13 @@ pub fn port_mux(
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// Unmask and enable an IRQ with the given interrupt number
|
||||
///
|
||||
/// ## Safety
|
||||
///
|
||||
/// The unmask function can break mask-based critical sections
|
||||
#[inline]
|
||||
pub (crate) fn unmask_irq(irq: pac::Interrupt) {
|
||||
unsafe { cortex_m::peripheral::NVIC::unmask(irq) };
|
||||
}
|
||||
|
||||
Reference in New Issue
Block a user