HAL update
- SPI: Clear TX and RX FIFO for transfers - Added `port_mux` function to manually select function for pins
This commit is contained in:
parent
3fc8ce519a
commit
fb158caf6e
@ -57,14 +57,17 @@
|
||||
//! operation, the trait functions will return
|
||||
//! [`InvalidPinType`](PinError::InvalidPinType).
|
||||
|
||||
use super::pins::{
|
||||
common_reg_if_functions, FilterType, InterruptEdge, InterruptLevel, Pin, PinError, PinId,
|
||||
PinMode, PinState,
|
||||
use super::{
|
||||
pins::{
|
||||
common_reg_if_functions, FilterType, InterruptEdge, InterruptLevel, Pin, PinError, PinId,
|
||||
PinMode, PinState,
|
||||
},
|
||||
reg::RegisterInterface,
|
||||
};
|
||||
use super::reg::RegisterInterface;
|
||||
use crate::{
|
||||
clock::FilterClkSel,
|
||||
pac::{self, IRQSEL, SYSCONFIG},
|
||||
utility::Funsel,
|
||||
};
|
||||
use embedded_hal::digital::v2::{InputPin, OutputPin, ToggleableOutputPin};
|
||||
use paste::paste;
|
||||
@ -98,13 +101,7 @@ pub enum DynOutput {
|
||||
ReadableOpenDrain,
|
||||
}
|
||||
|
||||
/// Value-level `enum` for alternate peripheral function configurations
|
||||
#[derive(PartialEq, Eq, Clone, Copy)]
|
||||
pub enum DynAlternate {
|
||||
Funsel1,
|
||||
Funsel2,
|
||||
Funsel3,
|
||||
}
|
||||
pub type DynAlternate = Funsel;
|
||||
|
||||
//==================================================================================================
|
||||
// DynPinMode
|
||||
|
@ -60,18 +60,7 @@ impl From<DynPinMode> for ModeFields {
|
||||
}
|
||||
}
|
||||
Alternate(config) => {
|
||||
use dynpins::DynAlternate::*;
|
||||
match config {
|
||||
Funsel1 => {
|
||||
fields.funsel = 1;
|
||||
}
|
||||
Funsel2 => {
|
||||
fields.funsel = 2;
|
||||
}
|
||||
Funsel3 => {
|
||||
fields.funsel = 3;
|
||||
}
|
||||
}
|
||||
fields.funsel = config as u8;
|
||||
}
|
||||
}
|
||||
fields
|
||||
|
13
src/spi.rs
13
src/spi.rs
@ -504,6 +504,16 @@ macro_rules! spi {
|
||||
});
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn clear_tx_fifo(&self) {
|
||||
self.spi.fifo_clr.write(|w| w.txfifo().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn clear_rx_fifo(&self) {
|
||||
self.spi.fifo_clr.write(|w| w.rxfifo().set_bit());
|
||||
}
|
||||
|
||||
#[inline]
|
||||
pub fn perid(&self) -> u32 {
|
||||
self.spi.perid.read().bits()
|
||||
@ -640,6 +650,9 @@ macro_rules! spi {
|
||||
// FIFO has a depth of 16.
|
||||
const FILL_DEPTH: usize = 12;
|
||||
|
||||
self.clear_tx_fifo();
|
||||
self.clear_rx_fifo();
|
||||
|
||||
if self.blockmode {
|
||||
self.spi.ctrl1.modify(|_, w| {
|
||||
w.mtxpause().set_bit()
|
||||
|
@ -3,11 +3,25 @@
|
||||
//! Some more information about the recommended scrub rates can be found on the
|
||||
//! [Vorago White Paper website](https://www.voragotech.com/resources) in the
|
||||
//! application note AN1212
|
||||
use va108xx::SYSCONFIG;
|
||||
use va108xx::{IOCONFIG, SYSCONFIG};
|
||||
|
||||
#[derive(PartialEq, Debug)]
|
||||
pub enum UtilityError {
|
||||
InvalidCounterResetVal,
|
||||
InvalidPin,
|
||||
}
|
||||
|
||||
#[derive(Debug, Eq, Copy, Clone, PartialEq)]
|
||||
pub enum Funsel {
|
||||
Funsel1 = 0b01,
|
||||
Funsel2 = 0b10,
|
||||
Funsel3 = 0b11,
|
||||
}
|
||||
|
||||
#[derive(Debug, Copy, Clone, PartialEq)]
|
||||
pub enum PortSel {
|
||||
PortA,
|
||||
PortB,
|
||||
}
|
||||
|
||||
#[derive(Copy, Clone, PartialEq)]
|
||||
@ -72,3 +86,28 @@ pub fn set_reset_bit(syscfg: &mut SYSCONFIG, periph_sel: PeripheralSelect) {
|
||||
.peripheral_reset
|
||||
.modify(|r, w| unsafe { w.bits(r.bits() | (1 << periph_sel as u8)) });
|
||||
}
|
||||
|
||||
/// Can be used to manually manipulate the function select of port pins
|
||||
pub fn port_mux(
|
||||
ioconfig: &mut IOCONFIG,
|
||||
port: PortSel,
|
||||
pin: u8,
|
||||
funsel: Funsel,
|
||||
) -> Result<(), UtilityError> {
|
||||
match port {
|
||||
PortSel::PortA => {
|
||||
if pin > 31 {
|
||||
return Err(UtilityError::InvalidPin);
|
||||
}
|
||||
ioconfig.porta[pin as usize].modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
|
||||
Ok(())
|
||||
}
|
||||
PortSel::PortB => {
|
||||
if pin > 23 {
|
||||
return Err(UtilityError::InvalidPin);
|
||||
}
|
||||
ioconfig.portb[pin as usize].modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
}
|
||||
|
Reference in New Issue
Block a user