Compare commits
2 Commits
main
...
mueller/so
Author | SHA1 | Date | |
---|---|---|---|
3eb92f8e10 | |||
dc4639b2f0 |
12
src/timer.rs
12
src/timer.rs
|
@ -21,7 +21,7 @@ use crate::{
|
||||||
private::Sealed,
|
private::Sealed,
|
||||||
time::Hertz,
|
time::Hertz,
|
||||||
timer,
|
timer,
|
||||||
utility::unmask_irq,
|
utility::{mask_irq, unmask_irq},
|
||||||
};
|
};
|
||||||
use core::cell::Cell;
|
use core::cell::Cell;
|
||||||
use cortex_m::interrupt::Mutex;
|
use cortex_m::interrupt::Mutex;
|
||||||
|
@ -576,6 +576,12 @@ impl<TIM: ValidTim> CountDownTimer<TIM> {
|
||||||
#[inline(always)]
|
#[inline(always)]
|
||||||
pub fn disable(&mut self) {
|
pub fn disable(&mut self) {
|
||||||
self.tim.reg().ctrl.modify(|_, w| w.enable().clear_bit());
|
self.tim.reg().ctrl.modify(|_, w| w.enable().clear_bit());
|
||||||
|
if let Some(irq_cfg) = self.irq_cfg {
|
||||||
|
self.disable_interrupt();
|
||||||
|
if irq_cfg.enable {
|
||||||
|
mask_irq(irq_cfg.irq);
|
||||||
|
}
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Disable the counter, setting both enable and active bit to 0
|
/// Disable the counter, setting both enable and active bit to 0
|
||||||
|
@ -742,9 +748,9 @@ pub fn set_up_ms_timer<TIM: ValidTim>(
|
||||||
sys_cfg: &mut pac::SYSCONFIG,
|
sys_cfg: &mut pac::SYSCONFIG,
|
||||||
irq_sel: Option<&mut pac::IRQSEL>,
|
irq_sel: Option<&mut pac::IRQSEL>,
|
||||||
sys_clk: impl Into<Hertz>,
|
sys_clk: impl Into<Hertz>,
|
||||||
tim0: TIM,
|
tim: TIM,
|
||||||
) -> CountDownTimer<TIM> {
|
) -> CountDownTimer<TIM> {
|
||||||
let mut ms_timer = CountDownTimer::new(sys_cfg, sys_clk, tim0);
|
let mut ms_timer = CountDownTimer::new(sys_cfg, sys_clk, tim);
|
||||||
ms_timer.listen(timer::Event::TimeOut, irq_cfg, irq_sel, Some(sys_cfg));
|
ms_timer.listen(timer::Event::TimeOut, irq_cfg, irq_sel, Some(sys_cfg));
|
||||||
ms_timer.start(1000.hz());
|
ms_timer.start(1000.hz());
|
||||||
ms_timer
|
ms_timer
|
||||||
|
|
|
@ -280,7 +280,7 @@ impl IrqResult {
|
||||||
#[derive(Debug, PartialEq)]
|
#[derive(Debug, PartialEq)]
|
||||||
enum IrqReceptionMode {
|
enum IrqReceptionMode {
|
||||||
Idle,
|
Idle,
|
||||||
Pending
|
Pending,
|
||||||
}
|
}
|
||||||
|
|
||||||
//==================================================================================================
|
//==================================================================================================
|
||||||
|
|
|
@ -142,3 +142,8 @@ pub fn port_mux(
|
||||||
pub(crate) fn unmask_irq(irq: pac::Interrupt) {
|
pub(crate) fn unmask_irq(irq: pac::Interrupt) {
|
||||||
unsafe { cortex_m::peripheral::NVIC::unmask(irq) };
|
unsafe { cortex_m::peripheral::NVIC::unmask(irq) };
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#[inline]
|
||||||
|
pub(crate) fn mask_irq(irq: pac::Interrupt) {
|
||||||
|
cortex_m::peripheral::NVIC::mask(irq);
|
||||||
|
}
|
||||||
|
|
Loading…
Reference in New Issue
Block a user