66 lines
2.2 KiB
Rust
66 lines
2.2 KiB
Rust
//! # API for clock related functionality
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//!
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//! This also includes functionality to enable the peripheral clocks
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use crate::time::Hertz;
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use crate::utility::PeripheralSelect;
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use cortex_m::interrupt::{self, Mutex};
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use once_cell::unsync::OnceCell;
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use va108xx::SYSCONFIG;
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static SYS_CLOCK: Mutex<OnceCell<Hertz>> = Mutex::new(OnceCell::new());
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pub type PeripheralClocks = PeripheralSelect;
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#[derive(Debug, PartialEq, Eq)]
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pub enum FilterClkSel {
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SysClk = 0,
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Clk1 = 1,
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Clk2 = 2,
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Clk3 = 3,
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Clk4 = 4,
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Clk5 = 5,
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Clk6 = 6,
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Clk7 = 7,
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}
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/// The Vorago in powered by an external clock which might have different frequencies.
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/// The clock can be set here so it can be used by other software components as well.
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/// The clock can be set exactly once
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pub fn set_sys_clock(freq: impl Into<Hertz>) {
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interrupt::free(|cs| {
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SYS_CLOCK.borrow(cs).set(freq.into()).ok();
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})
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}
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/// Returns the configured system clock
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pub fn get_sys_clock() -> Option<Hertz> {
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interrupt::free(|cs| SYS_CLOCK.borrow(cs).get().copied())
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}
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pub fn set_clk_div_register(syscfg: &mut SYSCONFIG, clk_sel: FilterClkSel, div: u32) {
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match clk_sel {
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FilterClkSel::SysClk => (),
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FilterClkSel::Clk1 => syscfg.ioconfig_clkdiv1.write(|w| unsafe { w.bits(div) }),
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FilterClkSel::Clk2 => syscfg.ioconfig_clkdiv2.write(|w| unsafe { w.bits(div) }),
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FilterClkSel::Clk3 => syscfg.ioconfig_clkdiv3.write(|w| unsafe { w.bits(div) }),
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FilterClkSel::Clk4 => syscfg.ioconfig_clkdiv4.write(|w| unsafe { w.bits(div) }),
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FilterClkSel::Clk5 => syscfg.ioconfig_clkdiv5.write(|w| unsafe { w.bits(div) }),
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FilterClkSel::Clk6 => syscfg.ioconfig_clkdiv6.write(|w| unsafe { w.bits(div) }),
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FilterClkSel::Clk7 => syscfg.ioconfig_clkdiv7.write(|w| unsafe { w.bits(div) }),
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}
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}
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#[inline]
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pub fn enable_peripheral_clock(syscfg: &mut SYSCONFIG, clock: PeripheralClocks) {
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syscfg
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.peripheral_clk_enable
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.modify(|r, w| unsafe { w.bits(r.bits() | (1 << clock as u8)) });
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}
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#[inline]
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pub fn disable_peripheral_clock(syscfg: &mut SYSCONFIG, clock: PeripheralClocks) {
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syscfg
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.peripheral_clk_enable
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.modify(|r, w| unsafe { w.bits(r.bits() & !(1 << clock as u8)) });
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}
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