370 lines
12 KiB
Rust
370 lines
12 KiB
Rust
use super::dynpins::{self, DynGroup, DynPinId, DynPinMode};
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use super::pins::{FilterClkSel, FilterType, PinError, PinState};
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use va108xx::{ioconfig, porta, IOCONFIG, PORTA, PORTB};
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/// Type definition to avoid confusion: These register blocks are identical
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type PortRegisterBlock = porta::RegisterBlock;
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//==================================================================================================
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// ModeFields
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//==================================================================================================
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/// Collect all fields needed to set the [`PinMode`](super::PinMode)
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#[derive(Default)]
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struct ModeFields {
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dir: bool,
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opendrn: bool,
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pull_en: bool,
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/// true for pullup, false for pulldown
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pull_dir: bool,
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funsel: u8,
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enb_input: bool,
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}
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impl From<DynPinMode> for ModeFields {
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#[inline]
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fn from(mode: DynPinMode) -> Self {
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let mut fields = Self::default();
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use DynPinMode::*;
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match mode {
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Input(config) => {
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use dynpins::DynInput::*;
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fields.dir = false;
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match config {
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Floating => {
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fields.pull_en = false;
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}
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PullUp => {
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fields.pull_en = true;
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fields.pull_dir = true;
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}
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PullDown => {
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fields.pull_en = true;
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fields.pull_dir = false;
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}
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}
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}
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Output(config) => {
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use dynpins::DynOutput::*;
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fields.dir = true;
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match config {
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PushPull => {
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fields.opendrn = false;
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}
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OpenDrain => {
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fields.opendrn = true;
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}
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ReadableOpenDrain => {
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fields.enb_input = true;
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fields.opendrn = true;
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}
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ReadablePushPull => {
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fields.enb_input = true;
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fields.opendrn = false;
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}
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}
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}
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Alternate(config) => {
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use dynpins::DynAlternate::*;
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match config {
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Funsel1 => {
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fields.funsel = 1;
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}
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Funsel2 => {
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fields.funsel = 2;
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}
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Funsel3 => {
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fields.funsel = 3;
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}
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}
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}
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}
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fields
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}
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}
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//==================================================================================================
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// Register Interface
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//==================================================================================================
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pub type IocfgPort = ioconfig::PORTA;
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#[repr(C)]
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pub(super) struct IOCFG_PORT_GROUP {
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port: [IocfgPort; 32],
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}
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/// Provide a safe register interface for pin objects
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///
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/// [`PORTA`] and [`PORTB`], like every PAC `struct`, is [`Send`] but not [`Sync`], because it
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/// points to a `RegisterBlock` of `VolatileCell`s. Unfortunately, such an
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/// interface is quite restrictive. Instead, it would be ideal if we could split
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/// the [`PORT`] into independent pins that are both [`Send`] and [`Sync`].
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///
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/// [`PORT`] is a single, zero-sized marker `struct` that provides access to
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/// every [`PORT`] register. Instead, we would like to create zero-sized marker
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/// `struct`s for every pin, where each pin is only allowed to control its own
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/// registers. Furthermore, each pin `struct` should be a singleton, so that
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/// exclusive access to the `struct` also guarantees exclusive access to the
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/// corresponding registers. Finally, the pin `struct`s should not have any
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/// interior mutability. Together, these requirements would allow the pin
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/// `struct`s to be both [`Send`] and [`Sync`].
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///
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/// This trait creates a safe API for accomplishing these goals. Implementers
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/// supply a pin ID through the [`id`] function. The remaining functions provide
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/// a safe API for accessing the registers associated with that pin ID. Any
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/// modification of the registers requires `&mut self`, which destroys interior
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/// mutability.
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///
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/// # Safety
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///
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/// Users should only implement the [`id`] function. No default function
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/// implementations should be overridden. The implementing type must also have
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/// "control" over the corresponding pin ID, i.e. it must guarantee that a each
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/// pin ID is a singleton.
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///
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/// [`id`]: Self::id
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pub(super) unsafe trait RegisterInterface {
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/// Provide a [`DynPinId`] identifying the set of registers controlled by
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/// this type.
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fn id(&self) -> DynPinId;
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const PORTA: *const PortRegisterBlock = PORTA::ptr();
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const PORTB: *const PortRegisterBlock = PORTB::ptr();
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const PORT_CFG: *const IOCFG_PORT_GROUP = IOCONFIG::ptr() as *const _;
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/// Change the pin mode
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#[inline]
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fn change_mode(&mut self, mode: DynPinMode) {
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let ModeFields {
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dir,
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funsel,
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opendrn,
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pull_dir,
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pull_en,
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enb_input,
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} = mode.into();
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let (portreg, iocfg) = (self.port_reg(), self.iocfg_port());
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iocfg.port[self.id().num as usize].write(|w| {
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w.opendrn().bit(opendrn);
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w.pen().bit(pull_en);
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w.plevel().bit(pull_dir);
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w.iewo().bit(enb_input);
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unsafe { w.funsel().bits(funsel) }
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});
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let mask = self.mask_32();
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unsafe {
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if dir {
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portreg.dir().modify(|r, w| w.bits(r.bits() | mask));
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} else {
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portreg.dir().modify(|r, w| w.bits(r.bits() & !mask));
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}
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}
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}
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#[inline]
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fn port_reg(&self) -> &PortRegisterBlock {
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match self.id().group {
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DynGroup::A => unsafe { &(*Self::PORTA) },
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DynGroup::B => unsafe { &(*Self::PORTB) },
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}
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}
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fn iocfg_port(&self) -> &IOCFG_PORT_GROUP {
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match self.id().group {
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DynGroup::A => unsafe { &*Self::PORT_CFG },
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DynGroup::B => unsafe { &*Self::PORT_CFG.add(1) },
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}
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}
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#[inline]
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fn mask_32(&self) -> u32 {
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1 << self.id().num
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}
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#[inline]
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fn enable_input_for_output(&self, enable: bool) {
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let iocfg = self.iocfg_port();
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iocfg.port[self.id().num as usize].modify(|_, w| w.iewo().bit(enable))
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}
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/// Set the direction of a pin
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#[inline]
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fn set_dir(&mut self, bit: bool) {
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let portreg = self.port_reg();
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let mask = self.mask_32();
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// Safety: Only the bit for this Pin ID is modified
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unsafe {
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if bit {
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portreg.dir().modify(|r, w| w.bits(r.bits() | mask));
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} else {
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portreg.dir().modify(|r, w| w.bits(r.bits() & !mask));
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}
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}
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}
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fn get_perid(&self) -> u32 {
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let portreg = self.port_reg();
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portreg.perid.read().bits()
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}
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/// Read the logic level of an output pin
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fn read_pin(&self) -> bool {
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let portreg = self.port_reg();
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((portreg.datainraw().read().bits() >> self.id().num) & 0x01) == 1
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}
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// Get DATAMASK bit for this particular pin
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#[inline(always)]
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fn datamask(&self) -> bool {
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let portreg = self.port_reg();
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(portreg.datamask().read().bits() >> self.id().num) == 1
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}
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/// Read a pin but use the masked version but check whether the datamask for the pin is
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/// cleared as well
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fn read_pin_masked(&self) -> Result<bool, PinError> {
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if !self.datamask() {
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Err(PinError::IsMasked)
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} else {
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let portreg = self.port_reg();
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Ok(((portreg.datain().read().bits() >> self.id().num) & 0x01) == 1)
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}
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}
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/// Write the logic level of an output pin
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#[inline]
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fn write_pin(&mut self, bit: bool) {
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let portreg = self.port_reg();
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let mask = self.mask_32();
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// Safety: SETOUT is a "mask" register, and we only write the bit for
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// this pin ID
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unsafe {
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if bit {
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portreg.setout().write(|w| w.bits(mask));
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} else {
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portreg.clrout().write(|w| w.bits(mask));
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}
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}
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}
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/// Write the logic level of an output pin but check whether the datamask for the pin is
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/// cleared as well
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#[inline]
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fn write_pin_masked(&mut self, bit: bool) -> Result<(), PinError> {
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if !self.datamask() {
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Err(PinError::IsMasked)
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} else {
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let portreg = self.port_reg();
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let mask = self.mask_32();
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// Safety: SETOUT is a "mask" register, and we only write the bit for
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// this pin ID
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unsafe {
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if bit {
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portreg.setout().write(|w| w.bits(mask));
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} else {
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portreg.clrout().write(|w| w.bits(mask));
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}
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Ok(())
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}
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}
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}
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/// Toggle the logic level of an output pin
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#[inline]
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fn toggle(&mut self) {
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let portreg = self.port_reg();
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let mask = self.mask_32();
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// Safety: TOGOUT is a "mask" register, and we only write the bit for
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// this pin ID
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unsafe { portreg.togout().write(|w| w.bits(mask)) };
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}
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/// Only useful for input pins
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#[inline]
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fn filter_type(&self, filter: FilterType, clksel: FilterClkSel) {
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let iocfg = self.iocfg_port();
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iocfg.port[self.id().num as usize].modify(|_, w| {
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// Safety: Only write to register for this Pin ID
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unsafe {
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w.flttype().bits(filter as u8);
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w.fltclk().bits(clksel as u8)
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}
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});
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}
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/// Set DATAMASK bit for this particular pin. 1 is the default
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/// state of the bit and allows access of the corresponding bit
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#[inline(always)]
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fn set_datamask(&self) {
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let portreg = self.port_reg();
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unsafe {
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portreg
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.datamask()
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.modify(|r, w| w.bits(r.bits() | self.mask_32()))
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}
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}
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/// Clear DATAMASK bit for this particular pin. This prevents access
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/// of the corresponding bit for output and input operations
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#[inline(always)]
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fn clear_datamask(&self) {
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let portreg = self.port_reg();
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unsafe {
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portreg
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.datamask()
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.modify(|r, w| w.bits(r.bits() & !self.mask_32()))
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}
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}
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/// Only useful for output pins
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/// See p.52 of the programmers guide for more information.
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/// When configured for pulse mode, a given pin will set the non-default state for exactly
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/// one clock cycle before returning to the configured default state
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fn pulse_mode(&self, enable: bool, default_state: PinState) {
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let portreg = self.port_reg();
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unsafe {
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if enable {
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portreg
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.pulse()
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.modify(|r, w| w.bits(r.bits() | self.mask_32()));
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} else {
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portreg
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.pulse()
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.modify(|r, w| w.bits(r.bits() & !self.mask_32()));
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}
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if default_state == PinState::Low {
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portreg
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.pulsebase()
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.modify(|r, w| w.bits(r.bits() & !self.mask_32()));
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} else {
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portreg
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.pulsebase()
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.modify(|r, w| w.bits(r.bits() | self.mask_32()));
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}
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}
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}
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/// Only useful for output pins
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fn delay(&self, delay_1: bool, delay_2: bool) {
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let portreg = self.port_reg();
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unsafe {
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if delay_1 {
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portreg
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.delay1()
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.modify(|r, w| w.bits(r.bits() | self.mask_32()));
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} else {
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portreg
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.delay1()
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.modify(|r, w| w.bits(r.bits() & !self.mask_32()));
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}
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if delay_2 {
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portreg
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.delay2()
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.modify(|r, w| w.bits(r.bits() | self.mask_32()));
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} else {
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portreg
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.delay2()
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.modify(|r, w| w.bits(r.bits() & !self.mask_32()));
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}
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}
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}
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}
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