doc fixes
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@ -221,7 +221,7 @@ async fn output_task(
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}
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GpioCmdType::RisingEdge => {
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defmt::info!("{}: Rising edge", ctx);
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if !out.is_set_high() {
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if !out.is_set_low() {
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out.set_low();
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}
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out.set_high();
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@ -1,7 +1,7 @@
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//! API for the SPI peripheral.
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//!
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//! The main abstraction provided by this module are the [Spi] and the [SpiBase] structure.
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//! These provide the [embedded_hal::spi] traits, but also offer a low level interface
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//! The main abstraction provided by this module is the [Spi] an structure.
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//! It provides the [embedded_hal::spi] traits, but also offer a low level interface
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//! via the [SpiLowLevel] trait.
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//!
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//! ## Examples
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@ -290,7 +290,7 @@ pub type TimRegBlock = tim0::RegisterBlock;
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///
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/// # Safety
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///
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/// Users should only implement the [Self::tim_id] function. No default function
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/// Users should only implement the [Self::raw_id] function. No default function
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/// implementations should be overridden. The implementing type must also have
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/// "control" over the corresponding pin ID, i.e. it must guarantee that a each
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/// pin ID is a singleton.
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@ -1,6 +1,6 @@
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//! # API for the UART peripheral
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//!
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//! The core of this API are the [Uart], [UartBase], [Rx] and [Tx] structures.
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//! The core of this API are the [Uart], [Rx] and [Tx] structures.
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//! The RX structure also has a dedicated [RxWithInterrupt] variant which allows reading the receiver
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//! using interrupts.
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//!
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@ -510,7 +510,7 @@ pub struct UartIdMissmatchError;
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// UART implementation
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//==================================================================================================
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/// Type erased variant of a UART. Can be created with the [`Uart::downgrade`] function.
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/// UART driver structure.
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pub struct Uart {
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tx: Tx,
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rx: Rx,
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@ -793,7 +793,7 @@ pub fn disable_rx_interrupts(uart: &uart_base::RegisterBlock) {
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/// Serial receiver.
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///
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/// Can be created by using the [Uart::split] or [UartBase::split] API.
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/// Can be created by using the [Uart::split] API.
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pub struct Rx(UartId);
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impl Rx {
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@ -963,7 +963,7 @@ pub fn disable_tx_interrupts(uart: &uart_base::RegisterBlock) {
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/// Serial transmitter
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///
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/// Can be created by using the [Uart::split] or [UartBase::split] API.
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/// Can be created by using the [Uart::split] API.
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pub struct Tx(UartId);
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impl Tx {
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@ -1,6 +1,7 @@
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[package]
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name = "vorago-shared-periphs"
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version = "0.1.0"
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description = "Peripheral drivers shared between Vorago families"
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edition = "2024"
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[dependencies]
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@ -1,6 +1,6 @@
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//! # Async GPIO functionality for the Vorago GPIO peripherals.
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//!
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//! This module provides the [InputPinAsync] and [InputDynPinAsync] which both implement
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//! This module provides the [InputPinAsync] which implements
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//! the [embedded_hal_async::digital::Wait] trait. These types allow for asynchronous waiting
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//! on GPIO pins. Please note that this module does not specify/declare the interrupt handlers
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//! which must be provided for async support to work. However, it provides the
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@ -75,7 +75,7 @@ fn on_interrupt_for_port(
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/// Input pin future which implements the [Future] trait.
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///
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/// Generally, you want to use the [InputPinAsync] or [InputDynPinAsync] types instead of this
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/// Generally, you want to use the [InputPinAsync] types instead of this
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/// which also implements the [embedded_hal_async::digital::Wait] trait. However, access to this
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/// struture is granted to allow writing custom async structures.
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pub struct InputPinFuture {
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@ -143,7 +143,7 @@ pub struct InputPinAsync {
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}
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impl InputPinAsync {
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/// Create a new asynchronous input pin from a [DynPin]. The interrupt ID to be used must be
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/// Create a new asynchronous input pin from an [Input] pin. The interrupt ID to be used must be
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/// passed as well and is used to route and enable the interrupt.
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///
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/// Please note that the interrupt handler itself must be provided by the user and the
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