doc fixes

This commit is contained in:
Robin Müller 2025-04-16 14:44:32 +02:00
parent 121b467fb9
commit 5c1f05fb32
Signed by: muellerr
GPG Key ID: A649FB78196E3849
7 changed files with 12 additions and 11 deletions

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@ -221,7 +221,7 @@ async fn output_task(
}
GpioCmdType::RisingEdge => {
defmt::info!("{}: Rising edge", ctx);
if !out.is_set_high() {
if !out.is_set_low() {
out.set_low();
}
out.set_high();

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@ -1,7 +1,7 @@
//! API for the SPI peripheral.
//!
//! The main abstraction provided by this module are the [Spi] and the [SpiBase] structure.
//! These provide the [embedded_hal::spi] traits, but also offer a low level interface
//! The main abstraction provided by this module is the [Spi] an structure.
//! It provides the [embedded_hal::spi] traits, but also offer a low level interface
//! via the [SpiLowLevel] trait.
//!
//! ## Examples

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@ -290,7 +290,7 @@ pub type TimRegBlock = tim0::RegisterBlock;
///
/// # Safety
///
/// Users should only implement the [Self::tim_id] function. No default function
/// Users should only implement the [Self::raw_id] function. No default function
/// implementations should be overridden. The implementing type must also have
/// "control" over the corresponding pin ID, i.e. it must guarantee that a each
/// pin ID is a singleton.

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@ -1,6 +1,6 @@
//! # API for the UART peripheral
//!
//! The core of this API are the [Uart], [UartBase], [Rx] and [Tx] structures.
//! The core of this API are the [Uart], [Rx] and [Tx] structures.
//! The RX structure also has a dedicated [RxWithInterrupt] variant which allows reading the receiver
//! using interrupts.
//!
@ -510,7 +510,7 @@ pub struct UartIdMissmatchError;
// UART implementation
//==================================================================================================
/// Type erased variant of a UART. Can be created with the [`Uart::downgrade`] function.
/// UART driver structure.
pub struct Uart {
tx: Tx,
rx: Rx,
@ -793,7 +793,7 @@ pub fn disable_rx_interrupts(uart: &uart_base::RegisterBlock) {
/// Serial receiver.
///
/// Can be created by using the [Uart::split] or [UartBase::split] API.
/// Can be created by using the [Uart::split] API.
pub struct Rx(UartId);
impl Rx {
@ -963,7 +963,7 @@ pub fn disable_tx_interrupts(uart: &uart_base::RegisterBlock) {
/// Serial transmitter
///
/// Can be created by using the [Uart::split] or [UartBase::split] API.
/// Can be created by using the [Uart::split] API.
pub struct Tx(UartId);
impl Tx {

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@ -1,6 +1,7 @@
[package]
name = "vorago-shared-periphs"
version = "0.1.0"
description = "Peripheral drivers shared between Vorago families"
edition = "2024"
[dependencies]

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@ -1,6 +1,6 @@
//! # Async GPIO functionality for the Vorago GPIO peripherals.
//!
//! This module provides the [InputPinAsync] and [InputDynPinAsync] which both implement
//! This module provides the [InputPinAsync] which implements
//! the [embedded_hal_async::digital::Wait] trait. These types allow for asynchronous waiting
//! on GPIO pins. Please note that this module does not specify/declare the interrupt handlers
//! which must be provided for async support to work. However, it provides the
@ -75,7 +75,7 @@ fn on_interrupt_for_port(
/// Input pin future which implements the [Future] trait.
///
/// Generally, you want to use the [InputPinAsync] or [InputDynPinAsync] types instead of this
/// Generally, you want to use the [InputPinAsync] types instead of this
/// which also implements the [embedded_hal_async::digital::Wait] trait. However, access to this
/// struture is granted to allow writing custom async structures.
pub struct InputPinFuture {
@ -143,7 +143,7 @@ pub struct InputPinAsync {
}
impl InputPinAsync {
/// Create a new asynchronous input pin from a [DynPin]. The interrupt ID to be used must be
/// Create a new asynchronous input pin from an [Input] pin. The interrupt ID to be used must be
/// passed as well and is used to route and enable the interrupt.
///
/// Please note that the interrupt handler itself must be provided by the user and the