simplfied UART error handling
This commit is contained in:
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c693530ab7
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@ -8,6 +8,16 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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## [unreleased]
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## [v0.11.0] 2025-03-07
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## Changed
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- Bugfix for I2C `TimingCfg::reg`
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- Simplified UART error handling. All APIs are now infallible because writing to a FIFO or
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reading from a FIFO never fails. Users can either poll errors using `Rx::poll_errors` or
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`Uart::poll_rx_errors` / `UartBase::poll_rx_errors`, or detect errors using the provided
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interrupt handlers.
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## [v0.10.0] 2025-02-17
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## Added
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@ -104,14 +114,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Updated `embedded-hal` to v1
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- Added optional `defmt` v0.3 feature and support.
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## [v0.5.2] 2024-06-16
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## v0.5.2 2024-06-16
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## Fixed
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- Replaced usage to `ptr::write_volatile` in UART module which is denied on more recent Rust
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compilers.
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## [v0.5.1]
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## v0.5.1
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### Changes
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@ -120,7 +130,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- `once_cell` to 1.12.0
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- Other dependencies: Only revision has changed
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## [v0.5.0]
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## v0.5.0
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### Added
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@ -133,14 +143,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Bugfix in UART code where RX and TX could not be enabled or disabled independently
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## [v0.4.3]
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## v0.4.3
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- Various smaller fixes for READMEs, update of links in documentation
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- Simplified CI for github, do not use `cross`
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- New `blinky-pac` example
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- Use HAL delay in `blinky` example
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## [v0.4.2]
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## v0.4.2
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### Added
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@ -150,24 +160,24 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Clear TX and RX FIFO in SPI transfer function
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## [v0.4.1]
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## v0.4.1
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### Fixed
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- Initial blockmode setting was not set in SPI constructor
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## [v0.4.0]
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## v0.4.0
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### Changed
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- Replaced `Hertz` by `impl Into<Hertz>` completely and removed
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`+ Copy` where not necessary
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## [v0.3.1]
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## v0.3.1
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- Updated all links to point to new repository
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## [v0.3.0]
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## v0.3.0
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### Added
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@ -179,7 +189,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Primary repository now hosted on IRS external git: https://egit.irs.uni-stuttgart.de/rust/va108xx-hal
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- Relicensed as Apache-2.0
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## [0.2.3]
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## v0.2.3
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### Added
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@ -191,7 +201,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Improved Timer API. It is now possible to simply use `new` on `CountDownTimer`
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## [0.2.2]
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## v0.2.2
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### Added
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@ -203,7 +213,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- API which expects values in Hertz now uses `impl Into<Hertz>` as input parameter
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## [0.2.1]
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## v0.2.1
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### Added
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@ -217,7 +227,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Moved the `FilterClkSel` struct to the `clock` module, re-exporting in `gpio`
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- Clearing output state at initialization of Output pins
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## [0.2.0]
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## v0.2.0
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### Changed
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@ -232,7 +242,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Some bugfixes for GPIO implementation
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- Rust edition updated to 2021
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## [0.1.0]
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## v0.1.0
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### Added
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@ -241,3 +251,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- RTT example application
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- Added basic test binary in form of an example
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- README with basic instructions how to set up own binary crate
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[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...HEAD
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[v0.11.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.10.0...va108xx-hal-v0.11.0
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[v0.10.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.9.0...va108xx-hal-v0.10.0
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[v0.9.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.8.0...va108xx-hal-v0.9.0
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[v0.8.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.7.0...va108xx-hal-v0.8.0
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[v0.7.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.6.0...va108xx-hal-v0.7.0
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[v0.6.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/tag/va108xx-hal-v0.6.0
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@ -198,13 +198,13 @@ impl TimingCfg {
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}
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pub fn reg(&self) -> u32 {
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(self.tbuf as u32) << 28
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| (self.thd_sta as u32) << 24
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| (self.tsu_sta as u32) << 20
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| (self.tsu_sto as u32) << 16
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| (self.tlow as u32) << 12
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| (self.thigh as u32) << 8
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| (self.tf as u32) << 4
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((self.tbuf as u32) << 28)
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| ((self.thd_sta as u32) << 24)
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| ((self.tsu_sta as u32) << 20)
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| ((self.tsu_sto as u32) << 16)
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| ((self.tlow as u32) << 12)
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| ((self.thigh as u32) << 8)
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| ((self.tf as u32) << 4)
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| (self.tr as u32)
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}
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}
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@ -376,7 +376,7 @@ impl<I2c: Instance> I2cBase<I2c> {
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if let Some(max_words) = max_words {
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self.i2c
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.s0_maxwords()
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.write(|w| unsafe { w.bits(1 << 31 | max_words as u32) });
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.write(|w| unsafe { w.bits((1 << 31) | max_words as u32) });
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}
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let (addr, addr_mode_mask) = Self::unwrap_addr(sl_cfg.addr);
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// The first bit is the read/write value. Normally, both read and write are matched
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@ -437,7 +437,7 @@ impl<I2c: Instance> I2cBase<I2c> {
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let clk_div = self.calc_clk_div(speed_mode)?;
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self.i2c
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.clkscale()
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.write(|w| unsafe { w.bits((speed_mode as u32) << 31 | clk_div as u32) });
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.write(|w| unsafe { w.bits(((speed_mode as u32) << 31) | clk_div as u32) });
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Ok(())
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}
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@ -64,55 +64,6 @@ pub struct NoInterruptIdWasSet;
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#[error("transer is pending")]
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pub struct TransferPendingError;
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#[derive(Debug, PartialEq, Eq, thiserror::Error)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum RxError {
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#[error("overrun error")]
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Overrun,
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#[error("framing error")]
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Framing,
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#[error("parity error")]
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Parity,
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}
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#[derive(Debug, PartialEq, Eq, thiserror::Error)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Error {
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#[error("rx error: {0}")]
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Rx(#[from] RxError),
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#[error("break condition")]
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BreakCondition,
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}
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impl embedded_io::Error for Error {
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fn kind(&self) -> embedded_io::ErrorKind {
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embedded_io::ErrorKind::Other
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}
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}
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impl embedded_io::Error for RxError {
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fn kind(&self) -> embedded_io::ErrorKind {
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embedded_io::ErrorKind::Other
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}
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}
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impl embedded_hal_nb::serial::Error for RxError {
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fn kind(&self) -> embedded_hal_nb::serial::ErrorKind {
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match self {
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RxError::Overrun => embedded_hal_nb::serial::ErrorKind::Overrun,
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RxError::Framing => embedded_hal_nb::serial::ErrorKind::FrameFormat,
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RxError::Parity => embedded_hal_nb::serial::ErrorKind::Parity,
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}
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}
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}
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impl embedded_hal_nb::serial::Error for Error {
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fn kind(&self) -> embedded_hal_nb::serial::ErrorKind {
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match self {
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Error::Rx(rx_error) => embedded_hal_nb::serial::Error::kind(rx_error),
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Error::BreakCondition => embedded_hal_nb::serial::ErrorKind::Other,
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}
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}
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}
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#[derive(Debug, PartialEq, Eq, Copy, Clone)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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pub enum Event {
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@ -363,7 +314,7 @@ impl UartErrors {
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impl UartErrors {
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#[inline(always)]
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pub fn error(&self) -> bool {
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self.overflow || self.framing || self.parity
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self.overflow || self.framing || self.parity || self.other
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}
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}
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@ -585,22 +536,27 @@ impl<Uart: Instance> UartBase<Uart> {
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self.uart
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}
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/// Poll receiver errors.
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pub fn poll_rx_errors(&self) -> Option<UartErrors> {
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self.rx.poll_errors()
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}
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pub fn split(self) -> (Tx<Uart>, Rx<Uart>) {
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(self.tx, self.rx)
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}
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}
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impl<UartInstance> embedded_io::ErrorType for UartBase<UartInstance> {
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type Error = Error;
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type Error = Infallible;
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}
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impl<UartInstance> embedded_hal_nb::serial::ErrorType for UartBase<UartInstance> {
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type Error = Error;
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type Error = Infallible;
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}
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impl<Uart: Instance> embedded_hal_nb::serial::Read<u8> for UartBase<Uart> {
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fn read(&mut self) -> nb::Result<u8, Self::Error> {
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self.rx.read().map_err(|e| e.map(Error::Rx))
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self.rx.read()
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}
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}
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@ -711,6 +667,11 @@ where
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self
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}
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/// Poll receiver errors.
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pub fn poll_rx_errors(&self) -> Option<UartErrors> {
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self.inner.poll_rx_errors()
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}
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#[inline]
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pub fn enable_rx(&mut self) {
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self.inner.enable_rx();
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@ -825,6 +786,23 @@ impl<Uart: Instance> Rx<Uart> {
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&self.0
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}
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pub fn poll_errors(&self) -> Option<UartErrors> {
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let mut errors = UartErrors::default();
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let uart = unsafe { &(*Uart::ptr()) };
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let status_reader = uart.rxstatus().read();
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if status_reader.rxovr().bit_is_set() {
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errors.overflow = true;
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} else if status_reader.rxfrm().bit_is_set() {
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errors.framing = true;
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} else if status_reader.rxpar().bit_is_set() {
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errors.parity = true;
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} else {
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return None;
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};
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Some(errors)
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}
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#[inline]
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pub fn clear_fifo(&self) {
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self.0.fifo_clr().write(|w| w.rxfifo().set_bit());
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@ -887,34 +865,15 @@ impl<Uart: Instance> Rx<Uart> {
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}
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impl<Uart> embedded_io::ErrorType for Rx<Uart> {
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type Error = RxError;
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type Error = Infallible;
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}
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impl<Uart> embedded_hal_nb::serial::ErrorType for Rx<Uart> {
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type Error = RxError;
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type Error = Infallible;
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}
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impl<Uart: Instance> embedded_hal_nb::serial::Read<u8> for Rx<Uart> {
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fn read(&mut self) -> nb::Result<u8, Self::Error> {
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let uart = unsafe { &(*Uart::ptr()) };
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let status_reader = uart.rxstatus().read();
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let err = if status_reader.rxovr().bit_is_set() {
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Some(RxError::Overrun)
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} else if status_reader.rxfrm().bit_is_set() {
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Some(RxError::Framing)
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} else if status_reader.rxpar().bit_is_set() {
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Some(RxError::Parity)
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} else {
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None
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};
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if let Some(err) = err {
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// The status code is always related to the next bit for the framing
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// and parity status bits. We have to read the DATA register
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// so that the next status reflects the next DATA word
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// For overrun error, we read as well to clear the peripheral
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self.read_fifo_unchecked();
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return Err(err.into());
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}
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self.read_fifo().map(|val| (val & 0xff) as u8).map_err(|e| {
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if let nb::Error::Other(_) = e {
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unreachable!()
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@ -926,16 +885,18 @@ impl<Uart: Instance> embedded_hal_nb::serial::Read<u8> for Rx<Uart> {
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impl<Uart: Instance> embedded_io::Read for Rx<Uart> {
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fn read(&mut self, buf: &mut [u8]) -> Result<usize, Self::Error> {
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if buf.is_empty() {
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return Ok(0);
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}
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let mut read = 0;
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for byte in buf.iter_mut() {
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let w = nb::block!(<Self as embedded_hal_nb::serial::Read<u8>>::read(self))?;
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*byte = w;
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match <Self as embedded_hal_nb::serial::Read<u8>>::read(self) {
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Ok(w) => {
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*byte = w;
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read += 1;
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}
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Err(nb::Error::WouldBlock) => break,
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}
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}
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Ok(buf.len())
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Ok(read)
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}
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}
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@ -1090,14 +1051,12 @@ impl<Uart: Instance> embedded_hal_nb::serial::Write<u8> for Tx<Uart> {
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impl<Uart: Instance> embedded_io::Write for Tx<Uart> {
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fn write(&mut self, buf: &[u8]) -> Result<usize, Self::Error> {
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if buf.is_empty() {
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return Ok(0);
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}
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let mut written = 0;
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for byte in buf.iter() {
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nb::block!(<Self as embedded_hal_nb::serial::Write<u8>>::write(
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self, *byte
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))?;
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match <Self as embedded_hal_nb::serial::Write<u8>>::write(self, *byte) {
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Ok(_) => written += 1,
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Err(nb::Error::WouldBlock) => return Ok(written),
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}
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}
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Ok(buf.len())
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@ -1218,15 +1177,10 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
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// Timeout, empty the FIFO completely.
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if irq_end.irq_rx_to().bit_is_set() {
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loop {
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// While there is data in the FIFO, write it into the reception buffer
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let read_result = self.0.read();
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if let Some(byte) = self.read_handler(&mut result.errors, &read_result) {
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buf[result.bytes_read] = byte;
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result.bytes_read += 1;
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} else {
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break;
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}
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// While there is data in the FIFO, write it into the reception buffer
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while let Ok(byte) = self.0.read_fifo() {
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buf[result.bytes_read] = byte as u8;
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result.bytes_read += 1;
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}
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}
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@ -1303,12 +1257,13 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
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if context.rx_idx == context.max_len {
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break;
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}
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let read_result = self.0.read();
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if let Some(byte) = self.read_handler(&mut result.errors, &read_result) {
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buf[context.rx_idx] = byte;
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context.rx_idx += 1;
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} else {
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break;
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// While there is data in the FIFO, write it into the reception buffer
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match self.0.read() {
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Ok(byte) => {
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buf[result.bytes_read] = byte;
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result.bytes_read += 1;
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}
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Err(_) => break,
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}
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}
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self.irq_completion_handler_max_size_timeout(&mut result, context);
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@ -1327,29 +1282,6 @@ impl<Uart: Instance> RxWithInterrupt<Uart> {
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Ok(result)
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}
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fn read_handler(
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&self,
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errors: &mut Option<UartErrors>,
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read_res: &nb::Result<u8, RxError>,
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) -> Option<u8> {
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match read_res {
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Ok(byte) => Some(*byte),
|
||||
Err(nb::Error::WouldBlock) => None,
|
||||
Err(nb::Error::Other(e)) => {
|
||||
// Ensure `errors` is Some(IrqUartError), initializing if it's None
|
||||
let err = errors.get_or_insert(UartErrors::default());
|
||||
|
||||
// Now we can safely modify fields inside `err`
|
||||
match e {
|
||||
RxError::Overrun => err.overflow = true,
|
||||
RxError::Framing => err.framing = true,
|
||||
RxError::Parity => err.parity = true,
|
||||
}
|
||||
None
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fn check_for_errors(&self, errors: &mut Option<UartErrors>) {
|
||||
let rx_status = self.uart().rxstatus().read();
|
||||
|
||||
|
||||
@ -26,7 +26,7 @@ use embedded_io::ErrorType;
|
||||
use portable_atomic::AtomicBool;
|
||||
use va108xx::uarta as uart_base;
|
||||
|
||||
use super::{Bank, Instance, Rx, RxError, UartErrors};
|
||||
use super::{Bank, Instance, Rx, UartErrors};
|
||||
|
||||
static UART_RX_WAKERS: [AtomicWaker; 2] = [const { AtomicWaker::new() }; 2];
|
||||
static RX_READ_ACTIVE: [AtomicBool; 2] = [const { AtomicBool::new(false) }; 2];
|
||||
@ -46,7 +46,7 @@ impl RxFuture {
|
||||
}
|
||||
|
||||
impl Future for RxFuture {
|
||||
type Output = Result<(), RxError>;
|
||||
type Output = Result<(), Infallible>;
|
||||
|
||||
fn poll(
|
||||
self: core::pin::Pin<&mut Self>,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user