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bump HAL and PAC

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This commit is contained in:
Robin Mueller
2025-09-03 10:30:39 +02:00
parent 07d8bc7952
commit c5a43356cc
35 changed files with 110 additions and 81 deletions
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21
README.md
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@@ -58,10 +58,27 @@ cp -rT vscode .vscode
You can then adapt the files in `.vscode` to your needs.
## Building projects
Building an application requires the `thumbv6m-none-eabi` cross-compiler toolchain.
If you have not installed it yet, you can do so with
```sh
rustup target add thumbv6m-none-eabi
```
After that, you can use `cargo build` to build the development version of the crate.
For example, you can use
```sh
cargo build --example blinky
```
to build a simple blinky app.
## Flashing, running and debugging the software
You can use CLI or VS Code for flashing, running and debugging. In any case, take
care of installing the pre-requisites first.
You can use CLI or VS Code for flashing, running and debugging.
### Using CLI with probe-rs

2
board-tests/Cargo.toml
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@@ -12,7 +12,7 @@ panic-probe = { version = "1", features = ["print-defmt"] }
embedded-hal = "1"
[dependencies.va108xx-hal]
version = "0.11"
version = "0.12"
features = ["rt"]
path = "../va108xx-hal"

2
bootloader/Cargo.toml
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@@ -15,7 +15,7 @@ num_enum = { version = "0.7", default-features = false }
static_assertions = "1"
[dependencies.va108xx-hal]
version = "0.11"
version = "0.12"
path = "../va108xx-hal"
features = ["defmt"]

4
bootloader/src/main.rs
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@@ -10,7 +10,7 @@ use num_enum::TryFromPrimitive;
use panic_probe as _;
// Import logger.
use defmt_rtt as _;
use va108xx_hal::{pac, spi::SpiClkConfig, time::Hertz, timer::CountdownTimer};
use va108xx_hal::{pac, spi::SpiClockConfig, time::Hertz, timer::CountdownTimer};
use vorago_reb1::m95m01::M95M01;
// Useful for debugging and see what the bootloader is doing. Enabled currently, because
@@ -106,7 +106,7 @@ fn main() -> ! {
let cp = cortex_m::Peripherals::take().unwrap();
let mut timer = CountdownTimer::new(dp.tim0, CLOCK_FREQ);
let clk_config = SpiClkConfig::new(2, 4);
let clk_config = SpiClockConfig::new(2, 4);
let mut nvm = M95M01::new(dp.spic, clk_config);
if FLASH_SELF {

4
examples/embassy/Cargo.toml
View File

@@ -26,8 +26,8 @@ embassy-executor = { version = "0.9", features = [
"executor-interrupt"
]}
va108xx-hal = { version = "0.11", path = "../../va108xx-hal", features = ["defmt"] }
va108xx-embassy = { version = "0.2", path = "../../va108xx-embassy" }
va108xx-hal = { version = "0.12", path = "../../va108xx-hal", features = ["defmt"] }
va108xx-embassy = { version = "0.3", path = "../../va108xx-embassy" }
[features]
default = ["ticks-hz-1_000", "va108xx-embassy/irq-oc30-oc31"]

2
examples/rtic/Cargo.toml
View File

@@ -13,5 +13,5 @@ rtic = { version = "2", features = ["thumbv6-backend"] }
rtic-monotonics = { version = "2", features = ["cortex-m-systick"] }
ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }
va108xx-hal = { version = "0.11", path = "../../va108xx-hal" }
va108xx-hal = { version = "0.12", path = "../../va108xx-hal" }
vorago-reb1 = { version = "0.8", path = "../../vorago-reb1" }

6
examples/rtic/src/bin/blinky-button-rtic.rs
View File

@@ -10,7 +10,7 @@ mod app {
// Import global logger.
use defmt_rtt as _;
use va108xx_hal::{
clock::{set_clk_div_register, FilterClkSel},
clock::{set_clk_div_register, FilterClockSelect},
gpio::{FilterType, InterruptEdge},
pac,
pins::PinsA,
@@ -60,8 +60,8 @@ mod app {
if mode == PressMode::Toggle {
// This filter debounces the switch for edge based interrupts
button.configure_filter_type(FilterType::FilterFourCycles, FilterClkSel::Clk1);
set_clk_div_register(&mut dp.sysconfig, FilterClkSel::Clk1, 50_000);
button.configure_filter_type(FilterType::FilterFourCycles, FilterClockSelect::Clk1);
set_clk_div_register(&mut dp.sysconfig, FilterClockSelect::Clk1, 50_000);
}
button.configure_and_enable_edge_interrupt(
edge_irq,

2
examples/simple/Cargo.toml
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@@ -16,6 +16,6 @@ embedded-io = "0.6"
portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }
[dependencies.va108xx-hal]
version = "0.11"
version = "0.12"
path = "../../va108xx-hal"
features = ["defmt"]

4
examples/simple/examples/spi.rs
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@@ -14,7 +14,7 @@ use va108xx_hal::{
pac,
pins::{PinsA, PinsB},
prelude::*,
spi::{self, configure_pin_as_hw_cs_pin, Spi, SpiClkConfig, TransferConfig},
spi::{self, configure_pin_as_hw_cs_pin, Spi, SpiClockConfig, TransferConfig},
timer::CountdownTimer,
};
@@ -45,7 +45,7 @@ fn main() -> ! {
let dp = pac::Peripherals::take().unwrap();
let mut delay = CountdownTimer::new(dp.tim0, 50.MHz());
let spi_clk_cfg = SpiClkConfig::from_clk(50.MHz(), SPI_SPEED_KHZ.kHz())
let spi_clk_cfg = SpiClockConfig::from_clk(50.MHz(), SPI_SPEED_KHZ.kHz())
.expect("creating SPI clock config failed");
let pinsa = PinsA::new(dp.porta);
let pinsb = PinsB::new(dp.portb);

4
examples/simple/examples/timer-ticks.rs
View File

@@ -41,8 +41,8 @@ fn main() -> ! {
dp.sysconfig
.tim_clk_enable()
.modify(|r, w| w.bits(r.bits() | (1 << 0) | (1 << 1)));
dp.irqsel.tim0(0).write(|w| w.bits(0x00));
dp.irqsel.tim0(1).write(|w| w.bits(0x01));
dp.irqsel.tim(0).write(|w| w.bits(0x00));
dp.irqsel.tim(1).write(|w| w.bits(0x01));
}
let sys_clk: Hertz = 50.MHz();

3
flashloader/Cargo.toml
View File

@@ -23,12 +23,13 @@ rtic = { version = "2", features = ["thumbv6-backend"] }
rtic-monotonics = { version = "2", features = ["cortex-m-systick"] }
[dependencies.va108xx-hal]
version = "0.11"
version = "0.12"
path = "../va108xx-hal"
features = ["defmt"]
[dependencies.vorago-reb1]
version = "0.8"
path = "../vorago-reb1"
[package.metadata.cargo-machete]
ignored = ["portable-atomic", "cortex-m-rt"]

12
flashloader/src/main.rs
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@@ -69,7 +69,8 @@ mod app {
tc::PusTcReader, tm::PusTmCreator, EcssEnumU8, PusPacket, WritablePusPacket,
};
use va108xx_hal::pins::PinsA;
use va108xx_hal::uart::IrqContextTimeoutOrMaxSize;
use va108xx_hal::spi::SpiClockConfig;
use va108xx_hal::uart::InterruptContextTimeoutOrMaxSize;
use va108xx_hal::{pac, uart, InterruptConfig};
use vorago_reb1::m95m01::M95M01;
@@ -85,7 +86,7 @@ mod app {
struct Local {
uart_rx: uart::RxWithInterrupt,
uart_tx: uart::Tx,
rx_context: IrqContextTimeoutOrMaxSize,
rx_context: InterruptContextTimeoutOrMaxSize,
verif_reporter: VerificationReportCreator,
nvm: M95M01,
}
@@ -105,8 +106,9 @@ mod app {
Mono::start(cx.core.SYST, SYSCLK_FREQ.raw());
let mut dp = cx.device;
let nvm = M95M01::new(&mut dp.sysconfig, SYSCLK_FREQ, dp.spic);
let dp = cx.device;
let spi_clock_config = SpiClockConfig::new(2, 4);
let nvm = M95M01::new(dp.spic, spi_clock_config);
let gpioa = PinsA::new(dp.porta);
let tx = gpioa.pa9;
@@ -127,7 +129,7 @@ mod app {
let verif_reporter = VerificationReportCreator::new(0).unwrap();
let mut rx_context = IrqContextTimeoutOrMaxSize::new(MAX_TC_FRAME_SIZE);
let mut rx_context = InterruptContextTimeoutOrMaxSize::new(MAX_TC_FRAME_SIZE);
rx.read_fixed_len_or_timeout_based_using_irq(&mut rx_context)
.expect("initiating UART RX failed");
pus_tc_handler::spawn().unwrap();

4
va108xx-embassy/Cargo.toml
View File

@@ -1,6 +1,6 @@
[package]
name = "va108xx-embassy"
version = "0.2.1"
version = "0.3.0"
edition = "2021"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
description = "Embassy-rs support for the Vorago VA108xx family of microcontrollers"
@@ -11,7 +11,7 @@ keywords = ["no-std", "hal", "cortex-m", "vorago", "va108xx"]
categories = ["aerospace", "embedded", "no-std", "hardware-support"]
[dependencies]
vorago-shared-periphs = { git = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs.git", features = ["vor1x"] }
vorago-shared-hal = { version = "0.2", features = ["vor1x"] }
va108xx-hal = { path = "../va108xx-hal" }
[features]

8
va108xx-embassy/src/lib.rs
View File

@@ -36,8 +36,8 @@
#[cfg(feature = "irqs-in-lib")]
use va108xx_hal::pac::{self, interrupt};
use va108xx_hal::time::Hertz;
use va108xx_hal::timer::TimMarker;
use vorago_shared_periphs::embassy::time_driver;
use va108xx_hal::timer::TimInstance;
use vorago_shared_hal::embassy::time_driver;
/// Macro to define the IRQ handlers for the time driver.
///
@@ -87,7 +87,7 @@ embassy_time_driver_irqs!(timekeeper_irq = OC29, alarm_irq = OC28);
/// This should be used if the interrupt handler is provided by the library, which is the
/// default case.
#[cfg(feature = "irqs-in-lib")]
pub fn init<TimekeeperTim: TimMarker, AlarmTim: TimMarker>(
pub fn init<TimekeeperTim: TimInstance, AlarmTim: TimInstance>(
timekeeper_tim: TimekeeperTim,
alarm_tim: AlarmTim,
sysclk: Hertz,
@@ -98,7 +98,7 @@ pub fn init<TimekeeperTim: TimMarker, AlarmTim: TimMarker>(
/// Initialization method for embassy when using custom IRQ handlers.
///
/// Requires an explicit [pac::Interrupt] argument for the timekeeper and alarm IRQs.
pub fn init_with_custom_irqs<TimekeeperTim: TimMarker, AlarmTim: TimMarker>(
pub fn init_with_custom_irqs<TimekeeperTim: TimInstance, AlarmTim: TimInstance>(
timekeeper_tim: TimekeeperTim,
alarm_tim: AlarmTim,
sysclk: Hertz,

7
va108xx-hal/CHANGELOG.md
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@@ -8,9 +8,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased]
## [v0.12.0] 2025-09-03
## Changed
- Move most library components to new [`vorago-shared-periphs`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs)
- Move most library components to new [`vorago-shared-hal`](https://egit.irs.uni-stuttgart.de/rust/vorago-shared-hal)
which is mostly re-exported in this crate.
- Overhaul and simplification of several HAL APIs. The system configuration and IRQ router
peripheral instance generally does not need to be passed to HAL API anymore.
@@ -274,7 +276,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
- Added basic test binary in form of an example
- README with basic instructions how to set up own binary crate
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...HEAD
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.12.0...HEAD
[v0.12.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.1...va108xx-hal-v0.12.0
[v0.11.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...va108xx-hal-v0.11.1
[v0.11.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.10.0...va108xx-hal-v0.11.0
[v0.10.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.9.0...va108xx-hal-v0.10.0

8
va108xx-hal/Cargo.toml
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@@ -1,6 +1,6 @@
[package]
name = "va108xx-hal"
version = "0.11.1"
version = "0.12.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "HAL for the Vorago VA108xx family of microcontrollers"
@@ -12,10 +12,10 @@ categories = ["aerospace", "embedded", "no-std", "hardware-support"]
[dependencies]
cortex-m = { version = "0.7", features = ["critical-section-single-core"]}
vorago-shared-periphs = { git = "https://egit.irs.uni-stuttgart.de/rust/vorago-shared-periphs.git", features = ["vor1x"] }
vorago-shared-hal = { version = "0.2", features = ["vor1x"] }
fugit = "0.3"
thiserror = { version = "2", default-features = false }
va108xx = { version = "0.5", default-features = false, features = ["critical-section", "defmt"] }
va108xx = { version = "0.6", default-features = false, features = ["critical-section", "defmt"] }
defmt = { version = "1", optional = true }
[target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies]
@@ -26,7 +26,7 @@ portable-atomic = "1"
[features]
default = ["rt"]
rt = ["va108xx/rt"]
defmt = ["dep:defmt", "vorago-shared-periphs/defmt"]
defmt = ["dep:defmt", "vorago-shared-hal/defmt"]
[package.metadata.docs.rs]
all-features = true

22
va108xx-hal/src/clock.rs
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@@ -1,31 +1,31 @@
//! # API for clock related functionality
//!
//! This also includes functionality to enable the peripheral clocks
pub use vorago_shared_periphs::gpio::FilterClkSel;
pub use vorago_shared_periphs::sysconfig::{disable_peripheral_clock, enable_peripheral_clock};
pub use vorago_shared_hal::gpio::FilterClockSelect;
pub use vorago_shared_hal::sysconfig::{disable_peripheral_clock, enable_peripheral_clock};
pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClkSel, div: u32) {
pub fn set_clk_div_register(syscfg: &mut va108xx::Sysconfig, clk_sel: FilterClockSelect, div: u32) {
match clk_sel {
FilterClkSel::SysClk => (),
FilterClkSel::Clk1 => {
FilterClockSelect::SysClk => (),
FilterClockSelect::Clk1 => {
syscfg.ioconfig_clkdiv1().write(|w| unsafe { w.bits(div) });
}
FilterClkSel::Clk2 => {
FilterClockSelect::Clk2 => {
syscfg.ioconfig_clkdiv2().write(|w| unsafe { w.bits(div) });
}
FilterClkSel::Clk3 => {
FilterClockSelect::Clk3 => {
syscfg.ioconfig_clkdiv3().write(|w| unsafe { w.bits(div) });
}
FilterClkSel::Clk4 => {
FilterClockSelect::Clk4 => {
syscfg.ioconfig_clkdiv4().write(|w| unsafe { w.bits(div) });
}
FilterClkSel::Clk5 => {
FilterClockSelect::Clk5 => {
syscfg.ioconfig_clkdiv5().write(|w| unsafe { w.bits(div) });
}
FilterClkSel::Clk6 => {
FilterClockSelect::Clk6 => {
syscfg.ioconfig_clkdiv6().write(|w| unsafe { w.bits(div) });
}
FilterClkSel::Clk7 => {
FilterClockSelect::Clk7 => {
syscfg.ioconfig_clkdiv7().write(|w| unsafe { w.bits(div) });
}
}

2
va108xx-hal/src/gpio/mod.rs
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@@ -17,4 +17,4 @@
//!
//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs)
//! - [Async GPIO example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-gpio.rs)
pub use vorago_shared_periphs::gpio::*;
pub use vorago_shared_hal::gpio::*;

2
va108xx-hal/src/i2c.rs
View File

@@ -3,4 +3,4 @@
//! ## Examples
//!
//! - [REB1 I2C temperature sensor example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/adt75-temp-sensor.rs)
pub use vorago_shared_periphs::i2c::*;
pub use vorago_shared_hal::i2c::*;

9
va108xx-hal/src/lib.rs
View File

@@ -17,8 +17,9 @@ pub mod time;
pub mod timer;
pub mod uart;
pub use vorago_shared_periphs::{
disable_nvic_interrupt, enable_nvic_interrupt, FunSel, InterruptConfig, PeripheralSelect,
pub use vorago_shared_hal::{
disable_nvic_interrupt, enable_nvic_interrupt, FunctionSelect, InterruptConfig,
PeripheralSelect,
};
/// This is the NONE destination reigster value for the IRQSEL peripheral.
@@ -38,7 +39,7 @@ pub fn port_function_select(
ioconfig: &mut pac::Ioconfig,
port: Port,
pin: u8,
funsel: FunSel,
funsel: FunctionSelect,
) -> Result<(), InvalidPinError> {
if (port == Port::A && pin >= 32) || (port == Port::B && pin >= 24) {
return Err(InvalidPinError(pin));
@@ -46,7 +47,7 @@ pub fn port_function_select(
let reg_block = match port {
Port::A => ioconfig.porta(pin as usize),
Port::B => ioconfig.portb0(pin as usize),
Port::B => ioconfig.portb(pin as usize),
};
reg_block.modify(|_, w| unsafe { w.funsel().bits(funsel as u8) });

2
va108xx-hal/src/pins.rs
View File

@@ -3,4 +3,4 @@
//! This module contains the pin singletons. It allows creating those singletons
//! to access the [Pin] structures of individual ports in a safe way with checked ownership
//! rules.
pub use vorago_shared_periphs::pins::*;
pub use vorago_shared_hal::pins::*;

2
va108xx-hal/src/pwm.rs
View File

@@ -5,4 +5,4 @@
//! ## Examples
//!
//! - [PWM example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/pwm.rs)
pub use vorago_shared_periphs::pwm::*;
pub use vorago_shared_hal::pwm::*;

2
va108xx-hal/src/spi/mod.rs
View File

@@ -9,4 +9,4 @@
//! - [Blocking SPI example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/spi.rs)
//! - [REB1 ADC example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/max11519-adc.rs)
//! - [REB1 EEPROM library](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/src/m95m01.rs)
pub use vorago_shared_periphs::spi::*;
pub use vorago_shared_hal::spi::*;

2
va108xx-hal/src/sysconfig.rs
View File

@@ -38,6 +38,6 @@ pub fn disable_ram_scrubbing() {
syscfg.ram_scrub().write(|w| unsafe { w.bits(0) });
}
pub use vorago_shared_periphs::sysconfig::{
pub use vorago_shared_hal::sysconfig::{
assert_peripheral_reset, disable_peripheral_clock, enable_peripheral_clock,
};

2
va108xx-hal/src/time.rs
View File

@@ -1,2 +1,2 @@
//! Time units
pub use vorago_shared_periphs::time::*;
pub use vorago_shared_hal::time::*;

2
va108xx-hal/src/timer.rs
View File

@@ -4,4 +4,4 @@
//!
//! - [MS and second tick implementation](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/timer-ticks.rs)
//! - [Cascade feature example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/cascade.rs)
pub use vorago_shared_periphs::timer::*;
pub use vorago_shared_hal::timer::*;

2
va108xx-hal/src/uart/mod.rs
View File

@@ -14,4 +14,4 @@
//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader)
//! - [Async UART RX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-rx.rs)
//! - [Async UART TX example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/embassy/src/bin/async-uart-tx.rs)
pub use vorago_shared_periphs::uart::*;
pub use vorago_shared_hal::uart::*;

7
vorago-reb1/CHANGELOG.md
View File

@@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased]
## [v0.8.2] 2025-09-03
- Bumped allowed `va108xx-hal` dependency to 0.12
## [v0.8.1] 2025-03-07
- Bumped allowed `va108xx-hal` dependency to 0.11
@@ -62,7 +66,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
it provides a starting point
- Added ADC base library and example building on the new max116xx-10bit device driver crate
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/vorago-reb1-v0.8.1...HEAD
[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/vorago-reb1-v0.8.2...HEAD
[v0.8.2]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/vorago-reb1-v0.8.1...vorago-reb1-v0.8.2
[v0.8.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/vorago-reb1-v0.8.0...vorago-reb1-v0.8.1
[v0.8.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/vorago-reb1-v0.7.0...vorago-reb1-v0.8.0
[v0.7.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/vorago-reb1-v0.6.0...vorago-reb1-v0.7.0

6
vorago-reb1/Cargo.toml
View File

@@ -1,6 +1,6 @@
[package]
name = "vorago-reb1"
version = "0.8.1"
version = "0.8.2"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "Board Support Crate for the Vorago REB1 development board"
@@ -16,10 +16,10 @@ cortex-m-rt = "0.7"
embedded-hal = "1"
nb = "1"
bitbybit = "1.3"
arbitrary-int = "1.3"
arbitrary-int = "2"
max116xx-10bit = "0.3"
va108xx-hal = { version = ">=0.10, <=0.11", path = "../va108xx-hal", features = ["rt"] }
va108xx-hal = { version = "0.12", path = "../va108xx-hal", features = ["rt"] }
[features]
rt = ["va108xx-hal/rt"]

4
vorago-reb1/examples/adxl343-accelerometer.rs
View File

@@ -11,7 +11,7 @@ use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print};
use va108xx_hal::gpio::{Output, PinState};
use va108xx_hal::pins::PinsA;
use va108xx_hal::spi::{configure_pin_as_hw_cs_pin, SpiClkConfig};
use va108xx_hal::spi::{configure_pin_as_hw_cs_pin, SpiClockConfig};
use va108xx_hal::timer::CountdownTimer;
use va108xx_hal::{
pac,
@@ -42,7 +42,7 @@ fn main() -> ! {
let spi_cfg = SpiConfig::default()
.clk_cfg(
SpiClkConfig::from_clk(50.MHz(), 1.MHz()).expect("creating SPI clock config failed"),
SpiClockConfig::from_clk(50.MHz(), 1.MHz()).expect("creating SPI clock config failed"),
)
.mode(MODE_3)
.slave_output_disable(true);

6
vorago-reb1/examples/blinky-button-irq.rs
View File

@@ -9,7 +9,7 @@ use cortex_m_rt::entry;
use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print};
use va108xx_hal::{
clock::{set_clk_div_register, FilterClkSel},
clock::{set_clk_div_register, FilterClockSelect},
gpio::{FilterType, InterruptEdge},
pac::{self, interrupt},
pins::PinsA,
@@ -46,8 +46,8 @@ fn main() -> ! {
if PRESS_MODE == PressMode::Toggle {
// This filter debounces the switch for edge based interrupts
button.configure_filter_type(FilterType::FilterFourCycles, FilterClkSel::Clk1);
set_clk_div_register(&mut dp.sysconfig, FilterClkSel::Clk1, 50_000);
button.configure_filter_type(FilterType::FilterFourCycles, FilterClockSelect::Clk1);
set_clk_div_register(&mut dp.sysconfig, FilterClockSelect::Clk1, 50_000);
}
button.configure_and_enable_edge_interrupt(
edge_irq,

14
vorago-reb1/examples/max11619-adc.rs
View File

@@ -16,14 +16,14 @@ use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print};
use va108xx_hal::gpio::{Input, Output, PinState, Port};
use va108xx_hal::pins::PinsA;
use va108xx_hal::spi::{configure_pin_as_hw_cs_pin, SpiClkConfig};
use va108xx_hal::spi::{configure_pin_as_hw_cs_pin, SpiClockConfig};
use va108xx_hal::timer::CountdownTimer;
use va108xx_hal::{
pac,
prelude::*,
spi::{HwChipSelectId, Spi, SpiConfig},
};
use va108xx_hal::{port_function_select, FunSel};
use va108xx_hal::{port_function_select, FunctionSelect};
use vorago_reb1::max11619::{
max11619_externally_clocked_no_wakeup, max11619_externally_clocked_with_wakeup,
max11619_internally_clocked, AN2_CHANNEL, POTENTIOMETER_CHANNEL,
@@ -117,16 +117,16 @@ fn main() -> ! {
let pinsa = PinsA::new(dp.porta);
let spi_cfg = SpiConfig::default()
.clk_cfg(SpiClkConfig::from_clk(SYS_CLK, 3.MHz()).unwrap())
.clk_cfg(SpiClockConfig::from_clk(SYS_CLK, 3.MHz()).unwrap())
.mode(MODE_0)
.blockmode(true);
let (sck, mosi, miso) = (pinsa.pa20, pinsa.pa19, pinsa.pa18);
if MUX_MODE == MuxMode::PortB19to17 {
port_function_select(&mut dp.ioconfig, Port::B, 19, FunSel::Sel1).ok();
port_function_select(&mut dp.ioconfig, Port::B, 18, FunSel::Sel2).ok();
port_function_select(&mut dp.ioconfig, Port::B, 17, FunSel::Sel1).ok();
port_function_select(&mut dp.ioconfig, Port::B, 16, FunSel::Sel1).ok();
port_function_select(&mut dp.ioconfig, Port::B, 19, FunctionSelect::Sel1).ok();
port_function_select(&mut dp.ioconfig, Port::B, 18, FunctionSelect::Sel2).ok();
port_function_select(&mut dp.ioconfig, Port::B, 17, FunctionSelect::Sel1).ok();
port_function_select(&mut dp.ioconfig, Port::B, 16, FunctionSelect::Sel1).ok();
}
// Set the accelerometer chip select low in case the board slot is populated
Output::new(pinsa.pa16, PinState::Low);

4
vorago-reb1/examples/nvm.rs
View File

@@ -5,7 +5,7 @@ use cortex_m_rt::entry;
use embedded_hal::delay::DelayNs;
use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print};
use va108xx_hal::{pac, spi::SpiClkConfig, time::Hertz, timer::CountdownTimer};
use va108xx_hal::{pac, spi::SpiClockConfig, time::Hertz, timer::CountdownTimer};
use vorago_reb1::m95m01::{M95M01, PAGE_SIZE};
const CLOCK_FREQ: Hertz = Hertz::from_raw(50_000_000);
@@ -18,7 +18,7 @@ fn main() -> ! {
let dp = pac::Peripherals::take().unwrap();
let mut delay = CountdownTimer::new(dp.tim0, CLOCK_FREQ);
let clk_config = SpiClkConfig::new(2, 4);
let clk_config = SpiClockConfig::new(2, 4);
let mut nvm = M95M01::new(dp.spic, clk_config);
let status_reg = nvm.read_status_reg().expect("reading status reg failed");
if status_reg.zero_segment().value() == 0b111 {

4
vorago-reb1/src/button.rs
View File

@@ -5,7 +5,7 @@
//! - [Button Blinky with IRQs](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-irq.rs)
//! - [Button Blinky with IRQs and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/vorago-reb1/examples/blinky-button-rtic.rs)
use va108xx_hal::{
clock::FilterClkSel,
clock::FilterClockSelect,
gpio::{FilterType, Input, InterruptEdge, InterruptLevel, Pin},
pins::Pa11,
InterruptConfig,
@@ -53,7 +53,7 @@ impl Button {
///
/// Please note that you still have to set a clock divisor yourself using the
/// [`va108xx_hal::clock::set_clk_div_register`] function in order for this to work.
pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClockSelect) {
self.0.configure_filter_type(filter, clksel);
}
}

4
vorago-reb1/src/m95m01.rs
View File

@@ -47,7 +47,7 @@ pub mod regs {
use regs::*;
use va108xx_hal::{
pac,
spi::{Spi, SpiClkConfig, SpiConfig, SpiLowLevel, BMSTART_BMSTOP_MASK},
spi::{Spi, SpiClockConfig, SpiConfig, SpiLowLevel, BMSTART_BMSTOP_MASK},
};
pub type RomSpi = Spi<u8>;
@@ -63,7 +63,7 @@ pub struct M95M01 {
pub struct PageBoundaryExceededError;
impl M95M01 {
pub fn new(spi: pac::Spic, clk_config: SpiClkConfig) -> Self {
pub fn new(spi: pac::Spic, clk_config: SpiClockConfig) -> Self {
let spi = RomSpi::new_for_rom(spi, SpiConfig::default().clk_cfg(clk_config)).unwrap();
let mut spi_dev = Self { spi };
spi_dev.clear_block_protection().unwrap();