rust/va108xx-rs
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re-worked SPI code
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This commit is contained in:
Robin Müller
2024-09-20 10:32:25 +02:00
parent 8ca46b26c4
commit dc77f3a129
10 changed files with 575 additions and 437 deletions
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20
vorago-reb1/examples/adxl343-accelerometer.rs
View File

@ -5,7 +5,7 @@
#![no_main]
#![no_std]
use cortex_m_rt::entry;
use embedded_hal::spi::SpiBus;
use embedded_hal::spi::{SpiBus, MODE_3};
use embedded_hal::{delay::DelayNs, digital::OutputPin};
use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print};
@ -14,7 +14,7 @@ use va108xx_hal::{
gpio::PinsA,
pac,
prelude::*,
spi::{Spi, SpiConfig, TransferConfigWithHwcs},
spi::{Spi, SpiConfig},
timer::set_up_ms_delay_provider,
};
@ -32,7 +32,6 @@ fn main() -> ! {
let mut dp = pac::Peripherals::take().unwrap();
let mut delay = set_up_ms_delay_provider(&mut dp.sysconfig, 50.MHz(), dp.tim0);
let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
let spi_cfg = SpiConfig::default();
let (sck, mosi, miso) = (
pinsa.pa20.into_funsel_2(),
pinsa.pa19.into_funsel_2(),
@ -46,21 +45,20 @@ fn main() -> ! {
.set_high()
.expect("Setting ADC chip select high failed");
let transfer_cfg = TransferConfigWithHwcs::new(
Some(SpiClkConfig::from_clk(50.MHz(), 1.MHz()).expect("creating SPI clock config failed")),
Some(embedded_hal::spi::MODE_3),
Some(cs_pin),
false,
true,
);
let spi_cfg = SpiConfig::default()
.clk_cfg(
SpiClkConfig::from_clk(50.MHz(), 1.MHz()).expect("creating SPI clock config failed"),
)
.mode(MODE_3)
.slave_output_disable(true);
let mut spi = Spi::new(
&mut dp.sysconfig,
50.MHz(),
dp.spib,
(sck, miso, mosi),
spi_cfg,
Some(&transfer_cfg.downgrade()),
);
spi.cfg_hw_cs_with_pin(&cs_pin);
let mut tx_rx_buf: [u8; 3] = [0; 3];
tx_rx_buf[0] = READ_MASK | DEVID_REG;

10
vorago-reb1/examples/max11619-adc.rs
View File

@ -9,7 +9,7 @@ use core::convert::Infallible;
use cortex_m_rt::entry;
use embedded_hal::digital::OutputPin;
use embedded_hal::spi::{SpiBus, SpiDevice};
use embedded_hal::spi::{SpiBus, SpiDevice, MODE_0};
use embedded_hal::{delay::DelayNs, spi};
use max116xx_10bit::VoltageRefMode;
use max116xx_10bit::{AveragingConversions, AveragingResults};
@ -21,7 +21,7 @@ use va108xx_hal::{
gpio::PinsA,
pac::{self, interrupt},
prelude::*,
spi::{Spi, SpiBase, SpiConfig, TransferConfigWithHwcs},
spi::{Spi, SpiBase, SpiConfig},
timer::{default_ms_irq_handler, set_up_ms_tick, DelayMs, IrqCfg},
};
use va108xx_hal::{port_mux, FunSel, PortSel};
@ -124,7 +124,10 @@ fn main() -> ! {
}
let pinsa = PinsA::new(&mut dp.sysconfig, None, dp.porta);
let spi_cfg = SpiConfig::default().clk_cfg(SpiClkConfig::from_clk(SYS_CLK, 3.MHz()).unwrap());
let spi_cfg = SpiConfig::default()
.clk_cfg(SpiClkConfig::from_clk(SYS_CLK, 3.MHz()).unwrap())
.mode(MODE_0)
.blockmode(true);
let (sck, mosi, miso) = (
pinsa.pa20.into_funsel_2(),
pinsa.pa19.into_funsel_2(),
@ -143,7 +146,6 @@ fn main() -> ! {
.set_high()
.expect("Setting accelerometer chip select high failed");
let transfer_cfg = TransferConfigWithHwcs::new_no_hw_cs(None, Some(spi::MODE_0), true, false);
let spi = Spi::new(
&mut dp.sysconfig,
50.MHz(),

91
vorago-reb1/examples/nvm.rs
View File

@ -1,23 +1,13 @@
//! Example application which interfaces with the boot EEPROM.
#![no_main]
#![no_std]
use cortex_m_rt::entry;
use embedded_hal::spi::{SpiBus, MODE_0};
use embedded_hal_bus::spi::ExclusiveDevice;
use embedded_hal::delay::DelayNs;
use panic_rtt_target as _;
use rtt_target::{rprintln, rtt_init_print};
use va108xx_hal::{
pac,
spi::{
RomCs, RomMiso, RomMosi, RomSck, Spi, SpiClkConfig, SpiConfig, TransferConfigWithHwcs,
BMSTART_BMSTOP_MASK,
},
time::Hertz,
};
use vorago_reb1::m95m01::{
regs::{RDSR, WREN},
StatusReg, M95M01,
};
use va108xx_hal::{pac, pwm::CountDownTimer, time::Hertz};
use vorago_reb1::m95m01::M95M01;
const CLOCK_FREQ: Hertz = Hertz::from_raw(50_000_000);
@ -27,49 +17,48 @@ fn main() -> ! {
rprintln!("-- VA108XX REB1 NVM example --");
let mut dp = pac::Peripherals::take().unwrap();
let cp = cortex_m::Peripherals::take().unwrap();
let mut spi = Spi::<pac::Spic, (RomSck, RomMiso, RomMosi)>::new(
&mut dp.sysconfig,
CLOCK_FREQ,
dp.spic,
(RomSck, RomMiso, RomMosi),
// These values are taken from the vorago bootloader app, don't want to experiment here..
SpiConfig::default().clk_cfg(SpiClkConfig::new(2, 4)),
);
let mut read_buf: [u8; 2] = [0; 2];
let spi = spi.spi();
unsafe {
spi.data().write(|w| w.bits(RDSR.into()));
spi.data().write(|w| w.bits(0 | BMSTART_BMSTOP_MASK));
}
while spi.status().read().tfe().bit_is_clear() {}
while spi.status().read().rne().bit_is_clear() {}
let dummy = spi.data().read().bits();
while spi.status().read().rne().bit_is_clear() {}
let reg = StatusReg(spi.data().read().bits() as u8);
rprintln!("status reg {:?}", reg);
//spi.transfer(&mut read_buf, &[RDSR, 0]);
rprintln!("read buf {:?}", read_buf);
//spi.write(&[WREN]);
/*
let mut nvm =
M95M01::new(ExclusiveDevice::new_no_delay(spi, dummy_pin::DummyPin::new_low()).unwrap())
.expect("creating NVM structure failed");
let mut timer = CountDownTimer::new(&mut dp.sysconfig, CLOCK_FREQ, dp.tim0);
let mut nvm = M95M01::new(&mut dp.sysconfig, CLOCK_FREQ, dp.spic);
let status_reg = nvm.read_status_reg().expect("reading status reg failed");
rprintln!("status reg: {:?}", status_reg);
if status_reg.zero_segment() == 0b111 {
panic!("status register unexpected values");
}
let mut orig_content: [u8; 16] = [0; 16];
let mut read_buf: [u8; 16] = [0; 16];
nvm.read(0x4000, &mut read_buf[0..4])
.expect("reading NVM failed");
rprintln!("NVM address 0x4000: {:x?}", &read_buf[0..4]);
let write_buf: [u8; 4] = [1, 2, 3, 4];
nvm.write(0x4000, &write_buf).unwrap();
let write_buf: [u8; 16] = [0; 16];
for (idx, val) in read_buf.iter_mut().enumerate() {
*val = idx as u8;
}
nvm.read(0x4000, &mut orig_content).unwrap();
// One byte write and read.
nvm.write(0x4000, &write_buf[0..1]).unwrap();
nvm.read(0x4000, &mut read_buf[0..1]).unwrap();
assert_eq!(write_buf[0], read_buf[0]);
read_buf.fill(0);
// Four bytes write and read.
nvm.write(0x4000, &write_buf[0..4]).unwrap();
nvm.read(0x4000, &mut read_buf[0..4]).unwrap();
assert_eq!(&read_buf[0..4], write_buf);
*/
loop {}
assert_eq!(&read_buf[0..4], &write_buf[0..4]);
read_buf.fill(0);
// Full sixteen bytes
nvm.write(0x4000, &write_buf).unwrap();
nvm.read(0x4000, &mut read_buf).unwrap();
assert_eq!(&read_buf, &write_buf);
read_buf.fill(0);
// 3 bytes
nvm.write(0x4000, &write_buf[0..3]).unwrap();
nvm.read(0x4000, &mut read_buf[0..3]).unwrap();
assert_eq!(&read_buf[0..3], &write_buf[0..3]);
// Write back original content.
nvm.write(0x4000, &orig_content).unwrap();
loop {
timer.delay_ms(500);
}
}