Merge pull request 'prepare BSP release' (#19) from prep-bsp-release into main

Reviewed-on: #19

board-tests/Cargo.toml

@@ -14,7 +14,6 @@ embedded-hal-nb = "1"
 embedded-io = "0.6"
 
 [dependencies.va108xx-hal]
-version = "0.7"
 path = "../va108xx-hal"
 features = ["rt"]
 

examples/rtic/Cargo.toml

@@ -38,7 +38,7 @@ default-features = false
 features = ["portable-atomic"]
 
 [dependencies.va108xx-hal]
-path = "../../va108xx-hal"
+version = "0.8"
 
 [dependencies.vorago-reb1]
 path = "../../vorago-reb1"

examples/simple/Cargo.toml

@@ -16,7 +16,7 @@ embedded-io = "0.6"
 cortex-m-semihosting = "0.5.0"
 
 [dependencies.va108xx-hal]
-path = "../../va108xx-hal"
+version = "0.8"
 features = ["rt", "defmt"]
 
 [dependencies.vorago-reb1]

va108xx-hal/CHANGELOG.md

@@ -8,6 +8,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
+## [v0.8.0] 2024-09-30
+
 ## Changed
 
 - Improves `CascardSource` handling and general API when chosing cascade sources.

va108xx-hal/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "va108xx-hal"
-version = "0.7.0"
+version = "0.8.0"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "HAL for the Vorago VA108xx family of microcontrollers"

va108xx-hal/src/uart.rs

@@ -3,7 +3,8 @@
 //! ## Examples
 //!
 //! - [UART simple example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/uart.rs)
-//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/va108xx-update-package/examples/rtic/src/bin/uart-rtic.rs)
+//! - [UART with IRQ and RTIC](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/rtic/src/bin/uart-echo-rtic.rs)
+//! - [Flashloader exposing a CCSDS interface via UART](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/flashloader)
 use core::{convert::Infallible, ops::Deref};
 use fugit::RateExtU32;
 use va108xx::Uarta;
@@ -863,7 +864,7 @@ impl<Uart: Instance> Tx<Uart> {
     ///
     /// This does not necesarily mean that the FIFO can process another word because it might be
     /// full.
-    /// Use the [Self::read_fifo] function to write a word to the FIFO reliably using the [nb]
+    /// Use the [Self::write_fifo] function to write a word to the FIFO reliably using the [nb]
     /// API.
     #[inline(always)]
     pub fn write_fifo_unchecked(&self, data: u32) {
@@ -916,7 +917,7 @@ impl<Uart: Instance> embedded_io::Write for Tx<Uart> {
 
 /// Serial receiver, using interrupts to offload reading to the hardware.
 ///
-/// You can use [Rx::to_rx_with_irq] to convert a normal [Rx] structure into this structure.
+/// You can use [Rx::into_rx_with_irq] to convert a normal [Rx] structure into this structure.
 /// This structure provides two distinct ways to read the UART RX using interrupts. It should
 /// be noted that the interrupt service routine (ISR) still has to be provided by the user. However,
 /// this structure provides API calls which can be used inside the ISRs to simplify the reading

vorago-reb1/CHANGELOG.md

@@ -8,7 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [unreleased]
 
+## [v0.6.0] 2024-09-30
+
 - Added M95M01 EEPROM module/API
+- Update `va108xx-hal` dependency to range >=v0.8, <0.9
 
 ## [v0.5.1] 2024-07-04
 

vorago-reb1/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "vorago-reb1"
-version = "0.5.1"
+version = "0.6.0"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "Board Support Crate for the Vorago REB1 development board"
@@ -21,8 +21,7 @@ bitfield = "0.17"
 version = "0.3"
 
 [dependencies.va108xx-hal]
-version = ">=0.7, <0.8"
-path = "../va108xx-hal"
+version = ">=0.8, <0.9"
 features = ["rt"]
 
 [features]