Merge pull request 'check all updated dependencies' (#69) from check-all-updates-deps into main

Reviewed-on: #69

examples/embassy/Cargo.toml

@@ -27,8 +27,8 @@ embassy-executor = { version = "0.7", features = [
   "executor-interrupt"
 ]}
 
-va108xx-hal = { version = "0.10" }
-va108xx-embassy = { version = "0.2" }
+va108xx-hal = { version = "0.11", path = "../../va108xx-hal" }
+va108xx-embassy = { version = "0.2", path = "../../va108xx-embassy" }
 
 [features]
 default = ["ticks-hz-1_000", "va108xx-embassy/irq-oc30-oc31"]

examples/rtic/Cargo.toml

@@ -22,5 +22,5 @@ rtic-sync = { version = "1.3", features = ["defmt-03"] }
 once_cell = {version = "1", default-features = false, features = ["critical-section"]}
 ringbuf = { version = "0.4.7", default-features = false, features = ["portable-atomic"] }
 
-va108xx-hal = { version = "0.10" }
-vorago-reb1 = { version = "0.8" }
+va108xx-hal = { version = "0.11", path = "../../va108xx-hal" }
+vorago-reb1 = { version = "0.8", path = "../../vorago-reb1" }

examples/simple/Cargo.toml

@@ -16,8 +16,10 @@ embedded-io = "0.6"
 cortex-m-semihosting = "0.5.0"
 
 [dependencies.va108xx-hal]
-version = "0.10"
+version = "0.11"
+path = "../../va108xx-hal"
 features = ["rt", "defmt"]
 
 [dependencies.vorago-reb1]
 version = "0.8"
+path = "../../vorago-reb1"

va108xx-embassy/Cargo.toml

@@ -20,7 +20,7 @@ embassy-time-queue-utils = "0.1"
 
 once_cell = { version = "1", default-features = false, features = ["critical-section"] }
 
-va108xx-hal = { version = "0.10" }
+va108xx-hal = { version = "0.11", path = "../va108xx-hal" }
 
 [target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies]
 portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }

va108xx-hal/CHANGELOG.md

@@ -12,6 +12,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## Changed
 
+- Bugfix for I2C `TimingCfg::reg`
 - Simplified UART error handling. All APIs are now infallible because writing to a FIFO or
   reading from a FIFO never fails. Users can either poll errors using `Rx::poll_errors` or
   `Uart::poll_rx_errors` / `UartBase::poll_rx_errors`, or detect errors using the provided
@@ -113,14 +114,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Updated `embedded-hal` to v1
 - Added optional `defmt` v0.3 feature and support.
 
-## [v0.5.2] 2024-06-16
+## v0.5.2 2024-06-16
 
 ## Fixed
 
 - Replaced usage to `ptr::write_volatile` in UART module which is denied on more recent Rust
   compilers.
 
-## [v0.5.1]
+## v0.5.1
 
 ### Changes
 
@@ -129,7 +130,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
   - `once_cell` to 1.12.0
   - Other dependencies: Only revision has changed
 
-## [v0.5.0]
+## v0.5.0
 
 ### Added
 
@@ -142,14 +143,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Bugfix in UART code where RX and TX could not be enabled or disabled independently
 
-## [v0.4.3]
+## v0.4.3
 
 - Various smaller fixes for READMEs, update of links in documentation
 - Simplified CI for github, do not use `cross`
 - New `blinky-pac` example
 - Use HAL delay in `blinky` example
 
-## [v0.4.2]
+## v0.4.2
 
 ### Added
 
@@ -159,24 +160,24 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Clear TX and RX FIFO in SPI transfer function
 
-## [v0.4.1]
+## v0.4.1
 
 ### Fixed
 
 - Initial blockmode setting was not set in SPI constructor
 
-## [v0.4.0]
+## v0.4.0
 
 ### Changed
 
 - Replaced `Hertz` by `impl Into<Hertz>` completely and removed
   `+ Copy` where not necessary
 
-## [v0.3.1]
+## v0.3.1
 
 - Updated all links to point to new repository
 
-## [v0.3.0]
+## v0.3.0
 
 ### Added
 
@@ -188,7 +189,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Primary repository now hosted on IRS external git: https://egit.irs.uni-stuttgart.de/rust/va108xx-hal
 - Relicensed as Apache-2.0
 
-## [0.2.3]
+## v0.2.3
 
 ### Added
 
@@ -200,7 +201,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Improved Timer API. It is now possible to simply use `new` on `CountDownTimer`
 
-## [0.2.2]
+## v0.2.2
 
 ### Added
 
@@ -212,7 +213,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - API which expects values in Hertz now uses `impl Into<Hertz>` as input parameter
 
-## [0.2.1]
+## v0.2.1
 
 ### Added
 
@@ -226,7 +227,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Moved the `FilterClkSel` struct to the `clock` module, re-exporting in `gpio`
 - Clearing output state at initialization of Output pins
 
-## [0.2.0]
+## v0.2.0
 
 ### Changed
 
@@ -241,7 +242,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Some bugfixes for GPIO implementation
 - Rust edition updated to 2021
 
-## [0.1.0]
+## v0.1.0
 
 ### Added
 
@@ -251,7 +252,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Added basic test binary in form of an example
 - README with basic instructions how to set up own binary crate
 
-[unreleased]: https://github.com/rust-embedded/cortex-ar/compare/cortex-ar-v0.1.0...HEAD
+[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...HEAD
 [v0.11.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.10.0...va108xx-hal-v0.11.0
 [v0.10.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.9.0...va108xx-hal-v0.10.0
 [v0.9.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.8.0...va108xx-hal-v0.9.0

va108xx-hal/Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "va108xx-hal"
-version = "0.10.0"
+version = "0.11.0"
 authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
 edition = "2021"
 description = "HAL for the Vorago VA108xx family of microcontrollers"

va108xx-hal/src/i2c.rs

@@ -198,13 +198,13 @@ impl TimingCfg {
     }
 
     pub fn reg(&self) -> u32 {
-        (self.tbuf as u32) << 28
-            | (self.thd_sta as u32) << 24
-            | (self.tsu_sta as u32) << 20
-            | (self.tsu_sto as u32) << 16
-            | (self.tlow as u32) << 12
-            | (self.thigh as u32) << 8
-            | (self.tf as u32) << 4
+        ((self.tbuf as u32) << 28)
+            | ((self.thd_sta as u32) << 24)
+            | ((self.tsu_sta as u32) << 20)
+            | ((self.tsu_sto as u32) << 16)
+            | ((self.tlow as u32) << 12)
+            | ((self.thigh as u32) << 8)
+            | ((self.tf as u32) << 4)
             | (self.tr as u32)
     }
 }
@@ -376,7 +376,7 @@ impl<I2c: Instance> I2cBase<I2c> {
         if let Some(max_words) = max_words {
             self.i2c
                 .s0_maxwords()
-                .write(|w| unsafe { w.bits(1 << 31 | max_words as u32) });
+                .write(|w| unsafe { w.bits((1 << 31) | max_words as u32) });
         }
         let (addr, addr_mode_mask) = Self::unwrap_addr(sl_cfg.addr);
         // The first bit is the read/write value. Normally, both read and write are matched
@@ -437,7 +437,7 @@ impl<I2c: Instance> I2cBase<I2c> {
         let clk_div = self.calc_clk_div(speed_mode)?;
         self.i2c
             .clkscale()
-            .write(|w| unsafe { w.bits((speed_mode as u32) << 31 | clk_div as u32) });
+            .write(|w| unsafe { w.bits(((speed_mode as u32) << 31) | clk_div as u32) });
         Ok(())
     }
 

vorago-reb1/Cargo.toml

@@ -18,7 +18,7 @@ nb = "1"
 bitfield = ">=0.17, <=0.18"
 max116xx-10bit = "0.3"
 
-va108xx-hal = { version = "0.10", features = ["rt"] }
+va108xx-hal = { version = ">=0.10, <=0.11", path = "../va108xx-hal", features = ["rt"] }
 
 [features]
 rt = ["va108xx-hal/rt"]