Compare commits
12 Commits
fc894bc421
...
31b25b0211
Author | SHA1 | Date | |
---|---|---|---|
31b25b0211 | |||
8b55d0923f | |||
a65f4039ee | |||
97da2a0752
|
|||
c43d1f8861 | |||
181c2bdc7b | |||
2bca96b5db | |||
bf41b59a24 | |||
6cbba8414c | |||
fe04a3e7cd
|
|||
e25fb20b08 | |||
67af1bb9b5 |
6
.github/workflows/ci.yml
vendored
6
.github/workflows/ci.yml
vendored
@ -12,6 +12,8 @@ jobs:
|
|||||||
targets: "thumbv6m-none-eabi"
|
targets: "thumbv6m-none-eabi"
|
||||||
- run: cargo check --target thumbv6m-none-eabi
|
- run: cargo check --target thumbv6m-none-eabi
|
||||||
- run: cargo check --target thumbv6m-none-eabi --examples
|
- run: cargo check --target thumbv6m-none-eabi --examples
|
||||||
|
- run: cargo check -p va108xx --target thumbv6m-none-eabi --all-features
|
||||||
|
- run: cargo check -p va108xx-hal --target thumbv6m-none-eabi --features "defmt"
|
||||||
|
|
||||||
test:
|
test:
|
||||||
name: Run Tests
|
name: Run Tests
|
||||||
@ -39,8 +41,8 @@ jobs:
|
|||||||
steps:
|
steps:
|
||||||
- uses: actions/checkout@v4
|
- uses: actions/checkout@v4
|
||||||
- uses: dtolnay/rust-toolchain@nightly
|
- uses: dtolnay/rust-toolchain@nightly
|
||||||
- run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx
|
- run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx --all-features
|
||||||
- run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx-hal
|
- run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p va108xx-hal --all-features
|
||||||
- run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p vorago-reb1
|
- run: RUSTDOCFLAGS="--cfg docsrs --generate-link-to-definition -Z unstable-options" cargo +nightly doc -p vorago-reb1
|
||||||
|
|
||||||
clippy:
|
clippy:
|
||||||
|
@ -122,14 +122,14 @@ fn main() -> ! {
|
|||||||
}
|
}
|
||||||
TestCase::Pulse => {
|
TestCase::Pulse => {
|
||||||
let mut output_pulsed = pinsa.pa0.into_push_pull_output();
|
let mut output_pulsed = pinsa.pa0.into_push_pull_output();
|
||||||
output_pulsed.pulse_mode(true, PinState::Low);
|
output_pulsed.configure_pulse_mode(true, PinState::Low);
|
||||||
rprintln!("Pulsing high 10 times..");
|
rprintln!("Pulsing high 10 times..");
|
||||||
output_pulsed.set_low().unwrap();
|
output_pulsed.set_low().unwrap();
|
||||||
for _ in 0..10 {
|
for _ in 0..10 {
|
||||||
output_pulsed.set_high().unwrap();
|
output_pulsed.set_high().unwrap();
|
||||||
cortex_m::asm::delay(25_000_000);
|
cortex_m::asm::delay(25_000_000);
|
||||||
}
|
}
|
||||||
output_pulsed.pulse_mode(true, PinState::High);
|
output_pulsed.configure_pulse_mode(true, PinState::High);
|
||||||
rprintln!("Pulsing low 10 times..");
|
rprintln!("Pulsing low 10 times..");
|
||||||
for _ in 0..10 {
|
for _ in 0..10 {
|
||||||
output_pulsed.set_low().unwrap();
|
output_pulsed.set_low().unwrap();
|
||||||
@ -137,15 +137,12 @@ fn main() -> ! {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
TestCase::DelayGpio => {
|
TestCase::DelayGpio => {
|
||||||
let mut out_0 = pinsa
|
let mut out_0 = pinsa.pa0.into_readable_push_pull_output();
|
||||||
.pa0
|
out_0.configure_delay(true, false);
|
||||||
.into_readable_push_pull_output()
|
let mut out_1 = pinsa.pa1.into_readable_push_pull_output();
|
||||||
.delay(true, false);
|
out_1.configure_delay(false, true);
|
||||||
let mut out_1 = pinsa
|
let mut out_2 = pinsa.pa3.into_readable_push_pull_output();
|
||||||
.pa1
|
out_2.configure_delay(true, true);
|
||||||
.into_readable_push_pull_output()
|
|
||||||
.delay(false, true);
|
|
||||||
let mut out_2 = pinsa.pa3.into_readable_push_pull_output().delay(true, true);
|
|
||||||
for _ in 0..20 {
|
for _ in 0..20 {
|
||||||
out_0.toggle().unwrap();
|
out_0.toggle().unwrap();
|
||||||
out_1.toggle().unwrap();
|
out_1.toggle().unwrap();
|
||||||
|
@ -27,8 +27,8 @@ embassy-executor = { version = "0.7", features = [
|
|||||||
"executor-interrupt"
|
"executor-interrupt"
|
||||||
]}
|
]}
|
||||||
|
|
||||||
va108xx-hal = "0.9"
|
va108xx-hal = { version = "0.9", path = "../../va108xx-hal" }
|
||||||
va108xx-embassy = "0.1"
|
va108xx-embassy = { version = "0.1", path = "../../va108xx-embassy" }
|
||||||
|
|
||||||
[features]
|
[features]
|
||||||
default = ["ticks-hz-1_000", "va108xx-embassy/irq-oc30-oc31"]
|
default = ["ticks-hz-1_000", "va108xx-embassy/irq-oc30-oc31"]
|
||||||
|
@ -14,7 +14,9 @@ use embedded_hal_async::digital::Wait;
|
|||||||
use panic_rtt_target as _;
|
use panic_rtt_target as _;
|
||||||
use rtt_target::{rprintln, rtt_init_print};
|
use rtt_target::{rprintln, rtt_init_print};
|
||||||
use va108xx_embassy::embassy;
|
use va108xx_embassy::embassy;
|
||||||
use va108xx_hal::gpio::{on_interrupt_for_asynch_gpio, InputDynPinAsync, InputPinAsync, PinsB};
|
use va108xx_hal::gpio::{
|
||||||
|
on_interrupt_for_async_gpio_for_port, InputDynPinAsync, InputPinAsync, PinsB, Port,
|
||||||
|
};
|
||||||
use va108xx_hal::{
|
use va108xx_hal::{
|
||||||
gpio::{DynPin, PinsA},
|
gpio::{DynPin, PinsA},
|
||||||
pac::{self, interrupt},
|
pac::{self, interrupt},
|
||||||
@ -244,15 +246,16 @@ async fn output_task(
|
|||||||
}
|
}
|
||||||
|
|
||||||
// PB22 to PB23 can be handled by both OC10 and OC11 depending on configuration.
|
// PB22 to PB23 can be handled by both OC10 and OC11 depending on configuration.
|
||||||
|
|
||||||
#[interrupt]
|
#[interrupt]
|
||||||
#[allow(non_snake_case)]
|
#[allow(non_snake_case)]
|
||||||
fn OC10() {
|
fn OC10() {
|
||||||
on_interrupt_for_asynch_gpio();
|
on_interrupt_for_async_gpio_for_port(Port::A);
|
||||||
|
on_interrupt_for_async_gpio_for_port(Port::B);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
// This interrupt only handles PORT B interrupts.
|
||||||
#[interrupt]
|
#[interrupt]
|
||||||
#[allow(non_snake_case)]
|
#[allow(non_snake_case)]
|
||||||
fn OC11() {
|
fn OC11() {
|
||||||
on_interrupt_for_asynch_gpio();
|
on_interrupt_for_async_gpio_for_port(Port::B);
|
||||||
}
|
}
|
||||||
|
@ -20,7 +20,7 @@ embassy-time-queue-utils = "0.1"
|
|||||||
|
|
||||||
once_cell = { version = "1", default-features = false, features = ["critical-section"] }
|
once_cell = { version = "1", default-features = false, features = ["critical-section"] }
|
||||||
|
|
||||||
va108xx-hal = "0.9"
|
va108xx-hal = { version = "0.9", path = "../va108xx-hal" }
|
||||||
|
|
||||||
[target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies]
|
[target.'cfg(all(target_arch = "arm", target_os = "none"))'.dependencies]
|
||||||
portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }
|
portable-atomic = { version = "1", features = ["unsafe-assume-single-core"] }
|
||||||
|
@ -8,6 +8,24 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
|
|||||||
|
|
||||||
## [unreleased]
|
## [unreleased]
|
||||||
|
|
||||||
|
## [v0.10.0]
|
||||||
|
|
||||||
|
## Added
|
||||||
|
|
||||||
|
- A lot of missing `defmt::Format` implementations.
|
||||||
|
|
||||||
|
## Changed
|
||||||
|
|
||||||
|
- Missing GPIO API replacements from `x` to `configure_x`
|
||||||
|
- Renamed GPIO `DynGroup` to `Port`
|
||||||
|
- Rename generic GPIO interrupt handler into `on_interrupt_for_asynch_gpio`
|
||||||
|
into `on_interrupt_for_async_gpio_for_port` which expects a Port argument
|
||||||
|
|
||||||
|
## Fixed
|
||||||
|
|
||||||
|
- Bug in async GPIO interrupt handler where all enabled interrupts, even the ones which might
|
||||||
|
be unrelated to the pin, were disabled.
|
||||||
|
|
||||||
## [v0.9.0]
|
## [v0.9.0]
|
||||||
|
|
||||||
## Fixed
|
## Fixed
|
||||||
|
@ -29,7 +29,7 @@ static_cell = "2"
|
|||||||
thiserror = { version = "2", default-features = false }
|
thiserror = { version = "2", default-features = false }
|
||||||
void = { version = "1", default-features = false }
|
void = { version = "1", default-features = false }
|
||||||
once_cell = {version = "1", default-features = false }
|
once_cell = {version = "1", default-features = false }
|
||||||
va108xx = { version = "0.4", default-features = false, features = ["critical-section"] }
|
va108xx = { version = "0.5", path = "../va108xx", default-features = false, features = ["critical-section", "defmt"] }
|
||||||
embassy-sync = "0.6"
|
embassy-sync = "0.6"
|
||||||
|
|
||||||
defmt = { version = "0.3", optional = true }
|
defmt = { version = "0.3", optional = true }
|
||||||
@ -42,7 +42,7 @@ portable-atomic = "1"
|
|||||||
[features]
|
[features]
|
||||||
default = ["rt"]
|
default = ["rt"]
|
||||||
rt = ["va108xx/rt"]
|
rt = ["va108xx/rt"]
|
||||||
defmt = ["dep:defmt", "fugit/defmt"]
|
defmt = ["dep:defmt", "fugit/defmt", "embedded-hal/defmt-03"]
|
||||||
|
|
||||||
[package.metadata.docs.rs]
|
[package.metadata.docs.rs]
|
||||||
all-features = true
|
all-features = true
|
||||||
|
@ -3,9 +3,9 @@
|
|||||||
//! This module provides the [InputPinAsync] and [InputDynPinAsync] which both implement
|
//! This module provides the [InputPinAsync] and [InputDynPinAsync] which both implement
|
||||||
//! the [embedded_hal_async::digital::Wait] trait. These types allow for asynchronous waiting
|
//! the [embedded_hal_async::digital::Wait] trait. These types allow for asynchronous waiting
|
||||||
//! on GPIO pins. Please note that this module does not specify/declare the interrupt handlers
|
//! on GPIO pins. Please note that this module does not specify/declare the interrupt handlers
|
||||||
//! which must be provided for async support to work. However, it provides one generic
|
//! which must be provided for async support to work. However, it provides the
|
||||||
//! [handler][on_interrupt_for_asynch_gpio] which should be called in ALL user interrupt handlers
|
//! [on_interrupt_for_async_gpio_for_port] generic interrupt handler. This should be called in all
|
||||||
//! which handle GPIO interrupts.
|
//! IRQ functions which handle any GPIO interrupts with the corresponding [Port] argument.
|
||||||
//!
|
//!
|
||||||
//! # Example
|
//! # Example
|
||||||
//!
|
//!
|
||||||
@ -21,62 +21,68 @@ use va108xx::{self as pac, Irqsel, Sysconfig};
|
|||||||
use crate::InterruptConfig;
|
use crate::InterruptConfig;
|
||||||
|
|
||||||
use super::{
|
use super::{
|
||||||
pin, DynGroup, DynPin, DynPinId, InputConfig, InterruptEdge, InvalidPinTypeError, Pin, PinId,
|
pin, DynPin, DynPinId, InputConfig, InterruptEdge, InvalidPinTypeError, Pin, PinId, Port,
|
||||||
NUM_GPIO_PINS, NUM_PINS_PORT_A,
|
NUM_PINS_PORT_A, NUM_PINS_PORT_B,
|
||||||
};
|
};
|
||||||
|
|
||||||
static WAKERS: [AtomicWaker; NUM_GPIO_PINS] = [const { AtomicWaker::new() }; NUM_GPIO_PINS];
|
static WAKERS_FOR_PORT_A: [AtomicWaker; NUM_PINS_PORT_A] =
|
||||||
static EDGE_DETECTION: [AtomicBool; NUM_GPIO_PINS] =
|
[const { AtomicWaker::new() }; NUM_PINS_PORT_A];
|
||||||
[const { AtomicBool::new(false) }; NUM_GPIO_PINS];
|
static WAKERS_FOR_PORT_B: [AtomicWaker; NUM_PINS_PORT_B] =
|
||||||
|
[const { AtomicWaker::new() }; NUM_PINS_PORT_B];
|
||||||
|
static EDGE_DETECTION_PORT_A: [AtomicBool; NUM_PINS_PORT_A] =
|
||||||
|
[const { AtomicBool::new(false) }; NUM_PINS_PORT_A];
|
||||||
|
static EDGE_DETECTION_PORT_B: [AtomicBool; NUM_PINS_PORT_B] =
|
||||||
|
[const { AtomicBool::new(false) }; NUM_PINS_PORT_B];
|
||||||
|
|
||||||
#[inline]
|
/// Generic interrupt handler for GPIO interrupts on a specific port to support async functionalities
|
||||||
fn pin_id_to_offset(dyn_pin_id: DynPinId) -> usize {
|
|
||||||
match dyn_pin_id.group {
|
|
||||||
DynGroup::A => dyn_pin_id.num as usize,
|
|
||||||
DynGroup::B => NUM_PINS_PORT_A + dyn_pin_id.num as usize,
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Generic interrupt handler for GPIO interrupts to support the async functionalities.
|
|
||||||
///
|
///
|
||||||
/// This handler will wake the correspoding wakers for the pins which triggered an interrupt
|
/// This function should be called in all interrupt handlers which handle any GPIO interrupts
|
||||||
/// as well as updating the static edge detection structures. This allows the pin future to
|
/// matching the [Port] argument.
|
||||||
/// complete async operations. The user should call this function in ALL interrupt handlers
|
/// The handler will wake the corresponding wakers for the pins that triggered an interrupts
|
||||||
/// which handle any GPIO interrupts.
|
/// as well as update the static edge detection structures. This allows the pin future tocomplete
|
||||||
#[inline]
|
/// complete async operations.
|
||||||
pub fn on_interrupt_for_asynch_gpio() {
|
pub fn on_interrupt_for_async_gpio_for_port(port: Port) {
|
||||||
let periphs = unsafe { pac::Peripherals::steal() };
|
let periphs = unsafe { pac::Peripherals::steal() };
|
||||||
|
|
||||||
handle_interrupt_for_gpio_and_port(
|
let (irq_enb, edge_status, wakers, edge_detection) = match port {
|
||||||
|
Port::A => (
|
||||||
periphs.porta.irq_enb().read().bits(),
|
periphs.porta.irq_enb().read().bits(),
|
||||||
periphs.porta.edge_status().read().bits(),
|
periphs.porta.edge_status().read().bits(),
|
||||||
0,
|
WAKERS_FOR_PORT_A.as_ref(),
|
||||||
);
|
EDGE_DETECTION_PORT_A.as_ref(),
|
||||||
handle_interrupt_for_gpio_and_port(
|
),
|
||||||
|
Port::B => (
|
||||||
periphs.portb.irq_enb().read().bits(),
|
periphs.portb.irq_enb().read().bits(),
|
||||||
periphs.portb.edge_status().read().bits(),
|
periphs.portb.edge_status().read().bits(),
|
||||||
NUM_PINS_PORT_A,
|
WAKERS_FOR_PORT_B.as_ref(),
|
||||||
);
|
EDGE_DETECTION_PORT_B.as_ref(),
|
||||||
|
),
|
||||||
|
};
|
||||||
|
|
||||||
|
on_interrupt_for_port(irq_enb, edge_status, wakers, edge_detection);
|
||||||
}
|
}
|
||||||
|
|
||||||
// Uses the enabled interrupt register and the persistent edge status to capture all GPIO events.
|
|
||||||
#[inline]
|
#[inline]
|
||||||
fn handle_interrupt_for_gpio_and_port(mut irq_enb: u32, edge_status: u32, pin_base_offset: usize) {
|
fn on_interrupt_for_port(
|
||||||
|
mut irq_enb: u32,
|
||||||
|
edge_status: u32,
|
||||||
|
wakers: &'static [AtomicWaker],
|
||||||
|
edge_detection: &'static [AtomicBool],
|
||||||
|
) {
|
||||||
while irq_enb != 0 {
|
while irq_enb != 0 {
|
||||||
let bit_pos = irq_enb.trailing_zeros() as usize;
|
let bit_pos = irq_enb.trailing_zeros() as usize;
|
||||||
let bit_mask = 1 << bit_pos;
|
let bit_mask = 1 << bit_pos;
|
||||||
|
|
||||||
WAKERS[pin_base_offset + bit_pos].wake();
|
wakers[bit_pos].wake();
|
||||||
|
|
||||||
if edge_status & bit_mask != 0 {
|
if edge_status & bit_mask != 0 {
|
||||||
EDGE_DETECTION[pin_base_offset + bit_pos]
|
edge_detection[bit_pos].store(true, core::sync::atomic::Ordering::Relaxed);
|
||||||
.store(true, core::sync::atomic::Ordering::Relaxed);
|
|
||||||
}
|
|
||||||
|
|
||||||
// Clear the processed bit
|
// Clear the processed bit
|
||||||
irq_enb &= !bit_mask;
|
irq_enb &= !bit_mask;
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
}
|
||||||
|
|
||||||
/// Input pin future which implements the [Future] trait.
|
/// Input pin future which implements the [Future] trait.
|
||||||
///
|
///
|
||||||
@ -85,6 +91,8 @@ fn handle_interrupt_for_gpio_and_port(mut irq_enb: u32, edge_status: u32, pin_ba
|
|||||||
/// struture is granted to allow writing custom async structures.
|
/// struture is granted to allow writing custom async structures.
|
||||||
pub struct InputPinFuture {
|
pub struct InputPinFuture {
|
||||||
pin_id: DynPinId,
|
pin_id: DynPinId,
|
||||||
|
waker_group: &'static [AtomicWaker],
|
||||||
|
edge_detection_group: &'static [AtomicBool],
|
||||||
}
|
}
|
||||||
|
|
||||||
impl InputPinFuture {
|
impl InputPinFuture {
|
||||||
@ -102,6 +110,16 @@ impl InputPinFuture {
|
|||||||
Self::new_with_dyn_pin(pin, irq, edge, &mut periphs.sysconfig, &mut periphs.irqsel)
|
Self::new_with_dyn_pin(pin, irq, edge, &mut periphs.sysconfig, &mut periphs.irqsel)
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#[inline]
|
||||||
|
pub fn pin_group_to_waker_and_edge_detection_group(
|
||||||
|
group: Port,
|
||||||
|
) -> (&'static [AtomicWaker], &'static [AtomicBool]) {
|
||||||
|
match group {
|
||||||
|
Port::A => (WAKERS_FOR_PORT_A.as_ref(), EDGE_DETECTION_PORT_A.as_ref()),
|
||||||
|
Port::B => (WAKERS_FOR_PORT_B.as_ref(), EDGE_DETECTION_PORT_B.as_ref()),
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
pub fn new_with_dyn_pin(
|
pub fn new_with_dyn_pin(
|
||||||
pin: &mut DynPin,
|
pin: &mut DynPin,
|
||||||
irq: pac::Interrupt,
|
irq: pac::Interrupt,
|
||||||
@ -113,16 +131,22 @@ impl InputPinFuture {
|
|||||||
return Err(InvalidPinTypeError(pin.mode()));
|
return Err(InvalidPinTypeError(pin.mode()));
|
||||||
}
|
}
|
||||||
|
|
||||||
EDGE_DETECTION[pin_id_to_offset(pin.id())]
|
let (waker_group, edge_detection_group) =
|
||||||
|
Self::pin_group_to_waker_and_edge_detection_group(pin.id().group);
|
||||||
|
edge_detection_group[pin.id().num as usize]
|
||||||
.store(false, core::sync::atomic::Ordering::Relaxed);
|
.store(false, core::sync::atomic::Ordering::Relaxed);
|
||||||
pin.interrupt_edge(
|
pin.configure_edge_interrupt(
|
||||||
edge,
|
edge,
|
||||||
InterruptConfig::new(irq, true, true),
|
InterruptConfig::new(irq, true, true),
|
||||||
Some(sys_cfg),
|
Some(sys_cfg),
|
||||||
Some(irq_sel),
|
Some(irq_sel),
|
||||||
)
|
)
|
||||||
.unwrap();
|
.unwrap();
|
||||||
Ok(Self { pin_id: pin.id() })
|
Ok(Self {
|
||||||
|
pin_id: pin.id(),
|
||||||
|
waker_group,
|
||||||
|
edge_detection_group,
|
||||||
|
})
|
||||||
}
|
}
|
||||||
|
|
||||||
/// # Safety
|
/// # Safety
|
||||||
@ -146,7 +170,9 @@ impl InputPinFuture {
|
|||||||
sys_cfg: &mut Sysconfig,
|
sys_cfg: &mut Sysconfig,
|
||||||
irq_sel: &mut Irqsel,
|
irq_sel: &mut Irqsel,
|
||||||
) -> Self {
|
) -> Self {
|
||||||
EDGE_DETECTION[pin_id_to_offset(pin.id())]
|
let (waker_group, edge_detection_group) =
|
||||||
|
Self::pin_group_to_waker_and_edge_detection_group(pin.id().group);
|
||||||
|
edge_detection_group[pin.id().num as usize]
|
||||||
.store(false, core::sync::atomic::Ordering::Relaxed);
|
.store(false, core::sync::atomic::Ordering::Relaxed);
|
||||||
pin.configure_edge_interrupt(
|
pin.configure_edge_interrupt(
|
||||||
edge,
|
edge,
|
||||||
@ -154,14 +180,18 @@ impl InputPinFuture {
|
|||||||
Some(sys_cfg),
|
Some(sys_cfg),
|
||||||
Some(irq_sel),
|
Some(irq_sel),
|
||||||
);
|
);
|
||||||
Self { pin_id: pin.id() }
|
Self {
|
||||||
|
pin_id: pin.id(),
|
||||||
|
edge_detection_group,
|
||||||
|
waker_group,
|
||||||
|
}
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
impl Drop for InputPinFuture {
|
impl Drop for InputPinFuture {
|
||||||
fn drop(&mut self) {
|
fn drop(&mut self) {
|
||||||
let periphs = unsafe { pac::Peripherals::steal() };
|
let periphs = unsafe { pac::Peripherals::steal() };
|
||||||
if self.pin_id.group == DynGroup::A {
|
if self.pin_id.group == Port::A {
|
||||||
periphs
|
periphs
|
||||||
.porta
|
.porta
|
||||||
.irq_enb()
|
.irq_enb()
|
||||||
@ -181,9 +211,9 @@ impl Future for InputPinFuture {
|
|||||||
self: core::pin::Pin<&mut Self>,
|
self: core::pin::Pin<&mut Self>,
|
||||||
cx: &mut core::task::Context<'_>,
|
cx: &mut core::task::Context<'_>,
|
||||||
) -> core::task::Poll<Self::Output> {
|
) -> core::task::Poll<Self::Output> {
|
||||||
let idx = pin_id_to_offset(self.pin_id);
|
let idx = self.pin_id.num as usize;
|
||||||
WAKERS[idx].register(cx.waker());
|
self.waker_group[idx].register(cx.waker());
|
||||||
if EDGE_DETECTION[idx].swap(false, core::sync::atomic::Ordering::Relaxed) {
|
if self.edge_detection_group[idx].swap(false, core::sync::atomic::Ordering::Relaxed) {
|
||||||
return core::task::Poll::Ready(());
|
return core::task::Poll::Ready(());
|
||||||
}
|
}
|
||||||
core::task::Poll::Pending
|
core::task::Poll::Pending
|
||||||
@ -200,8 +230,8 @@ impl InputDynPinAsync {
|
|||||||
/// passed as well and is used to route and enable the interrupt.
|
/// passed as well and is used to route and enable the interrupt.
|
||||||
///
|
///
|
||||||
/// Please note that the interrupt handler itself must be provided by the user and the
|
/// Please note that the interrupt handler itself must be provided by the user and the
|
||||||
/// generic [on_interrupt_for_asynch_gpio] function must be called inside that function for
|
/// generic [on_interrupt_for_async_gpio_for_port] function must be called inside that function
|
||||||
/// the asynchronous functionality to work.
|
/// for the asynchronous functionality to work.
|
||||||
pub fn new(pin: DynPin, irq: pac::Interrupt) -> Result<Self, InvalidPinTypeError> {
|
pub fn new(pin: DynPin, irq: pac::Interrupt) -> Result<Self, InvalidPinTypeError> {
|
||||||
if !pin.is_input_pin() {
|
if !pin.is_input_pin() {
|
||||||
return Err(InvalidPinTypeError(pin.mode()));
|
return Err(InvalidPinTypeError(pin.mode()));
|
||||||
@ -335,8 +365,8 @@ impl<I: PinId, C: InputConfig> InputPinAsync<I, C> {
|
|||||||
/// passed as well and is used to route and enable the interrupt.
|
/// passed as well and is used to route and enable the interrupt.
|
||||||
///
|
///
|
||||||
/// Please note that the interrupt handler itself must be provided by the user and the
|
/// Please note that the interrupt handler itself must be provided by the user and the
|
||||||
/// generic [on_interrupt_for_asynch_gpio] function must be called inside that function for
|
/// generic [on_interrupt_for_async_gpio_for_port] function must be called inside that function
|
||||||
/// the asynchronous functionality to work.
|
/// for the asynchronous functionality to work.
|
||||||
pub fn new(pin: Pin<I, pin::Input<C>>, irq: pac::Interrupt) -> Self {
|
pub fn new(pin: Pin<I, pin::Input<C>>, irq: pac::Interrupt) -> Self {
|
||||||
Self { pin, irq }
|
Self { pin, irq }
|
||||||
}
|
}
|
||||||
|
@ -57,9 +57,9 @@
|
|||||||
//! [InvalidPinTypeError].
|
//! [InvalidPinTypeError].
|
||||||
|
|
||||||
use super::{
|
use super::{
|
||||||
pin::{FilterType, InterruptEdge, InterruptLevel, Pin, PinId, PinMode, PinState},
|
pin::{FilterType, Pin, PinId, PinMode},
|
||||||
reg::RegisterInterface,
|
reg::RegisterInterface,
|
||||||
InputDynPinAsync,
|
InputDynPinAsync, InterruptEdge, InterruptLevel, PinState,
|
||||||
};
|
};
|
||||||
use crate::{clock::FilterClkSel, enable_nvic_interrupt, pac, FunSel, InterruptConfig};
|
use crate::{clock::FilterClkSel, enable_nvic_interrupt, pac, FunSel, InterruptConfig};
|
||||||
|
|
||||||
@ -156,19 +156,13 @@ pub const DYN_ALT_FUNC_3: DynPinMode = DynPinMode::Alternate(DynAlternate::Sel3)
|
|||||||
// DynGroup & DynPinId
|
// DynGroup & DynPinId
|
||||||
//==================================================================================================
|
//==================================================================================================
|
||||||
|
|
||||||
/// Value-level `enum` for pin groups
|
pub type DynGroup = super::Port;
|
||||||
#[derive(Debug, PartialEq, Eq, Clone, Copy)]
|
|
||||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
|
||||||
pub enum DynGroup {
|
|
||||||
A,
|
|
||||||
B,
|
|
||||||
}
|
|
||||||
|
|
||||||
/// Value-level `struct` representing pin IDs
|
/// Value-level `struct` representing pin IDs
|
||||||
#[derive(Debug, PartialEq, Eq, Clone, Copy)]
|
#[derive(Debug, PartialEq, Eq, Clone, Copy)]
|
||||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
pub struct DynPinId {
|
pub struct DynPinId {
|
||||||
pub group: DynGroup,
|
pub group: super::Port,
|
||||||
pub num: u8,
|
pub num: u8,
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -181,6 +175,7 @@ pub struct DynPinId {
|
|||||||
/// This `struct` takes ownership of a [`DynPinId`] and provides an API to
|
/// This `struct` takes ownership of a [`DynPinId`] and provides an API to
|
||||||
/// access the corresponding regsiters.
|
/// access the corresponding regsiters.
|
||||||
#[derive(Debug)]
|
#[derive(Debug)]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
pub(crate) struct DynRegisters(DynPinId);
|
pub(crate) struct DynRegisters(DynPinId);
|
||||||
|
|
||||||
// [`DynRegisters`] takes ownership of the [`DynPinId`], and [`DynPin`]
|
// [`DynRegisters`] takes ownership of the [`DynPinId`], and [`DynPin`]
|
||||||
@ -368,12 +363,12 @@ impl DynPin {
|
|||||||
if irq_cfg.route {
|
if irq_cfg.route {
|
||||||
match self.regs.id().group {
|
match self.regs.id().group {
|
||||||
// Set the correct interrupt number in the IRQSEL register
|
// Set the correct interrupt number in the IRQSEL register
|
||||||
DynGroup::A => {
|
super::Port::A => {
|
||||||
irqsel
|
irqsel
|
||||||
.porta0(self.regs.id().num as usize)
|
.porta0(self.regs.id().num as usize)
|
||||||
.write(|w| unsafe { w.bits(irq_cfg.id as u32) });
|
.write(|w| unsafe { w.bits(irq_cfg.id as u32) });
|
||||||
}
|
}
|
||||||
DynGroup::B => {
|
super::Port::B => {
|
||||||
irqsel
|
irqsel
|
||||||
.portb0(self.regs.id().num as usize)
|
.portb0(self.regs.id().num as usize)
|
||||||
.write(|w| unsafe { w.bits(irq_cfg.id as u32) });
|
.write(|w| unsafe { w.bits(irq_cfg.id as u32) });
|
||||||
@ -392,11 +387,15 @@ impl DynPin {
|
|||||||
/// - Delay 2: 2
|
/// - Delay 2: 2
|
||||||
/// - Delay 1 + Delay 2: 3
|
/// - Delay 1 + Delay 2: 3
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn delay(self, delay_1: bool, delay_2: bool) -> Result<Self, InvalidPinTypeError> {
|
pub fn configure_delay(
|
||||||
|
&mut self,
|
||||||
|
delay_1: bool,
|
||||||
|
delay_2: bool,
|
||||||
|
) -> Result<(), InvalidPinTypeError> {
|
||||||
match self.mode {
|
match self.mode {
|
||||||
DynPinMode::Output(_) => {
|
DynPinMode::Output(_) => {
|
||||||
self.regs.delay(delay_1, delay_2);
|
self.regs.configure_delay(delay_1, delay_2);
|
||||||
Ok(self)
|
Ok(())
|
||||||
}
|
}
|
||||||
_ => Err(InvalidPinTypeError(self.mode)),
|
_ => Err(InvalidPinTypeError(self.mode)),
|
||||||
}
|
}
|
||||||
@ -406,7 +405,7 @@ impl DynPin {
|
|||||||
/// When configured for pulse mode, a given pin will set the non-default state for exactly
|
/// When configured for pulse mode, a given pin will set the non-default state for exactly
|
||||||
/// one clock cycle before returning to the configured default state
|
/// one clock cycle before returning to the configured default state
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn pulse_mode(
|
pub fn configure_pulse_mode(
|
||||||
&mut self,
|
&mut self,
|
||||||
enable: bool,
|
enable: bool,
|
||||||
default_state: PinState,
|
default_state: PinState,
|
||||||
@ -422,14 +421,14 @@ impl DynPin {
|
|||||||
|
|
||||||
/// See p.37 and p.38 of the programmers guide for more information.
|
/// See p.37 and p.38 of the programmers guide for more information.
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn filter_type(
|
pub fn configure_filter_type(
|
||||||
&mut self,
|
&mut self,
|
||||||
filter: FilterType,
|
filter: FilterType,
|
||||||
clksel: FilterClkSel,
|
clksel: FilterClkSel,
|
||||||
) -> Result<(), InvalidPinTypeError> {
|
) -> Result<(), InvalidPinTypeError> {
|
||||||
match self.mode {
|
match self.mode {
|
||||||
DynPinMode::Input(_) => {
|
DynPinMode::Input(_) => {
|
||||||
self.regs.filter_type(filter, clksel);
|
self.regs.configure_filter_type(filter, clksel);
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
_ => Err(InvalidPinTypeError(self.mode)),
|
_ => Err(InvalidPinTypeError(self.mode)),
|
||||||
@ -437,7 +436,7 @@ impl DynPin {
|
|||||||
}
|
}
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn interrupt_edge(
|
pub fn configure_edge_interrupt(
|
||||||
&mut self,
|
&mut self,
|
||||||
edge_type: InterruptEdge,
|
edge_type: InterruptEdge,
|
||||||
irq_cfg: InterruptConfig,
|
irq_cfg: InterruptConfig,
|
||||||
@ -446,7 +445,7 @@ impl DynPin {
|
|||||||
) -> Result<(), InvalidPinTypeError> {
|
) -> Result<(), InvalidPinTypeError> {
|
||||||
match self.mode {
|
match self.mode {
|
||||||
DynPinMode::Input(_) | DynPinMode::Output(_) => {
|
DynPinMode::Input(_) | DynPinMode::Output(_) => {
|
||||||
self.regs.interrupt_edge(edge_type);
|
self.regs.configure_edge_interrupt(edge_type);
|
||||||
self.irq_enb(irq_cfg, syscfg, irqsel);
|
self.irq_enb(irq_cfg, syscfg, irqsel);
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
@ -455,7 +454,7 @@ impl DynPin {
|
|||||||
}
|
}
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn interrupt_level(
|
pub fn configure_level_interrupt(
|
||||||
&mut self,
|
&mut self,
|
||||||
level_type: InterruptLevel,
|
level_type: InterruptLevel,
|
||||||
irq_cfg: InterruptConfig,
|
irq_cfg: InterruptConfig,
|
||||||
@ -464,7 +463,7 @@ impl DynPin {
|
|||||||
) -> Result<(), InvalidPinTypeError> {
|
) -> Result<(), InvalidPinTypeError> {
|
||||||
match self.mode {
|
match self.mode {
|
||||||
DynPinMode::Input(_) | DynPinMode::Output(_) => {
|
DynPinMode::Input(_) | DynPinMode::Output(_) => {
|
||||||
self.regs.interrupt_level(level_type);
|
self.regs.configure_level_interrupt(level_type);
|
||||||
self.irq_enb(irq_cfg, syscfg, irqsel);
|
self.irq_enb(irq_cfg, syscfg, irqsel);
|
||||||
Ok(())
|
Ok(())
|
||||||
}
|
}
|
||||||
|
@ -22,14 +22,47 @@
|
|||||||
//!
|
//!
|
||||||
//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs)
|
//! - [Blinky example](https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/branch/main/examples/simple/examples/blinky.rs)
|
||||||
|
|
||||||
|
//==================================================================================================
|
||||||
|
// Errors, Definitions and Constants
|
||||||
|
//==================================================================================================
|
||||||
|
|
||||||
|
pub const NUM_PINS_PORT_A: usize = 32;
|
||||||
|
pub const NUM_PINS_PORT_B: usize = 24;
|
||||||
|
pub const NUM_GPIO_PINS: usize = NUM_PINS_PORT_A + NUM_PINS_PORT_B;
|
||||||
|
|
||||||
#[derive(Debug, PartialEq, Eq, thiserror::Error)]
|
#[derive(Debug, PartialEq, Eq, thiserror::Error)]
|
||||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
#[error("The pin is masked")]
|
#[error("The pin is masked")]
|
||||||
pub struct IsMaskedError;
|
pub struct IsMaskedError;
|
||||||
|
|
||||||
pub const NUM_PINS_PORT_A: usize = 32;
|
#[derive(Debug, PartialEq, Eq, Clone, Copy)]
|
||||||
pub const NUM_PINS_PORT_B: usize = 24;
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
pub const NUM_GPIO_PINS: usize = NUM_PINS_PORT_A + NUM_PINS_PORT_B;
|
pub enum Port {
|
||||||
|
A,
|
||||||
|
B,
|
||||||
|
}
|
||||||
|
|
||||||
|
#[derive(Debug, PartialEq, Eq)]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
|
pub enum InterruptEdge {
|
||||||
|
HighToLow,
|
||||||
|
LowToHigh,
|
||||||
|
BothEdges,
|
||||||
|
}
|
||||||
|
|
||||||
|
#[derive(Debug, PartialEq, Eq)]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
|
pub enum InterruptLevel {
|
||||||
|
Low = 0,
|
||||||
|
High = 1,
|
||||||
|
}
|
||||||
|
|
||||||
|
#[derive(Debug, PartialEq, Eq)]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
|
pub enum PinState {
|
||||||
|
Low = 0,
|
||||||
|
High = 1,
|
||||||
|
}
|
||||||
|
|
||||||
pub mod dynpin;
|
pub mod dynpin;
|
||||||
pub use dynpin::*;
|
pub use dynpin::*;
|
||||||
|
@ -70,9 +70,9 @@
|
|||||||
//! This module implements all of the embedded HAL GPIO traits for each [`Pin`]
|
//! This module implements all of the embedded HAL GPIO traits for each [`Pin`]
|
||||||
//! in the corresponding [`PinMode`]s, namely: [`InputPin`], [`OutputPin`],
|
//! in the corresponding [`PinMode`]s, namely: [`InputPin`], [`OutputPin`],
|
||||||
//! and [`StatefulOutputPin`].
|
//! and [`StatefulOutputPin`].
|
||||||
use super::dynpin::{DynAlternate, DynGroup, DynInput, DynOutput, DynPinId, DynPinMode};
|
use super::dynpin::{DynAlternate, DynInput, DynOutput, DynPinId, DynPinMode};
|
||||||
use super::reg::RegisterInterface;
|
use super::reg::RegisterInterface;
|
||||||
use super::{DynPin, InputPinAsync};
|
use super::{DynPin, InputPinAsync, InterruptEdge, InterruptLevel, PinState, Port};
|
||||||
use crate::{
|
use crate::{
|
||||||
pac::{Irqsel, Porta, Portb, Sysconfig},
|
pac::{Irqsel, Porta, Portb, Sysconfig},
|
||||||
typelevel::Sealed,
|
typelevel::Sealed,
|
||||||
@ -84,29 +84,6 @@ use core::mem::transmute;
|
|||||||
use embedded_hal::digital::{InputPin, OutputPin, StatefulOutputPin};
|
use embedded_hal::digital::{InputPin, OutputPin, StatefulOutputPin};
|
||||||
use paste::paste;
|
use paste::paste;
|
||||||
|
|
||||||
//==================================================================================================
|
|
||||||
// Errors and Definitions
|
|
||||||
//==================================================================================================
|
|
||||||
|
|
||||||
#[derive(Debug, PartialEq, Eq)]
|
|
||||||
pub enum InterruptEdge {
|
|
||||||
HighToLow,
|
|
||||||
LowToHigh,
|
|
||||||
BothEdges,
|
|
||||||
}
|
|
||||||
|
|
||||||
#[derive(Debug, PartialEq, Eq)]
|
|
||||||
pub enum InterruptLevel {
|
|
||||||
Low = 0,
|
|
||||||
High = 1,
|
|
||||||
}
|
|
||||||
|
|
||||||
#[derive(Debug, PartialEq, Eq)]
|
|
||||||
pub enum PinState {
|
|
||||||
Low = 0,
|
|
||||||
High = 1,
|
|
||||||
}
|
|
||||||
|
|
||||||
//==================================================================================================
|
//==================================================================================================
|
||||||
// Input configuration
|
// Input configuration
|
||||||
//==================================================================================================
|
//==================================================================================================
|
||||||
@ -318,7 +295,7 @@ macro_rules! pin_id {
|
|||||||
impl Sealed for $Id {}
|
impl Sealed for $Id {}
|
||||||
impl PinId for $Id {
|
impl PinId for $Id {
|
||||||
const DYN: DynPinId = DynPinId {
|
const DYN: DynPinId = DynPinId {
|
||||||
group: DynGroup::$Group,
|
group: Port::$Group,
|
||||||
num: $NUM,
|
num: $NUM,
|
||||||
};
|
};
|
||||||
}
|
}
|
||||||
@ -353,6 +330,7 @@ impl<I: PinId, M: PinMode> Pin<I, M> {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#[inline]
|
||||||
pub fn id(&self) -> DynPinId {
|
pub fn id(&self) -> DynPinId {
|
||||||
self.inner.id()
|
self.inner.id()
|
||||||
}
|
}
|
||||||
@ -482,11 +460,6 @@ impl<I: PinId, M: PinMode> Pin<I, M> {
|
|||||||
self.inner.regs.write_pin(false)
|
self.inner.regs.write_pin(false)
|
||||||
}
|
}
|
||||||
|
|
||||||
#[inline]
|
|
||||||
pub(crate) fn _toggle_with_toggle_reg(&mut self) {
|
|
||||||
self.inner.regs.toggle();
|
|
||||||
}
|
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
pub(crate) fn _is_low(&self) -> bool {
|
pub(crate) fn _is_low(&self) -> bool {
|
||||||
!self.inner.regs.read_pin()
|
!self.inner.regs.read_pin()
|
||||||
@ -599,7 +572,7 @@ impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
|
|||||||
syscfg: Option<&mut Sysconfig>,
|
syscfg: Option<&mut Sysconfig>,
|
||||||
irqsel: Option<&mut Irqsel>,
|
irqsel: Option<&mut Irqsel>,
|
||||||
) {
|
) {
|
||||||
self.inner.regs.interrupt_edge(edge_type);
|
self.inner.regs.configure_edge_interrupt(edge_type);
|
||||||
self.irq_enb(irq_cfg, syscfg, irqsel);
|
self.irq_enb(irq_cfg, syscfg, irqsel);
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -610,7 +583,7 @@ impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
|
|||||||
syscfg: Option<&mut Sysconfig>,
|
syscfg: Option<&mut Sysconfig>,
|
||||||
irqsel: Option<&mut Irqsel>,
|
irqsel: Option<&mut Irqsel>,
|
||||||
) {
|
) {
|
||||||
self.inner.regs.interrupt_level(level_type);
|
self.inner.regs.configure_level_interrupt(level_type);
|
||||||
self.irq_enb(irq_cfg, syscfg, irqsel);
|
self.irq_enb(irq_cfg, syscfg, irqsel);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -622,23 +595,34 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
|
|||||||
/// - Delay 2: 2
|
/// - Delay 2: 2
|
||||||
/// - Delay 1 + Delay 2: 3
|
/// - Delay 1 + Delay 2: 3
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn delay(self, delay_1: bool, delay_2: bool) -> Self {
|
pub fn configure_delay(&mut self, delay_1: bool, delay_2: bool) {
|
||||||
self.inner.regs.delay(delay_1, delay_2);
|
self.inner.regs.configure_delay(delay_1, delay_2);
|
||||||
self
|
|
||||||
}
|
}
|
||||||
|
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn toggle_with_toggle_reg(&mut self) {
|
pub fn toggle_with_toggle_reg(&mut self) {
|
||||||
self._toggle_with_toggle_reg()
|
self.inner.regs.toggle()
|
||||||
|
}
|
||||||
|
|
||||||
|
#[deprecated(
|
||||||
|
since = "0.9.0",
|
||||||
|
note = "Please use the `configure_pulse_mode` method instead"
|
||||||
|
)]
|
||||||
|
pub fn pulse_mode(&mut self, enable: bool, default_state: PinState) {
|
||||||
|
self.configure_pulse_mode(enable, default_state);
|
||||||
}
|
}
|
||||||
|
|
||||||
/// See p.52 of the programmers guide for more information.
|
/// See p.52 of the programmers guide for more information.
|
||||||
/// When configured for pulse mode, a given pin will set the non-default state for exactly
|
/// When configured for pulse mode, a given pin will set the non-default state for exactly
|
||||||
/// one clock cycle before returning to the configured default state
|
/// one clock cycle before returning to the configured default state
|
||||||
pub fn pulse_mode(&mut self, enable: bool, default_state: PinState) {
|
pub fn configure_pulse_mode(&mut self, enable: bool, default_state: PinState) {
|
||||||
self.inner.regs.pulse_mode(enable, default_state);
|
self.inner.regs.pulse_mode(enable, default_state);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#[deprecated(
|
||||||
|
since = "0.9.0",
|
||||||
|
note = "Please use the `configure_edge_interrupt` method instead"
|
||||||
|
)]
|
||||||
pub fn interrupt_edge(
|
pub fn interrupt_edge(
|
||||||
&mut self,
|
&mut self,
|
||||||
edge_type: InterruptEdge,
|
edge_type: InterruptEdge,
|
||||||
@ -646,18 +630,43 @@ impl<I: PinId, C: OutputConfig> Pin<I, Output<C>> {
|
|||||||
syscfg: Option<&mut Sysconfig>,
|
syscfg: Option<&mut Sysconfig>,
|
||||||
irqsel: Option<&mut Irqsel>,
|
irqsel: Option<&mut Irqsel>,
|
||||||
) {
|
) {
|
||||||
self.inner.regs.interrupt_edge(edge_type);
|
self.inner.regs.configure_edge_interrupt(edge_type);
|
||||||
self.irq_enb(irq_cfg, syscfg, irqsel);
|
self.irq_enb(irq_cfg, syscfg, irqsel);
|
||||||
}
|
}
|
||||||
|
|
||||||
pub fn interrupt_level(
|
pub fn configure_edge_interrupt(
|
||||||
|
&mut self,
|
||||||
|
edge_type: InterruptEdge,
|
||||||
|
irq_cfg: InterruptConfig,
|
||||||
|
syscfg: Option<&mut Sysconfig>,
|
||||||
|
irqsel: Option<&mut Irqsel>,
|
||||||
|
) {
|
||||||
|
self.inner.regs.configure_edge_interrupt(edge_type);
|
||||||
|
self.irq_enb(irq_cfg, syscfg, irqsel);
|
||||||
|
}
|
||||||
|
|
||||||
|
#[deprecated(
|
||||||
|
since = "0.9.0",
|
||||||
|
note = "Please use the `configure_level_interrupt` method instead"
|
||||||
|
)]
|
||||||
|
pub fn level_interrupt(
|
||||||
&mut self,
|
&mut self,
|
||||||
level_type: InterruptLevel,
|
level_type: InterruptLevel,
|
||||||
irq_cfg: InterruptConfig,
|
irq_cfg: InterruptConfig,
|
||||||
syscfg: Option<&mut Sysconfig>,
|
syscfg: Option<&mut Sysconfig>,
|
||||||
irqsel: Option<&mut Irqsel>,
|
irqsel: Option<&mut Irqsel>,
|
||||||
) {
|
) {
|
||||||
self.inner.regs.interrupt_level(level_type);
|
self.configure_level_interrupt(level_type, irq_cfg, syscfg, irqsel);
|
||||||
|
}
|
||||||
|
|
||||||
|
pub fn configure_level_interrupt(
|
||||||
|
&mut self,
|
||||||
|
level_type: InterruptLevel,
|
||||||
|
irq_cfg: InterruptConfig,
|
||||||
|
syscfg: Option<&mut Sysconfig>,
|
||||||
|
irqsel: Option<&mut Irqsel>,
|
||||||
|
) {
|
||||||
|
self.inner.regs.configure_level_interrupt(level_type);
|
||||||
self.irq_enb(irq_cfg, syscfg, irqsel);
|
self.irq_enb(irq_cfg, syscfg, irqsel);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
@ -666,7 +675,7 @@ impl<I: PinId, C: InputConfig> Pin<I, Input<C>> {
|
|||||||
/// See p.37 and p.38 of the programmers guide for more information.
|
/// See p.37 and p.38 of the programmers guide for more information.
|
||||||
#[inline]
|
#[inline]
|
||||||
pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
|
pub fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
|
||||||
self.inner.regs.filter_type(filter, clksel);
|
self.inner.regs.configure_filter_type(filter, clksel);
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
use super::dynpin::{self, DynGroup, DynPinId, DynPinMode};
|
use super::dynpin::{self, DynPinId, DynPinMode};
|
||||||
use super::pin::{FilterType, InterruptEdge, InterruptLevel, PinState};
|
use super::pin::FilterType;
|
||||||
use super::IsMaskedError;
|
use super::{InterruptEdge, InterruptLevel, IsMaskedError, PinState, Port};
|
||||||
use crate::clock::FilterClkSel;
|
use crate::clock::FilterClkSel;
|
||||||
use va108xx::{ioconfig, porta};
|
use va108xx::{ioconfig, porta};
|
||||||
|
|
||||||
@ -146,15 +146,15 @@ pub(super) unsafe trait RegisterInterface {
|
|||||||
#[inline]
|
#[inline]
|
||||||
fn port_reg(&self) -> &PortRegisterBlock {
|
fn port_reg(&self) -> &PortRegisterBlock {
|
||||||
match self.id().group {
|
match self.id().group {
|
||||||
DynGroup::A => unsafe { &(*Self::PORTA) },
|
Port::A => unsafe { &(*Self::PORTA) },
|
||||||
DynGroup::B => unsafe { &(*Self::PORTB) },
|
Port::B => unsafe { &(*Self::PORTB) },
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
fn iocfg_port(&self) -> &PortReg {
|
fn iocfg_port(&self) -> &PortReg {
|
||||||
let ioconfig = unsafe { va108xx::Ioconfig::ptr().as_ref().unwrap() };
|
let ioconfig = unsafe { va108xx::Ioconfig::ptr().as_ref().unwrap() };
|
||||||
match self.id().group {
|
match self.id().group {
|
||||||
DynGroup::A => ioconfig.porta(self.id().num as usize),
|
Port::A => ioconfig.porta(self.id().num as usize),
|
||||||
DynGroup::B => ioconfig.portb0(self.id().num as usize),
|
Port::B => ioconfig.portb0(self.id().num as usize),
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
@ -240,7 +240,7 @@ pub(super) unsafe trait RegisterInterface {
|
|||||||
/// Only useful for interrupt pins. Configure whether to use edges or level as interrupt soure
|
/// Only useful for interrupt pins. Configure whether to use edges or level as interrupt soure
|
||||||
/// When using edge mode, it is possible to generate interrupts on both edges as well
|
/// When using edge mode, it is possible to generate interrupts on both edges as well
|
||||||
#[inline]
|
#[inline]
|
||||||
fn interrupt_edge(&mut self, edge_type: InterruptEdge) {
|
fn configure_edge_interrupt(&mut self, edge_type: InterruptEdge) {
|
||||||
unsafe {
|
unsafe {
|
||||||
self.port_reg()
|
self.port_reg()
|
||||||
.irq_sen()
|
.irq_sen()
|
||||||
@ -267,7 +267,7 @@ pub(super) unsafe trait RegisterInterface {
|
|||||||
|
|
||||||
/// Configure which edge or level type triggers an interrupt
|
/// Configure which edge or level type triggers an interrupt
|
||||||
#[inline]
|
#[inline]
|
||||||
fn interrupt_level(&mut self, level: InterruptLevel) {
|
fn configure_level_interrupt(&mut self, level: InterruptLevel) {
|
||||||
unsafe {
|
unsafe {
|
||||||
self.port_reg()
|
self.port_reg()
|
||||||
.irq_sen()
|
.irq_sen()
|
||||||
@ -286,7 +286,7 @@ pub(super) unsafe trait RegisterInterface {
|
|||||||
|
|
||||||
/// Only useful for input pins
|
/// Only useful for input pins
|
||||||
#[inline]
|
#[inline]
|
||||||
fn filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
|
fn configure_filter_type(&mut self, filter: FilterType, clksel: FilterClkSel) {
|
||||||
self.iocfg_port().modify(|_, w| {
|
self.iocfg_port().modify(|_, w| {
|
||||||
// Safety: Only write to register for this Pin ID
|
// Safety: Only write to register for this Pin ID
|
||||||
unsafe {
|
unsafe {
|
||||||
@ -349,7 +349,7 @@ pub(super) unsafe trait RegisterInterface {
|
|||||||
}
|
}
|
||||||
|
|
||||||
/// Only useful for output pins
|
/// Only useful for output pins
|
||||||
fn delay(&self, delay_1: bool, delay_2: bool) {
|
fn configure_delay(&mut self, delay_1: bool, delay_2: bool) {
|
||||||
let portreg = self.port_reg();
|
let portreg = self.port_reg();
|
||||||
unsafe {
|
unsafe {
|
||||||
if delay_1 {
|
if delay_1 {
|
||||||
|
@ -36,8 +36,6 @@ pub struct InvalidTimingParamsError;
|
|||||||
#[derive(Debug, PartialEq, Eq, thiserror::Error)]
|
#[derive(Debug, PartialEq, Eq, thiserror::Error)]
|
||||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
pub enum Error {
|
pub enum Error {
|
||||||
//#[error("Invalid timing parameters")]
|
|
||||||
//InvalidTimingParams,
|
|
||||||
#[error("arbitration lost")]
|
#[error("arbitration lost")]
|
||||||
ArbitrationLost,
|
ArbitrationLost,
|
||||||
#[error("nack address")]
|
#[error("nack address")]
|
||||||
@ -82,6 +80,7 @@ impl embedded_hal::i2c::Error for Error {
|
|||||||
}
|
}
|
||||||
|
|
||||||
#[derive(Debug, PartialEq, Copy, Clone)]
|
#[derive(Debug, PartialEq, Copy, Clone)]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
enum I2cCmd {
|
enum I2cCmd {
|
||||||
Start = 0b00,
|
Start = 0b00,
|
||||||
Stop = 0b10,
|
Stop = 0b10,
|
||||||
@ -252,6 +251,8 @@ impl Default for MasterConfig {
|
|||||||
|
|
||||||
impl Sealed for MasterConfig {}
|
impl Sealed for MasterConfig {}
|
||||||
|
|
||||||
|
#[derive(Debug)]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
pub struct SlaveConfig {
|
pub struct SlaveConfig {
|
||||||
pub tx_fe_mode: FifoEmptyMode,
|
pub tx_fe_mode: FifoEmptyMode,
|
||||||
pub rx_fe_mode: FifoEmptyMode,
|
pub rx_fe_mode: FifoEmptyMode,
|
||||||
@ -455,13 +456,6 @@ impl<I2c: Instance> I2cBase<I2c> {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
// Unique mode to use the loopback functionality
|
|
||||||
// pub struct I2cLoopback<I2C> {
|
|
||||||
// i2c_base: I2cBase<I2C>,
|
|
||||||
// master_cfg: MasterConfig,
|
|
||||||
// slave_cfg: SlaveConfig,
|
|
||||||
// }
|
|
||||||
|
|
||||||
//==================================================================================================
|
//==================================================================================================
|
||||||
// I2C Master
|
// I2C Master
|
||||||
//==================================================================================================
|
//==================================================================================================
|
||||||
@ -673,275 +667,6 @@ impl<I2c: Instance, Addr> I2cMaster<I2c, Addr> {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
/*
|
|
||||||
macro_rules! i2c_master {
|
|
||||||
($($I2CX:path: ($i2cx:ident, $clk_enb:path),)+) => {
|
|
||||||
$(
|
|
||||||
impl<ADDR> I2cMaster<$I2CX, ADDR> {
|
|
||||||
pub fn $i2cx(
|
|
||||||
i2c: $I2CX,
|
|
||||||
cfg: MasterConfig,
|
|
||||||
sys_clk: impl Into<Hertz> + Copy,
|
|
||||||
speed_mode: I2cSpeed,
|
|
||||||
sys_cfg: Option<&mut pac::Sysconfig>,
|
|
||||||
) -> Self {
|
|
||||||
I2cMaster {
|
|
||||||
i2c_base: I2cBase::$i2cx(
|
|
||||||
i2c,
|
|
||||||
sys_clk,
|
|
||||||
speed_mode,
|
|
||||||
Some(&cfg),
|
|
||||||
None,
|
|
||||||
sys_cfg
|
|
||||||
),
|
|
||||||
_addr: PhantomData,
|
|
||||||
}
|
|
||||||
.enable_master()
|
|
||||||
}
|
|
||||||
|
|
||||||
#[inline]
|
|
||||||
pub fn cancel_transfer(&self) {
|
|
||||||
self.i2c_base
|
|
||||||
.i2c
|
|
||||||
.cmd()
|
|
||||||
.write(|w| unsafe { w.bits(I2cCmd::Cancel as u32) });
|
|
||||||
}
|
|
||||||
|
|
||||||
#[inline]
|
|
||||||
pub fn clear_tx_fifo(&self) {
|
|
||||||
self.i2c_base.i2c.fifo_clr().write(|w| w.txfifo().set_bit());
|
|
||||||
}
|
|
||||||
|
|
||||||
#[inline]
|
|
||||||
pub fn clear_rx_fifo(&self) {
|
|
||||||
self.i2c_base.i2c.fifo_clr().write(|w| w.rxfifo().set_bit());
|
|
||||||
}
|
|
||||||
|
|
||||||
#[inline]
|
|
||||||
pub fn enable_master(self) -> Self {
|
|
||||||
self.i2c_base.i2c.ctrl().modify(|_, w| w.enable().set_bit());
|
|
||||||
self
|
|
||||||
}
|
|
||||||
|
|
||||||
#[inline]
|
|
||||||
pub fn disable_master(self) -> Self {
|
|
||||||
self.i2c_base.i2c.ctrl().modify(|_, w| w.enable().clear_bit());
|
|
||||||
self
|
|
||||||
}
|
|
||||||
|
|
||||||
#[inline(always)]
|
|
||||||
fn load_fifo(&self, word: u8) {
|
|
||||||
self.i2c_base
|
|
||||||
.i2c
|
|
||||||
.data()
|
|
||||||
.write(|w| unsafe { w.bits(word as u32) });
|
|
||||||
}
|
|
||||||
|
|
||||||
#[inline(always)]
|
|
||||||
fn read_fifo(&self) -> u8 {
|
|
||||||
self.i2c_base.i2c.data().read().bits() as u8
|
|
||||||
}
|
|
||||||
|
|
||||||
fn error_handler_write(&mut self, init_cmd: &I2cCmd) {
|
|
||||||
self.clear_tx_fifo();
|
|
||||||
if *init_cmd == I2cCmd::Start {
|
|
||||||
self.i2c_base.stop_cmd()
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
fn write_base(
|
|
||||||
&mut self,
|
|
||||||
addr: I2cAddress,
|
|
||||||
init_cmd: I2cCmd,
|
|
||||||
bytes: impl IntoIterator<Item = u8>,
|
|
||||||
) -> Result<(), Error> {
|
|
||||||
let mut iter = bytes.into_iter();
|
|
||||||
// Load address
|
|
||||||
let (addr, addr_mode_bit) = I2cBase::<$I2CX>::unwrap_addr(addr);
|
|
||||||
self.i2c_base.i2c.address().write(|w| unsafe {
|
|
||||||
w.bits(I2cDirection::Send as u32 | (addr << 1) as u32 | addr_mode_bit)
|
|
||||||
});
|
|
||||||
|
|
||||||
self.i2c_base
|
|
||||||
.i2c
|
|
||||||
.cmd()
|
|
||||||
.write(|w| unsafe { w.bits(init_cmd as u32) });
|
|
||||||
let mut load_if_next_available = || {
|
|
||||||
if let Some(next_byte) = iter.next() {
|
|
||||||
self.load_fifo(next_byte);
|
|
||||||
}
|
|
||||||
};
|
|
||||||
loop {
|
|
||||||
let status_reader = self.i2c_base.i2c.status().read();
|
|
||||||
if status_reader.arblost().bit_is_set() {
|
|
||||||
self.error_handler_write(&init_cmd);
|
|
||||||
return Err(Error::ArbitrationLost);
|
|
||||||
} else if status_reader.nackaddr().bit_is_set() {
|
|
||||||
self.error_handler_write(&init_cmd);
|
|
||||||
return Err(Error::NackAddr);
|
|
||||||
} else if status_reader.nackdata().bit_is_set() {
|
|
||||||
self.error_handler_write(&init_cmd);
|
|
||||||
return Err(Error::NackData);
|
|
||||||
} else if status_reader.idle().bit_is_set() {
|
|
||||||
return Ok(());
|
|
||||||
} else {
|
|
||||||
while !status_reader.txnfull().bit_is_set() {
|
|
||||||
load_if_next_available();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
fn write_from_buffer(
|
|
||||||
&mut self,
|
|
||||||
init_cmd: I2cCmd,
|
|
||||||
addr: I2cAddress,
|
|
||||||
output: &[u8],
|
|
||||||
) -> Result<(), Error> {
|
|
||||||
let len = output.len();
|
|
||||||
// It should theoretically possible to transfer larger data sizes by tracking
|
|
||||||
// the number of sent words and setting it to 0x7fe as soon as only that many
|
|
||||||
// bytes are remaining. However, large transfer like this are not common. This
|
|
||||||
// feature will therefore not be supported for now.
|
|
||||||
if len > 0x7fe {
|
|
||||||
return Err(Error::DataTooLarge);
|
|
||||||
}
|
|
||||||
// Load number of words
|
|
||||||
self.i2c_base
|
|
||||||
.i2c
|
|
||||||
.words()
|
|
||||||
.write(|w| unsafe { w.bits(len as u32) });
|
|
||||||
let mut bytes = output.iter();
|
|
||||||
// FIFO has a depth of 16. We load slightly above the trigger level
|
|
||||||
// but not all of it because the transaction might fail immediately
|
|
||||||
const FILL_DEPTH: usize = 12;
|
|
||||||
|
|
||||||
// load the FIFO
|
|
||||||
for _ in 0..core::cmp::min(FILL_DEPTH, len) {
|
|
||||||
self.load_fifo(*bytes.next().unwrap());
|
|
||||||
}
|
|
||||||
|
|
||||||
self.write_base(addr, init_cmd, output.iter().cloned())
|
|
||||||
}
|
|
||||||
|
|
||||||
fn read_internal(&mut self, addr: I2cAddress, buffer: &mut [u8]) -> Result<(), Error> {
|
|
||||||
let len = buffer.len();
|
|
||||||
// It should theoretically possible to transfer larger data sizes by tracking
|
|
||||||
// the number of sent words and setting it to 0x7fe as soon as only that many
|
|
||||||
// bytes are remaining. However, large transfer like this are not common. This
|
|
||||||
// feature will therefore not be supported for now.
|
|
||||||
if len > 0x7fe {
|
|
||||||
return Err(Error::DataTooLarge);
|
|
||||||
}
|
|
||||||
// Clear the receive FIFO
|
|
||||||
self.clear_rx_fifo();
|
|
||||||
|
|
||||||
// Load number of words
|
|
||||||
self.i2c_base
|
|
||||||
.i2c
|
|
||||||
.words()
|
|
||||||
.write(|w| unsafe { w.bits(len as u32) });
|
|
||||||
let (addr, addr_mode_bit) = match addr {
|
|
||||||
I2cAddress::Regular(addr) => (addr as u16, 0 << 15),
|
|
||||||
I2cAddress::TenBit(addr) => (addr, 1 << 15),
|
|
||||||
};
|
|
||||||
// Load address
|
|
||||||
self.i2c_base.i2c.address().write(|w| unsafe {
|
|
||||||
w.bits(I2cDirection::Read as u32 | (addr << 1) as u32 | addr_mode_bit)
|
|
||||||
});
|
|
||||||
|
|
||||||
let mut buf_iter = buffer.iter_mut();
|
|
||||||
let mut read_bytes = 0;
|
|
||||||
// Start receive transfer
|
|
||||||
self.i2c_base
|
|
||||||
.i2c
|
|
||||||
.cmd()
|
|
||||||
.write(|w| unsafe { w.bits(I2cCmd::StartWithStop as u32) });
|
|
||||||
let mut read_if_next_available = || {
|
|
||||||
if let Some(next_byte) = buf_iter.next() {
|
|
||||||
*next_byte = self.read_fifo();
|
|
||||||
}
|
|
||||||
};
|
|
||||||
loop {
|
|
||||||
let status_reader = self.i2c_base.i2c.status().read();
|
|
||||||
if status_reader.arblost().bit_is_set() {
|
|
||||||
self.clear_rx_fifo();
|
|
||||||
return Err(Error::ArbitrationLost);
|
|
||||||
} else if status_reader.nackaddr().bit_is_set() {
|
|
||||||
self.clear_rx_fifo();
|
|
||||||
return Err(Error::NackAddr);
|
|
||||||
} else if status_reader.idle().bit_is_set() {
|
|
||||||
if read_bytes != len {
|
|
||||||
return Err(Error::InsufficientDataReceived);
|
|
||||||
}
|
|
||||||
return Ok(());
|
|
||||||
} else if status_reader.rxnempty().bit_is_set() {
|
|
||||||
read_if_next_available();
|
|
||||||
read_bytes += 1;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
//======================================================================================
|
|
||||||
// Embedded HAL I2C implementations
|
|
||||||
//======================================================================================
|
|
||||||
|
|
||||||
impl embedded_hal::i2c::ErrorType for I2cMaster<$I2CX, SevenBitAddress> {
|
|
||||||
type Error = Error;
|
|
||||||
}
|
|
||||||
impl embedded_hal::i2c::I2c for I2cMaster<$I2CX, SevenBitAddress> {
|
|
||||||
fn transaction(
|
|
||||||
&mut self,
|
|
||||||
address: SevenBitAddress,
|
|
||||||
operations: &mut [Operation<'_>],
|
|
||||||
) -> Result<(), Self::Error> {
|
|
||||||
for operation in operations {
|
|
||||||
match operation {
|
|
||||||
Operation::Read(buf) => self.read_internal(I2cAddress::Regular(address), buf)?,
|
|
||||||
Operation::Write(buf) => self.write_from_buffer(
|
|
||||||
I2cCmd::StartWithStop,
|
|
||||||
I2cAddress::Regular(address),
|
|
||||||
buf,
|
|
||||||
)?,
|
|
||||||
}
|
|
||||||
}
|
|
||||||
Ok(())
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
impl embedded_hal::i2c::ErrorType for I2cMaster<$I2CX, TenBitAddress> {
|
|
||||||
type Error = Error;
|
|
||||||
}
|
|
||||||
impl embedded_hal::i2c::I2c<TenBitAddress> for I2cMaster<$I2CX, TenBitAddress> {
|
|
||||||
fn transaction(
|
|
||||||
&mut self,
|
|
||||||
address: TenBitAddress,
|
|
||||||
operations: &mut [Operation<'_>],
|
|
||||||
) -> Result<(), Self::Error> {
|
|
||||||
for operation in operations {
|
|
||||||
match operation {
|
|
||||||
Operation::Read(buf) => self.read_internal(I2cAddress::TenBit(address), buf)?,
|
|
||||||
Operation::Write(buf) => self.write_from_buffer(
|
|
||||||
I2cCmd::StartWithStop,
|
|
||||||
I2cAddress::TenBit(address),
|
|
||||||
buf,
|
|
||||||
)?,
|
|
||||||
}
|
|
||||||
}
|
|
||||||
Ok(())
|
|
||||||
}
|
|
||||||
}
|
|
||||||
)+
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
i2c_master!(
|
|
||||||
pac::I2ca: (i2ca, PeripheralClocks::I2c0),
|
|
||||||
pac::I2cb: (i2cb, PeripheralClocks::I2c1),
|
|
||||||
);
|
|
||||||
*/
|
|
||||||
|
|
||||||
//======================================================================================
|
//======================================================================================
|
||||||
// Embedded HAL I2C implementations
|
// Embedded HAL I2C implementations
|
||||||
//======================================================================================
|
//======================================================================================
|
||||||
|
@ -31,7 +31,7 @@ pub enum PortSel {
|
|||||||
PortB,
|
PortB,
|
||||||
}
|
}
|
||||||
|
|
||||||
#[derive(Copy, Clone, PartialEq, Eq)]
|
#[derive(Debug, Copy, Clone, PartialEq, Eq)]
|
||||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
pub enum PeripheralSelect {
|
pub enum PeripheralSelect {
|
||||||
PortA = 0,
|
PortA = 0,
|
||||||
@ -54,6 +54,7 @@ pub enum PeripheralSelect {
|
|||||||
/// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might want to
|
/// Cortex-M0 NVIC. Both are generally necessary for IRQs to work, but the user might want to
|
||||||
/// perform those steps themselves.
|
/// perform those steps themselves.
|
||||||
#[derive(Debug, PartialEq, Eq, Clone, Copy)]
|
#[derive(Debug, PartialEq, Eq, Clone, Copy)]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
pub struct InterruptConfig {
|
pub struct InterruptConfig {
|
||||||
/// Interrupt target vector. Should always be set, might be required for disabling IRQs
|
/// Interrupt target vector. Should always be set, might be required for disabling IRQs
|
||||||
pub id: pac::Interrupt,
|
pub id: pac::Interrupt,
|
||||||
|
@ -33,6 +33,7 @@ use embedded_hal::spi::{Mode, MODE_0};
|
|||||||
const FILL_DEPTH: usize = 12;
|
const FILL_DEPTH: usize = 12;
|
||||||
|
|
||||||
pub const BMSTART_BMSTOP_MASK: u32 = 1 << 31;
|
pub const BMSTART_BMSTOP_MASK: u32 = 1 << 31;
|
||||||
|
pub const BMSKIPDATA_MASK: u32 = 1 << 30;
|
||||||
|
|
||||||
pub const DEFAULT_CLK_DIV: u16 = 2;
|
pub const DEFAULT_CLK_DIV: u16 = 2;
|
||||||
|
|
||||||
@ -288,6 +289,7 @@ pub trait TransferConfigProvider {
|
|||||||
/// This struct contains all configuration parameter which are transfer specific
|
/// This struct contains all configuration parameter which are transfer specific
|
||||||
/// and might change for transfers to different SPI slaves
|
/// and might change for transfers to different SPI slaves
|
||||||
#[derive(Copy, Clone, Debug)]
|
#[derive(Copy, Clone, Debug)]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
pub struct TransferConfigWithHwcs<HwCs> {
|
pub struct TransferConfigWithHwcs<HwCs> {
|
||||||
pub hw_cs: Option<HwCs>,
|
pub hw_cs: Option<HwCs>,
|
||||||
pub cfg: TransferConfig,
|
pub cfg: TransferConfig,
|
||||||
@ -296,6 +298,7 @@ pub struct TransferConfigWithHwcs<HwCs> {
|
|||||||
/// Type erased variant of the transfer configuration. This is required to avoid generics in
|
/// Type erased variant of the transfer configuration. This is required to avoid generics in
|
||||||
/// the SPI constructor.
|
/// the SPI constructor.
|
||||||
#[derive(Copy, Clone, Debug)]
|
#[derive(Copy, Clone, Debug)]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
pub struct TransferConfig {
|
pub struct TransferConfig {
|
||||||
pub clk_cfg: Option<SpiClkConfig>,
|
pub clk_cfg: Option<SpiClkConfig>,
|
||||||
pub mode: Option<Mode>,
|
pub mode: Option<Mode>,
|
||||||
@ -383,6 +386,8 @@ impl<HwCs: HwCsProvider> TransferConfigProvider for TransferConfigWithHwcs<HwCs>
|
|||||||
}
|
}
|
||||||
|
|
||||||
/// Configuration options for the whole SPI bus. See Programmer Guide p.92 for more details
|
/// Configuration options for the whole SPI bus. See Programmer Guide p.92 for more details
|
||||||
|
#[derive(Debug)]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
pub struct SpiConfig {
|
pub struct SpiConfig {
|
||||||
clk: SpiClkConfig,
|
clk: SpiClkConfig,
|
||||||
// SPI mode configuration
|
// SPI mode configuration
|
||||||
@ -532,6 +537,7 @@ pub struct Spi<SpiInstance, Pins, Word = u8> {
|
|||||||
pins: Pins,
|
pins: Pins,
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#[inline(always)]
|
||||||
pub fn mode_to_cpo_cph_bit(mode: embedded_hal::spi::Mode) -> (bool, bool) {
|
pub fn mode_to_cpo_cph_bit(mode: embedded_hal::spi::Mode) -> (bool, bool) {
|
||||||
match mode {
|
match mode {
|
||||||
embedded_hal::spi::MODE_0 => (false, false),
|
embedded_hal::spi::MODE_0 => (false, false),
|
||||||
@ -575,6 +581,7 @@ impl SpiClkConfig {
|
|||||||
}
|
}
|
||||||
|
|
||||||
#[derive(Debug, thiserror::Error)]
|
#[derive(Debug, thiserror::Error)]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
pub enum SpiClkConfigError {
|
pub enum SpiClkConfigError {
|
||||||
#[error("division by zero")]
|
#[error("division by zero")]
|
||||||
DivIsZero,
|
DivIsZero,
|
||||||
|
@ -8,6 +8,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
|
|||||||
|
|
||||||
## [unreleased]
|
## [unreleased]
|
||||||
|
|
||||||
|
## [v0.5.0] 2025-02-14
|
||||||
|
|
||||||
|
- Re-generated PAC with `svd2rust` v0.35.0 and added optional `defmt` and `Debug` implementations
|
||||||
|
|
||||||
## [v0.4.0] 2025-02-12
|
## [v0.4.0] 2025-02-12
|
||||||
|
|
||||||
- Re-generated PAC with `svd2rust` v0.35.0
|
- Re-generated PAC with `svd2rust` v0.35.0
|
||||||
|
@ -1,6 +1,6 @@
|
|||||||
[package]
|
[package]
|
||||||
name = "va108xx"
|
name = "va108xx"
|
||||||
version = "0.4.0"
|
version = "0.5.0"
|
||||||
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
|
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
|
||||||
edition = "2021"
|
edition = "2021"
|
||||||
description = "PAC for the Vorago VA108xx family of microcontrollers"
|
description = "PAC for the Vorago VA108xx family of microcontrollers"
|
||||||
@ -13,6 +13,7 @@ categories = ["embedded", "no-std", "hardware-support"]
|
|||||||
[dependencies]
|
[dependencies]
|
||||||
cortex-m = "0.7"
|
cortex-m = "0.7"
|
||||||
vcell = "0.1.3"
|
vcell = "0.1.3"
|
||||||
|
defmt = { version = "0.3", optional = true }
|
||||||
critical-section = { version = "1", optional = true }
|
critical-section = { version = "1", optional = true }
|
||||||
|
|
||||||
[dependencies.cortex-m-rt]
|
[dependencies.cortex-m-rt]
|
||||||
@ -21,6 +22,8 @@ version = ">=0.6.15,<0.8"
|
|||||||
|
|
||||||
[features]
|
[features]
|
||||||
rt = ["cortex-m-rt/device"]
|
rt = ["cortex-m-rt/device"]
|
||||||
|
# Adds Debug implementation
|
||||||
|
debug = []
|
||||||
|
|
||||||
[package.metadata.docs.rs]
|
[package.metadata.docs.rs]
|
||||||
all-features = true
|
all-features = true
|
||||||
|
@ -26,6 +26,12 @@ The `rt` feature is optional and recommended. It brings in support for `cortex-m
|
|||||||
For full details on the autgenerated API, please see the
|
For full details on the autgenerated API, please see the
|
||||||
[svd2rust documentation](https://docs.rs/svd2rust/latest/svd2rust/#peripheral-api).
|
[svd2rust documentation](https://docs.rs/svd2rust/latest/svd2rust/#peripheral-api).
|
||||||
|
|
||||||
|
## Optional Features
|
||||||
|
|
||||||
|
- [`defmt`](https://defmt.ferrous-systems.com/): Add support for `defmt` by adding the
|
||||||
|
[`defmt::Format`](https://defmt.ferrous-systems.com/format) derive on many types.
|
||||||
|
- `debug`: Add `Debug` derives for various structures
|
||||||
|
|
||||||
## Regenerating the PAC
|
## Regenerating the PAC
|
||||||
|
|
||||||
If you want to re-generate the PAC, for example if the register file `va416xx.svd` changes
|
If you want to re-generate the PAC, for example if the register file `va416xx.svd` changes
|
||||||
|
@ -30,7 +30,7 @@ fi
|
|||||||
|
|
||||||
svdtools patch svd/va108xx-patch.yml
|
svdtools patch svd/va108xx-patch.yml
|
||||||
# See https://github.com/rust-embedded/svd2rust/issues/830 for required re-export.
|
# See https://github.com/rust-embedded/svd2rust/issues/830 for required re-export.
|
||||||
${svd2rust_bin} --reexport-interrupt -i svd/va108xx.svd.patched
|
${svd2rust_bin} --reexport-interrupt --impl-defmt defmt --impl-debug-feature debug -i svd/va108xx.svd.patched
|
||||||
|
|
||||||
result=$?
|
result=$?
|
||||||
if [ $result -ne 0 ]; then
|
if [ $result -ne 0 ]; then
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<AddressSpec>;
|
pub type R = crate::R<AddressSpec>;
|
||||||
#[doc = "Register `ADDRESS` writer"]
|
#[doc = "Register `ADDRESS` writer"]
|
||||||
pub type W = crate::W<AddressSpec>;
|
pub type W = crate::W<AddressSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<ClktolimitSpec>;
|
pub type R = crate::R<ClktolimitSpec>;
|
||||||
#[doc = "Register `CLKTOLIMIT` writer"]
|
#[doc = "Register `CLKTOLIMIT` writer"]
|
||||||
pub type W = crate::W<ClktolimitSpec>;
|
pub type W = crate::W<ClktolimitSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<CmdSpec>;
|
pub type R = crate::R<CmdSpec>;
|
||||||
#[doc = "Register `CMD` writer"]
|
#[doc = "Register `CMD` writer"]
|
||||||
pub type W = crate::W<CmdSpec>;
|
pub type W = crate::W<CmdSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<DataSpec>;
|
pub type R = crate::R<DataSpec>;
|
||||||
#[doc = "Register `DATA` writer"]
|
#[doc = "Register `DATA` writer"]
|
||||||
pub type W = crate::W<DataSpec>;
|
pub type W = crate::W<DataSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `PERID` reader"]
|
#[doc = "Register `PERID` reader"]
|
||||||
pub type R = crate::R<PeridSpec>;
|
pub type R = crate::R<PeridSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `RXCOUNT` reader"]
|
#[doc = "Register `RXCOUNT` reader"]
|
||||||
pub type R = crate::R<RxcountSpec>;
|
pub type R = crate::R<RxcountSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<RxfifoirqtrgSpec>;
|
pub type R = crate::R<RxfifoirqtrgSpec>;
|
||||||
#[doc = "Register `RXFIFOIRQTRG` writer"]
|
#[doc = "Register `RXFIFOIRQTRG` writer"]
|
||||||
pub type W = crate::W<RxfifoirqtrgSpec>;
|
pub type W = crate::W<RxfifoirqtrgSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<S0AddressSpec>;
|
pub type R = crate::R<S0AddressSpec>;
|
||||||
#[doc = "Register `S0_ADDRESS` writer"]
|
#[doc = "Register `S0_ADDRESS` writer"]
|
||||||
pub type W = crate::W<S0AddressSpec>;
|
pub type W = crate::W<S0AddressSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<S0AddressbSpec>;
|
pub type R = crate::R<S0AddressbSpec>;
|
||||||
#[doc = "Register `S0_ADDRESSB` writer"]
|
#[doc = "Register `S0_ADDRESSB` writer"]
|
||||||
pub type W = crate::W<S0AddressbSpec>;
|
pub type W = crate::W<S0AddressbSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<S0AddressmaskSpec>;
|
pub type R = crate::R<S0AddressmaskSpec>;
|
||||||
#[doc = "Register `S0_ADDRESSMASK` writer"]
|
#[doc = "Register `S0_ADDRESSMASK` writer"]
|
||||||
pub type W = crate::W<S0AddressmaskSpec>;
|
pub type W = crate::W<S0AddressmaskSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<S0AddressmaskbSpec>;
|
pub type R = crate::R<S0AddressmaskbSpec>;
|
||||||
#[doc = "Register `S0_ADDRESSMASKB` writer"]
|
#[doc = "Register `S0_ADDRESSMASKB` writer"]
|
||||||
pub type W = crate::W<S0AddressmaskbSpec>;
|
pub type W = crate::W<S0AddressmaskbSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<S0DataSpec>;
|
pub type R = crate::R<S0DataSpec>;
|
||||||
#[doc = "Register `S0_DATA` writer"]
|
#[doc = "Register `S0_DATA` writer"]
|
||||||
pub type W = crate::W<S0DataSpec>;
|
pub type W = crate::W<S0DataSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `S0_LASTADDRESS` reader"]
|
#[doc = "Register `S0_LASTADDRESS` reader"]
|
||||||
pub type R = crate::R<S0LastaddressSpec>;
|
pub type R = crate::R<S0LastaddressSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<S0MaxwordsSpec>;
|
pub type R = crate::R<S0MaxwordsSpec>;
|
||||||
#[doc = "Register `S0_MAXWORDS` writer"]
|
#[doc = "Register `S0_MAXWORDS` writer"]
|
||||||
pub type W = crate::W<S0MaxwordsSpec>;
|
pub type W = crate::W<S0MaxwordsSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `S0_RXCOUNT` reader"]
|
#[doc = "Register `S0_RXCOUNT` reader"]
|
||||||
pub type R = crate::R<S0RxcountSpec>;
|
pub type R = crate::R<S0RxcountSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<S0RxfifoirqtrgSpec>;
|
pub type R = crate::R<S0RxfifoirqtrgSpec>;
|
||||||
#[doc = "Register `S0_RXFIFOIRQTRG` writer"]
|
#[doc = "Register `S0_RXFIFOIRQTRG` writer"]
|
||||||
pub type W = crate::W<S0RxfifoirqtrgSpec>;
|
pub type W = crate::W<S0RxfifoirqtrgSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `S0_STATE` reader"]
|
#[doc = "Register `S0_STATE` reader"]
|
||||||
pub type R = crate::R<S0StateSpec>;
|
pub type R = crate::R<S0StateSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `S0_TXCOUNT` reader"]
|
#[doc = "Register `S0_TXCOUNT` reader"]
|
||||||
pub type R = crate::R<S0TxcountSpec>;
|
pub type R = crate::R<S0TxcountSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<S0TxfifoirqtrgSpec>;
|
pub type R = crate::R<S0TxfifoirqtrgSpec>;
|
||||||
#[doc = "Register `S0_TXFIFOIRQTRG` writer"]
|
#[doc = "Register `S0_TXFIFOIRQTRG` writer"]
|
||||||
pub type W = crate::W<S0TxfifoirqtrgSpec>;
|
pub type W = crate::W<S0TxfifoirqtrgSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `STATE` reader"]
|
#[doc = "Register `STATE` reader"]
|
||||||
pub type R = crate::R<StateSpec>;
|
pub type R = crate::R<StateSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<TmconfigSpec>;
|
pub type R = crate::R<TmconfigSpec>;
|
||||||
#[doc = "Register `TMCONFIG` writer"]
|
#[doc = "Register `TMCONFIG` writer"]
|
||||||
pub type W = crate::W<TmconfigSpec>;
|
pub type W = crate::W<TmconfigSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `TXCOUNT` reader"]
|
#[doc = "Register `TXCOUNT` reader"]
|
||||||
pub type R = crate::R<TxcountSpec>;
|
pub type R = crate::R<TxcountSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<TxfifoirqtrgSpec>;
|
pub type R = crate::R<TxfifoirqtrgSpec>;
|
||||||
#[doc = "Register `TXFIFOIRQTRG` writer"]
|
#[doc = "Register `TXFIFOIRQTRG` writer"]
|
||||||
pub type W = crate::W<TxfifoirqtrgSpec>;
|
pub type W = crate::W<TxfifoirqtrgSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<WordsSpec>;
|
pub type R = crate::R<WordsSpec>;
|
||||||
#[doc = "Register `WORDS` writer"]
|
#[doc = "Register `WORDS` writer"]
|
||||||
pub type W = crate::W<WordsSpec>;
|
pub type W = crate::W<WordsSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `PERID` reader"]
|
#[doc = "Register `PERID` reader"]
|
||||||
pub type R = crate::R<PeridSpec>;
|
pub type R = crate::R<PeridSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -3,6 +3,7 @@ pub type R = crate::R<PortaSpec>;
|
|||||||
#[doc = "Register `PORTA[%s]` writer"]
|
#[doc = "Register `PORTA[%s]` writer"]
|
||||||
pub type W = crate::W<PortaSpec>;
|
pub type W = crate::W<PortaSpec>;
|
||||||
#[doc = "Input Filter Selectoin\n\nValue on reset: 0"]
|
#[doc = "Input Filter Selectoin\n\nValue on reset: 0"]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||||
#[repr(u8)]
|
#[repr(u8)]
|
||||||
pub enum Flttype {
|
pub enum Flttype {
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<IntRamSbeSpec>;
|
pub type R = crate::R<IntRamSbeSpec>;
|
||||||
#[doc = "Register `INT_RAM_SBE` writer"]
|
#[doc = "Register `INT_RAM_SBE` writer"]
|
||||||
pub type W = crate::W<IntRamSbeSpec>;
|
pub type W = crate::W<IntRamSbeSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `PERID` reader"]
|
#[doc = "Register `PERID` reader"]
|
||||||
pub type R = crate::R<PeridSpec>;
|
pub type R = crate::R<PeridSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -97,6 +97,7 @@ pub static __INTERRUPTS: [Vector; 32] = [
|
|||||||
Vector { _handler: OC31 },
|
Vector { _handler: OC31 },
|
||||||
];
|
];
|
||||||
#[doc = r"Enumeration of all the interrupts."]
|
#[doc = r"Enumeration of all the interrupts."]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||||
#[repr(u16)]
|
#[repr(u16)]
|
||||||
pub enum Interrupt {
|
pub enum Interrupt {
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `DATAIN` reader"]
|
#[doc = "Register `DATAIN` reader"]
|
||||||
pub type R = crate::R<DatainSpec>;
|
pub type R = crate::R<DatainSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `DATAINBYTE[%s]` reader"]
|
#[doc = "Register `DATAINBYTE[%s]` reader"]
|
||||||
pub type R = crate::R<DatainbyteSpec>;
|
pub type R = crate::R<DatainbyteSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<DatamaskSpec>;
|
pub type R = crate::R<DatamaskSpec>;
|
||||||
#[doc = "Register `DATAMASK` writer"]
|
#[doc = "Register `DATAMASK` writer"]
|
||||||
pub type W = crate::W<DatamaskSpec>;
|
pub type W = crate::W<DatamaskSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<DatamaskbyteSpec>;
|
pub type R = crate::R<DatamaskbyteSpec>;
|
||||||
#[doc = "Register `DATAMASKBYTE[%s]` writer"]
|
#[doc = "Register `DATAMASKBYTE[%s]` writer"]
|
||||||
pub type W = crate::W<DatamaskbyteSpec>;
|
pub type W = crate::W<DatamaskbyteSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `DATAOUT` writer"]
|
#[doc = "Register `DATAOUT` writer"]
|
||||||
pub type W = crate::W<DataoutSpec>;
|
pub type W = crate::W<DataoutSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for crate::generic::Reg<DataoutSpec> {
|
impl core::fmt::Debug for crate::generic::Reg<DataoutSpec> {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
|
||||||
write!(f, "(not readable)")
|
write!(f, "(not readable)")
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `DATAOUTBYTE[%s]` writer"]
|
#[doc = "Register `DATAOUTBYTE[%s]` writer"]
|
||||||
pub type W = crate::W<DataoutbyteSpec>;
|
pub type W = crate::W<DataoutbyteSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for crate::generic::Reg<DataoutbyteSpec> {
|
impl core::fmt::Debug for crate::generic::Reg<DataoutbyteSpec> {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
|
||||||
write!(f, "(not readable)")
|
write!(f, "(not readable)")
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<EdgeStatusSpec>;
|
pub type R = crate::R<EdgeStatusSpec>;
|
||||||
#[doc = "Register `EDGE_STATUS` writer"]
|
#[doc = "Register `EDGE_STATUS` writer"]
|
||||||
pub type W = crate::W<EdgeStatusSpec>;
|
pub type W = crate::W<EdgeStatusSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<IrqEdgeSpec>;
|
pub type R = crate::R<IrqEdgeSpec>;
|
||||||
#[doc = "Register `IRQ_EDGE` writer"]
|
#[doc = "Register `IRQ_EDGE` writer"]
|
||||||
pub type W = crate::W<IrqEdgeSpec>;
|
pub type W = crate::W<IrqEdgeSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<IrqEnbSpec>;
|
pub type R = crate::R<IrqEnbSpec>;
|
||||||
#[doc = "Register `IRQ_ENB` writer"]
|
#[doc = "Register `IRQ_ENB` writer"]
|
||||||
pub type W = crate::W<IrqEnbSpec>;
|
pub type W = crate::W<IrqEnbSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `IRQ_END` reader"]
|
#[doc = "Register `IRQ_END` reader"]
|
||||||
pub type R = crate::R<IrqEndSpec>;
|
pub type R = crate::R<IrqEndSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<IrqEvtSpec>;
|
pub type R = crate::R<IrqEvtSpec>;
|
||||||
#[doc = "Register `IRQ_EVT` writer"]
|
#[doc = "Register `IRQ_EVT` writer"]
|
||||||
pub type W = crate::W<IrqEvtSpec>;
|
pub type W = crate::W<IrqEvtSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `IRQ_RAW` reader"]
|
#[doc = "Register `IRQ_RAW` reader"]
|
||||||
pub type R = crate::R<IrqRawSpec>;
|
pub type R = crate::R<IrqRawSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<IrqSenSpec>;
|
pub type R = crate::R<IrqSenSpec>;
|
||||||
#[doc = "Register `IRQ_SEN` writer"]
|
#[doc = "Register `IRQ_SEN` writer"]
|
||||||
pub type W = crate::W<IrqSenSpec>;
|
pub type W = crate::W<IrqSenSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `PERID` reader"]
|
#[doc = "Register `PERID` reader"]
|
||||||
pub type R = crate::R<PeridSpec>;
|
pub type R = crate::R<PeridSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<ClkprescaleSpec>;
|
pub type R = crate::R<ClkprescaleSpec>;
|
||||||
#[doc = "Register `CLKPRESCALE` writer"]
|
#[doc = "Register `CLKPRESCALE` writer"]
|
||||||
pub type W = crate::W<ClkprescaleSpec>;
|
pub type W = crate::W<ClkprescaleSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<DataSpec>;
|
pub type R = crate::R<DataSpec>;
|
||||||
#[doc = "Register `DATA` writer"]
|
#[doc = "Register `DATA` writer"]
|
||||||
pub type W = crate::W<DataSpec>;
|
pub type W = crate::W<DataSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `PERID` reader"]
|
#[doc = "Register `PERID` reader"]
|
||||||
pub type R = crate::R<PeridSpec>;
|
pub type R = crate::R<PeridSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<RxfifoirqtrgSpec>;
|
pub type R = crate::R<RxfifoirqtrgSpec>;
|
||||||
#[doc = "Register `RXFIFOIRQTRG` writer"]
|
#[doc = "Register `RXFIFOIRQTRG` writer"]
|
||||||
pub type W = crate::W<RxfifoirqtrgSpec>;
|
pub type W = crate::W<RxfifoirqtrgSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `STATE` reader"]
|
#[doc = "Register `STATE` reader"]
|
||||||
pub type R = crate::R<StateSpec>;
|
pub type R = crate::R<StateSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<TxfifoirqtrgSpec>;
|
pub type R = crate::R<TxfifoirqtrgSpec>;
|
||||||
#[doc = "Register `TXFIFOIRQTRG` writer"]
|
#[doc = "Register `TXFIFOIRQTRG` writer"]
|
||||||
pub type W = crate::W<TxfifoirqtrgSpec>;
|
pub type W = crate::W<TxfifoirqtrgSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `EF_CONFIG` reader"]
|
#[doc = "Register `EF_CONFIG` reader"]
|
||||||
pub type R = crate::R<EfConfigSpec>;
|
pub type R = crate::R<EfConfigSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `EF_ID` reader"]
|
#[doc = "Register `EF_ID` reader"]
|
||||||
pub type R = crate::R<EfIdSpec>;
|
pub type R = crate::R<EfIdSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<IoconfigClkdivSpec>;
|
pub type R = crate::R<IoconfigClkdivSpec>;
|
||||||
#[doc = "Register `IOCONFIG_CLKDIV%s` writer"]
|
#[doc = "Register `IOCONFIG_CLKDIV%s` writer"]
|
||||||
pub type W = crate::W<IoconfigClkdivSpec>;
|
pub type W = crate::W<IoconfigClkdivSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `IOCONFIG_CLKDIV0` reader"]
|
#[doc = "Register `IOCONFIG_CLKDIV0` reader"]
|
||||||
pub type R = crate::R<IoconfigClkdiv0Spec>;
|
pub type R = crate::R<IoconfigClkdiv0Spec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `PERID` reader"]
|
#[doc = "Register `PERID` reader"]
|
||||||
pub type R = crate::R<PeridSpec>;
|
pub type R = crate::R<PeridSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `PROCID` reader"]
|
#[doc = "Register `PROCID` reader"]
|
||||||
pub type R = crate::R<ProcidSpec>;
|
pub type R = crate::R<ProcidSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<RamSbeSpec>;
|
pub type R = crate::R<RamSbeSpec>;
|
||||||
#[doc = "Register `RAM_SBE` writer"]
|
#[doc = "Register `RAM_SBE` writer"]
|
||||||
pub type W = crate::W<RamSbeSpec>;
|
pub type W = crate::W<RamSbeSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<RefreshConfigSpec>;
|
pub type R = crate::R<RefreshConfigSpec>;
|
||||||
#[doc = "Register `REFRESH_CONFIG` writer"]
|
#[doc = "Register `REFRESH_CONFIG` writer"]
|
||||||
pub type W = crate::W<RefreshConfigSpec>;
|
pub type W = crate::W<RefreshConfigSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `ROM_RETRIES` reader"]
|
#[doc = "Register `ROM_RETRIES` reader"]
|
||||||
pub type R = crate::R<RomRetriesSpec>;
|
pub type R = crate::R<RomRetriesSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<TimClkEnableSpec>;
|
pub type R = crate::R<TimClkEnableSpec>;
|
||||||
#[doc = "Register `TIM_CLK_ENABLE` writer"]
|
#[doc = "Register `TIM_CLK_ENABLE` writer"]
|
||||||
pub type W = crate::W<TimClkEnableSpec>;
|
pub type W = crate::W<TimClkEnableSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<TimResetSpec>;
|
pub type R = crate::R<TimResetSpec>;
|
||||||
#[doc = "Register `TIM_RESET` writer"]
|
#[doc = "Register `TIM_RESET` writer"]
|
||||||
pub type W = crate::W<TimResetSpec>;
|
pub type W = crate::W<TimResetSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<CntValueSpec>;
|
pub type R = crate::R<CntValueSpec>;
|
||||||
#[doc = "Register `CNT_VALUE` writer"]
|
#[doc = "Register `CNT_VALUE` writer"]
|
||||||
pub type W = crate::W<CntValueSpec>;
|
pub type W = crate::W<CntValueSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -21,6 +21,7 @@ pub type IrqEnbR = crate::BitReader;
|
|||||||
#[doc = "Field `IRQ_ENB` writer - Interrupt Enable"]
|
#[doc = "Field `IRQ_ENB` writer - Interrupt Enable"]
|
||||||
pub type IrqEnbW<'a, REG> = crate::BitWriter<'a, REG>;
|
pub type IrqEnbW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||||
#[doc = "Counter Status Selection\n\nValue on reset: 0"]
|
#[doc = "Counter Status Selection\n\nValue on reset: 0"]
|
||||||
|
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||||
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
#[derive(Clone, Copy, Debug, PartialEq, Eq)]
|
||||||
#[repr(u8)]
|
#[repr(u8)]
|
||||||
pub enum StatusSel {
|
pub enum StatusSel {
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `PERID` reader"]
|
#[doc = "Register `PERID` reader"]
|
||||||
pub type R = crate::R<PeridSpec>;
|
pub type R = crate::R<PeridSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<PwmValueSpec>;
|
pub type R = crate::R<PwmValueSpec>;
|
||||||
#[doc = "Register `PWM_VALUE` writer"]
|
#[doc = "Register `PWM_VALUE` writer"]
|
||||||
pub type W = crate::W<PwmValueSpec>;
|
pub type W = crate::W<PwmValueSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<PwmaValueSpec>;
|
pub type R = crate::R<PwmaValueSpec>;
|
||||||
#[doc = "Register `PWMA_VALUE` writer"]
|
#[doc = "Register `PWMA_VALUE` writer"]
|
||||||
pub type W = crate::W<PwmaValueSpec>;
|
pub type W = crate::W<PwmaValueSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<PwmbValueSpec>;
|
pub type R = crate::R<PwmbValueSpec>;
|
||||||
#[doc = "Register `PWMB_VALUE` writer"]
|
#[doc = "Register `PWMB_VALUE` writer"]
|
||||||
pub type W = crate::W<PwmbValueSpec>;
|
pub type W = crate::W<PwmbValueSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<RstValueSpec>;
|
pub type R = crate::R<RstValueSpec>;
|
||||||
#[doc = "Register `RST_VALUE` writer"]
|
#[doc = "Register `RST_VALUE` writer"]
|
||||||
pub type W = crate::W<RstValueSpec>;
|
pub type W = crate::W<RstValueSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<Addr9Spec>;
|
pub type R = crate::R<Addr9Spec>;
|
||||||
#[doc = "Register `ADDR9` writer"]
|
#[doc = "Register `ADDR9` writer"]
|
||||||
pub type W = crate::W<Addr9Spec>;
|
pub type W = crate::W<Addr9Spec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<Addr9maskSpec>;
|
pub type R = crate::R<Addr9maskSpec>;
|
||||||
#[doc = "Register `ADDR9MASK` writer"]
|
#[doc = "Register `ADDR9MASK` writer"]
|
||||||
pub type W = crate::W<Addr9maskSpec>;
|
pub type W = crate::W<Addr9maskSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<DataSpec>;
|
pub type R = crate::R<DataSpec>;
|
||||||
#[doc = "Register `DATA` writer"]
|
#[doc = "Register `DATA` writer"]
|
||||||
pub type W = crate::W<DataSpec>;
|
pub type W = crate::W<DataSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `PERID` reader"]
|
#[doc = "Register `PERID` reader"]
|
||||||
pub type R = crate::R<PeridSpec>;
|
pub type R = crate::R<PeridSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<RxfifoirqtrgSpec>;
|
pub type R = crate::R<RxfifoirqtrgSpec>;
|
||||||
#[doc = "Register `RXFIFOIRQTRG` writer"]
|
#[doc = "Register `RXFIFOIRQTRG` writer"]
|
||||||
pub type W = crate::W<RxfifoirqtrgSpec>;
|
pub type W = crate::W<RxfifoirqtrgSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<RxfifortstrgSpec>;
|
pub type R = crate::R<RxfifortstrgSpec>;
|
||||||
#[doc = "Register `RXFIFORTSTRG` writer"]
|
#[doc = "Register `RXFIFORTSTRG` writer"]
|
||||||
pub type W = crate::W<RxfifortstrgSpec>;
|
pub type W = crate::W<RxfifortstrgSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `STATE` reader"]
|
#[doc = "Register `STATE` reader"]
|
||||||
pub type R = crate::R<StateSpec>;
|
pub type R = crate::R<StateSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `TXBREAK` writer"]
|
#[doc = "Register `TXBREAK` writer"]
|
||||||
pub type W = crate::W<TxbreakSpec>;
|
pub type W = crate::W<TxbreakSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for crate::generic::Reg<TxbreakSpec> {
|
impl core::fmt::Debug for crate::generic::Reg<TxbreakSpec> {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
|
||||||
write!(f, "(not readable)")
|
write!(f, "(not readable)")
|
||||||
|
@ -2,6 +2,7 @@
|
|||||||
pub type R = crate::R<TxfifoirqtrgSpec>;
|
pub type R = crate::R<TxfifoirqtrgSpec>;
|
||||||
#[doc = "Register `TXFIFOIRQTRG` writer"]
|
#[doc = "Register `TXFIFOIRQTRG` writer"]
|
||||||
pub type W = crate::W<TxfifoirqtrgSpec>;
|
pub type W = crate::W<TxfifoirqtrgSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `PERID` reader"]
|
#[doc = "Register `PERID` reader"]
|
||||||
pub type R = crate::R<PeridSpec>;
|
pub type R = crate::R<PeridSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `SYND_CHECK_32_52_DATA` reader"]
|
#[doc = "Register `SYND_CHECK_32_52_DATA` reader"]
|
||||||
pub type R = crate::R<SyndCheck32_52DataSpec>;
|
pub type R = crate::R<SyndCheck32_52DataSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `SYND_CHECK_32_52_SYND` reader"]
|
#[doc = "Register `SYND_CHECK_32_52_SYND` reader"]
|
||||||
pub type R = crate::R<SyndCheck32_52SyndSpec>;
|
pub type R = crate::R<SyndCheck32_52SyndSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `SYND_CHECK_32_DATA` reader"]
|
#[doc = "Register `SYND_CHECK_32_DATA` reader"]
|
||||||
pub type R = crate::R<SyndCheck32DataSpec>;
|
pub type R = crate::R<SyndCheck32DataSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
@ -1,5 +1,6 @@
|
|||||||
#[doc = "Register `SYND_CHECK_32_SYND` reader"]
|
#[doc = "Register `SYND_CHECK_32_SYND` reader"]
|
||||||
pub type R = crate::R<SyndCheck32SyndSpec>;
|
pub type R = crate::R<SyndCheck32SyndSpec>;
|
||||||
|
#[cfg(feature = "debug")]
|
||||||
impl core::fmt::Debug for R {
|
impl core::fmt::Debug for R {
|
||||||
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
|
||||||
write!(f, "{}", self.bits())
|
write!(f, "{}", self.bits())
|
||||||
|
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user