21525 lines
929 KiB
Plaintext
21525 lines
929 KiB
Plaintext
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max11619-adc: file format elf32-littlearm
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Disassembly of section .text:
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000000c0 <__stext>:
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c0: ldr r4, [pc, #44] <$d>
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c2: mov lr, r4
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c4: bl 0x8374 <__pre_init> @ imm = #33452
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c8: mov lr, r4
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ca: ldr r0, [pc, #40] <$d+0x6>
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cc: ldr r1, [pc, #40] <$d+0x8>
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ce: movs r2, #0
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d0: cmp r1, r0
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d2: beq 0xd8 <__stext+0x18> @ imm = #2
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d4: stm r0!, {r2}
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d6: b 0xd0 <__stext+0x10> @ imm = #-10
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d8: ldr r0, [pc, #32] <$d+0xc>
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da: ldr r1, [pc, #36] <$d+0x12>
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dc: ldr r2, [pc, #36] <$d+0x14>
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de: cmp r1, r0
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e0: beq 0xe8 <__stext+0x28> @ imm = #4
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e2: ldm r2!, {r3}
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e4: stm r0!, {r3}
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e6: b 0xde <__stext+0x1e> @ imm = #-12
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e8: push {lr}
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ea: bl 0x2604 <main> @ imm = #9494
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ee: udf #0
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000000f0 <$d>:
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f0: ff ff ff ff .word 0xffffffff
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f4: 00 00 00 10 .word 0x10000000
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f8: 44 04 00 10 .word 0x10000444
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fc: 00 00 00 10 .word 0x10000000
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100: 00 00 00 10 .word 0x10000000
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104: 30 c7 00 00 .word 0x0000c730
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00000108 <<T as core::convert::Into<U>>::into::hc185e8b6b339f934>:
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108: push {r7, lr}
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10a: add r7, sp, #0
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10c: sub sp, #8
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10e: str r0, [sp, #4]
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110: bl 0x544c <<va108xx_hal::time::Hertz as core::convert::From<va108xx_hal::time::MegaHertz>>::from::hc5caf156f8e04a82> @ imm = #21304
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114: str r0, [sp]
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116: b 0x118 <<T as core::convert::Into<U>>::into::hc185e8b6b339f934+0x10> @ imm = #-2
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118: ldr r0, [sp]
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11a: add sp, #8
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11c: pop {r7, pc}
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0000011e <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17h09721f9c421c6e2bE>:
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11e: push {r7, lr}
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120: add r7, sp, #0
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122: sub sp, #16
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124: add r1, sp, #4
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126: strb r0, [r1]
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128: ldr r0, [sp, #4]
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12a: add r1, sp, #12
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12c: strb r0, [r1]
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12e: bl 0x1488 <_ZN112_$LT$max116xx_10bit..Error$LT$SpiE$C$PinE$GT$$u20$as$u20$core..convert..From$LT$max116xx_10bit..AdcError$GT$$GT$4from17h13b2f106daae083dE> @ imm = #4950
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132: uxtb r0, r0
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134: str r0, [sp]
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136: b 0x138 <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17h09721f9c421c6e2bE+0x1a> @ imm = #-2
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138: ldr r0, [sp]
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13a: add r1, sp, #8
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13c: strb r0, [r1]
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13e: ldr r0, [sp, #8]
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140: add sp, #16
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142: pop {r7, pc}
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00000144 <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hde03a568dc94affdE>:
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144: push {r7, lr}
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146: add r7, sp, #0
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148: sub sp, #16
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14a: add r1, sp, #4
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14c: strb r0, [r1]
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14e: ldr r0, [sp, #4]
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150: add r1, sp, #12
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152: strb r0, [r1]
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154: bl 0x1e78 <<T as core::convert::From<T>>::from::hd605e0ee22c7694c> @ imm = #7456
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158: uxtb r0, r0
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15a: str r0, [sp]
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15c: b 0x15e <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hde03a568dc94affdE+0x1a> @ imm = #-2
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15e: ldr r0, [sp]
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160: add r1, sp, #8
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162: strb r0, [r1]
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164: ldr r0, [sp, #8]
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166: add sp, #16
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168: pop {r7, pc}
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0000016a <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hf0b33a7df54d743fE>:
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16a: push {r7, lr}
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16c: add r7, sp, #0
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16e: sub sp, #16
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170: str r0, [sp]
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172: add r0, sp, #8
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174: strb r1, [r0]
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176: ldr r0, [sp, #8]
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178: add r1, sp, #12
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17a: strb r0, [r1]
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17c: bl 0x1e78 <<T as core::convert::From<T>>::from::hd605e0ee22c7694c> @ imm = #7416
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180: uxtb r0, r0
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182: str r0, [sp, #4]
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184: b 0x186 <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hf0b33a7df54d743fE+0x1c> @ imm = #-2
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186: ldr r1, [sp]
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188: ldr r0, [sp, #4]
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18a: strb r0, [r1, #1]
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18c: movs r0, #1
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18e: strb r0, [r1]
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190: add sp, #16
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192: pop {r7, pc}
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00000194 <_ZN4core6result19Result$LT$T$C$E$GT$2ok17h03f43d67c30d745bE>:
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194: sub sp, #12
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196: mov r1, r0
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198: mov r0, sp
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19a: strb r1, [r0]
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19c: ldrb r0, [r0]
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19e: subs r1, r0, #2
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1a0: subs r2, r1, #1
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1a2: sbcs r1, r2
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1a4: cmp r0, #2
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1a6: beq 0x1ae <_ZN4core6result19Result$LT$T$C$E$GT$2ok17h03f43d67c30d745bE+0x1a> @ imm = #4
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1a8: b 0x1aa <_ZN4core6result19Result$LT$T$C$E$GT$2ok17h03f43d67c30d745bE+0x16> @ imm = #-2
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1aa: b 0x1b6 <_ZN4core6result19Result$LT$T$C$E$GT$2ok17h03f43d67c30d745bE+0x22> @ imm = #8
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1ac: trap
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1ae: add r1, sp, #4
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1b0: movs r0, #1
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1b2: strb r0, [r1]
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1b4: b 0x1be <_ZN4core6result19Result$LT$T$C$E$GT$2ok17h03f43d67c30d745bE+0x2a> @ imm = #6
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1b6: add r1, sp, #4
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1b8: movs r0, #0
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1ba: strb r0, [r1]
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1bc: b 0x1be <_ZN4core6result19Result$LT$T$C$E$GT$2ok17h03f43d67c30d745bE+0x2a> @ imm = #-2
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1be: mov r0, sp
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1c0: ldrb r0, [r0]
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1c2: cmp r0, #2
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1c4: bne 0x1d0 <_ZN4core6result19Result$LT$T$C$E$GT$2ok17h03f43d67c30d745bE+0x3c> @ imm = #8
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1c6: b 0x1c8 <_ZN4core6result19Result$LT$T$C$E$GT$2ok17h03f43d67c30d745bE+0x34> @ imm = #-2
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1c8: add r0, sp, #4
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1ca: ldrb r0, [r0]
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1cc: add sp, #12
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1ce: bx lr
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1d0: b 0x1c8 <_ZN4core6result19Result$LT$T$C$E$GT$2ok17h03f43d67c30d745bE+0x34> @ imm = #-12
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1d2: bmi 0x17e <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hf0b33a7df54d743fE+0x14> @ imm = #-88
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000001d4 <_ZN4core6result19Result$LT$T$C$E$GT$6expect17h72221175f5037eceE>:
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1d4: push {r4, r6, r7, lr}
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1d6: add r7, sp, #8
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1d8: sub sp, #40
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1da: str r3, [sp, #8]
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1dc: str r2, [sp, #12]
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1de: str r1, [sp, #16]
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1e0: mov r3, r0
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1e2: add r0, sp, #20
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1e4: strb r3, [r0]
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1e6: str r1, [sp, #32]
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1e8: str r2, [sp, #36]
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1ea: ldrb r0, [r0]
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1ec: subs r1, r0, #7
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1ee: subs r2, r1, #1
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1f0: sbcs r1, r2
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1f2: cmp r0, #7
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1f4: beq 0x1fc <_ZN4core6result19Result$LT$T$C$E$GT$6expect17h72221175f5037eceE+0x28> @ imm = #4
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1f6: b 0x1f8 <_ZN4core6result19Result$LT$T$C$E$GT$6expect17h72221175f5037eceE+0x24> @ imm = #-2
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1f8: b 0x200 <_ZN4core6result19Result$LT$T$C$E$GT$6expect17h72221175f5037eceE+0x2c> @ imm = #4
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1fa: trap
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1fc: add sp, #40
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1fe: pop {r4, r6, r7, pc}
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200: ldr r1, [sp, #12]
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202: ldr r0, [sp, #16]
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204: ldr r3, [sp, #8]
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206: ldr r4, [sp, #20]
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208: add r2, sp, #24
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20a: strb r4, [r2]
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20c: str r3, [sp]
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20e: ldr r3, [pc, #8] <$d.5+0x2>
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210: bl 0x85d8 <core::result::unwrap_failed::hab9917f6469ee00f> @ imm = #33732
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214: trap
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216: mov r8, r8
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00000218 <$d.5>:
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218: f0 a8 00 00 .word 0x0000a8f0
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0000021c <_ZN4core6result19Result$LT$T$C$E$GT$6expect17h8e33f6808ace1129E>:
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21c: push {r7, lr}
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21e: add r7, sp, #0
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220: sub sp, #40
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222: str r2, [sp, #8]
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224: str r1, [sp, #12]
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226: str r0, [sp, #16]
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228: str r0, [sp, #32]
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22a: str r1, [sp, #36]
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22c: movs r0, #1
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22e: cmp r0, #0
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230: bne 0x238 <_ZN4core6result19Result$LT$T$C$E$GT$6expect17h8e33f6808ace1129E+0x1c> @ imm = #4
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232: b 0x234 <_ZN4core6result19Result$LT$T$C$E$GT$6expect17h8e33f6808ace1129E+0x18> @ imm = #-2
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234: b 0x23c <_ZN4core6result19Result$LT$T$C$E$GT$6expect17h8e33f6808ace1129E+0x20> @ imm = #4
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236: trap
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238: add sp, #40
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23a: pop {r7, pc}
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23c: ldr r1, [sp, #12]
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23e: ldr r0, [sp, #16]
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240: ldr r2, [sp, #8]
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242: str r2, [sp]
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244: ldr r3, [pc, #8] <$d.7>
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246: add r2, sp, #24
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248: bl 0x85d8 <core::result::unwrap_failed::hab9917f6469ee00f> @ imm = #33676
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24c: trap
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24e: mov r8, r8
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00000250 <$d.7>:
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250: 00 a9 00 00 .word 0x0000a900
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00000254 <_ZN4core6result19Result$LT$T$C$E$GT$6expect17h8e7426d0ee999988E>:
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254: push {r4, r6, r7, lr}
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256: add r7, sp, #8
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258: sub sp, #40
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25a: str r3, [sp, #8]
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25c: str r2, [sp, #12]
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25e: str r1, [sp, #16]
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260: str r0, [sp, #20]
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262: ldr r0, [r7, #8]
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264: str r0, [sp, #24]
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266: str r2, [sp, #32]
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268: str r3, [sp, #36]
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26a: ldrb r0, [r1]
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26c: lsls r0, r0, #31
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26e: cmp r0, #0
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270: beq 0x278 <_ZN4core6result19Result$LT$T$C$E$GT$6expect17h8e7426d0ee999988E+0x24> @ imm = #4
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272: b 0x274 <_ZN4core6result19Result$LT$T$C$E$GT$6expect17h8e7426d0ee999988E+0x20> @ imm = #-2
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274: b 0x28a <_ZN4core6result19Result$LT$T$C$E$GT$6expect17h8e7426d0ee999988E+0x36> @ imm = #18
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276: trap
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278: ldr r0, [sp, #20]
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27a: ldr r1, [sp, #16]
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27c: adds r1, r1, #4
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27e: ldm r1!, {r2, r3, r4}
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280: stm r0!, {r2, r3, r4}
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282: ldm r1!, {r2, r3, r4}
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284: stm r0!, {r2, r3, r4}
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286: add sp, #40
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288: pop {r4, r6, r7, pc}
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28a: ldr r1, [sp, #8]
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28c: ldr r0, [sp, #12]
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28e: ldr r3, [sp, #24]
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290: ldr r2, [sp, #16]
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292: ldrb r4, [r2, #1]
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294: add r2, sp, #28
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296: strb r4, [r2]
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298: str r3, [sp]
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29a: ldr r3, [pc, #8] <$d.9+0x2>
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29c: bl 0x85d8 <core::result::unwrap_failed::hab9917f6469ee00f> @ imm = #33592
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2a0: trap
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2a2: mov r8, r8
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000002a4 <$d.9>:
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2a4: f0 a8 00 00 .word 0x0000a8f0
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000002a8 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h2f75cf6a7249e271E>:
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2a8: push {r7, lr}
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2aa: add r7, sp, #0
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2ac: sub sp, #40
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2ae: str r0, [sp, #4]
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2b0: str r1, [sp, #8]
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2b2: str r2, [sp, #12]
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2b4: add r1, sp, #20
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2b6: movs r0, #0
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2b8: strb r0, [r1]
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2ba: movs r0, #1
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2bc: strb r0, [r1]
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2be: cmp r0, #0
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2c0: bne 0x2c8 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h2f75cf6a7249e271E+0x20> @ imm = #4
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2c2: b 0x2c4 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h2f75cf6a7249e271E+0x1c> @ imm = #-2
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2c4: b 0x2dc <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h2f75cf6a7249e271E+0x34> @ imm = #20
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2c6: trap
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2c8: ldr r1, [sp, #4]
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2ca: ldr r2, [sp, #8]
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2cc: ldr r0, [sp, #12]
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2ce: str r2, [sp, #32]
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2d0: str r0, [sp, #36]
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2d2: str r2, [r1, #4]
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2d4: str r0, [r1, #8]
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2d6: movs r0, #0
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2d8: strb r0, [r1]
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2da: b 0x2f8 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h2f75cf6a7249e271E+0x50> @ imm = #26
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2dc: add r1, sp, #20
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2de: movs r0, #0
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2e0: strb r0, [r1]
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2e2: bl 0x1f6e <core::ops::function::FnOnce::call_once::hfc8883650157a433> @ imm = #7304
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2e6: uxtb r0, r0
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2e8: str r0, [sp]
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2ea: b 0x2ec <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h2f75cf6a7249e271E+0x44> @ imm = #-2
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2ec: ldr r1, [sp, #4]
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2ee: ldr r0, [sp]
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2f0: strb r0, [r1, #1]
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2f2: movs r0, #1
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2f4: strb r0, [r1]
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2f6: b 0x2f8 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h2f75cf6a7249e271E+0x50> @ imm = #-2
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2f8: add r0, sp, #20
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2fa: ldrb r0, [r0]
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2fc: lsls r0, r0, #31
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2fe: cmp r0, #0
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300: bne 0x308 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h2f75cf6a7249e271E+0x60> @ imm = #4
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302: b 0x304 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h2f75cf6a7249e271E+0x5c> @ imm = #-2
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304: add sp, #40
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306: pop {r7, pc}
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308: b 0x304 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h2f75cf6a7249e271E+0x5c> @ imm = #-8
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0000030a <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE>:
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30a: push {r7, lr}
|
|
30c: add r7, sp, #0
|
|
30e: sub sp, #32
|
|
310: add r1, sp, #16
|
|
312: movs r0, #0
|
|
314: strb r0, [r1]
|
|
316: movs r0, #1
|
|
318: strb r0, [r1]
|
|
31a: cmp r0, #0
|
|
31c: bne 0x324 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE+0x1a> @ imm = #4
|
|
31e: b 0x320 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE+0x16> @ imm = #-2
|
|
320: b 0x330 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE+0x26> @ imm = #12
|
|
322: trap
|
|
324: add r1, sp, #8
|
|
326: movs r0, #0
|
|
328: strb r0, [r1]
|
|
32a: movs r0, #7
|
|
32c: strb r0, [r1]
|
|
32e: b 0x348 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE+0x3e> @ imm = #22
|
|
330: add r1, sp, #16
|
|
332: movs r0, #0
|
|
334: strb r0, [r1]
|
|
336: bl 0x1f58 <core::ops::function::FnOnce::call_once::h63d663bb20109018> @ imm = #7198
|
|
33a: uxtb r0, r0
|
|
33c: str r0, [sp]
|
|
33e: b 0x340 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE+0x36> @ imm = #-2
|
|
340: ldr r0, [sp]
|
|
342: add r1, sp, #8
|
|
344: strb r0, [r1]
|
|
346: b 0x348 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE+0x3e> @ imm = #-2
|
|
348: add r0, sp, #16
|
|
34a: ldrb r0, [r0]
|
|
34c: lsls r0, r0, #31
|
|
34e: cmp r0, #0
|
|
350: bne 0x35a <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE+0x50> @ imm = #6
|
|
352: b 0x354 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE+0x4a> @ imm = #-2
|
|
354: ldr r0, [sp, #8]
|
|
356: add sp, #32
|
|
358: pop {r7, pc}
|
|
35a: b 0x354 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE+0x4a> @ imm = #-10
|
|
|
|
0000035c <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17hf0e429eaa3a37c4aE>:
|
|
35c: push {r7, lr}
|
|
35e: add r7, sp, #0
|
|
360: sub sp, #32
|
|
362: add r1, sp, #16
|
|
364: movs r0, #0
|
|
366: strb r0, [r1]
|
|
368: movs r0, #1
|
|
36a: strb r0, [r1]
|
|
36c: cmp r0, #0
|
|
36e: bne 0x376 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17hf0e429eaa3a37c4aE+0x1a> @ imm = #4
|
|
370: b 0x372 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17hf0e429eaa3a37c4aE+0x16> @ imm = #-2
|
|
372: b 0x382 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17hf0e429eaa3a37c4aE+0x26> @ imm = #12
|
|
374: trap
|
|
376: add r1, sp, #8
|
|
378: movs r0, #0
|
|
37a: strb r0, [r1]
|
|
37c: movs r0, #7
|
|
37e: strb r0, [r1]
|
|
380: b 0x39a <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17hf0e429eaa3a37c4aE+0x3e> @ imm = #22
|
|
382: add r1, sp, #16
|
|
384: movs r0, #0
|
|
386: strb r0, [r1]
|
|
388: bl 0x1f6e <core::ops::function::FnOnce::call_once::hfc8883650157a433> @ imm = #7138
|
|
38c: uxtb r0, r0
|
|
38e: str r0, [sp]
|
|
390: b 0x392 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17hf0e429eaa3a37c4aE+0x36> @ imm = #-2
|
|
392: ldr r0, [sp]
|
|
394: add r1, sp, #8
|
|
396: strb r0, [r1]
|
|
398: b 0x39a <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17hf0e429eaa3a37c4aE+0x3e> @ imm = #-2
|
|
39a: add r0, sp, #16
|
|
39c: ldrb r0, [r0]
|
|
39e: lsls r0, r0, #31
|
|
3a0: cmp r0, #0
|
|
3a2: bne 0x3ac <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17hf0e429eaa3a37c4aE+0x50> @ imm = #6
|
|
3a4: b 0x3a6 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17hf0e429eaa3a37c4aE+0x4a> @ imm = #-2
|
|
3a6: ldr r0, [sp, #8]
|
|
3a8: add sp, #32
|
|
3aa: pop {r7, pc}
|
|
3ac: b 0x3a6 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17hf0e429eaa3a37c4aE+0x4a> @ imm = #-10
|
|
|
|
000003ae <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h03eff1b1a9c091dcE>:
|
|
3ae: push {r4, r5, r6, r7, lr}
|
|
3b0: add r7, sp, #12
|
|
3b2: sub sp, #64
|
|
3b4: str r1, [sp]
|
|
3b6: str r0, [sp, #4]
|
|
3b8: ldrb r0, [r1]
|
|
3ba: lsls r0, r0, #31
|
|
3bc: cmp r0, #0
|
|
3be: beq 0x3c6 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h03eff1b1a9c091dcE+0x18> @ imm = #4
|
|
3c0: b 0x3c2 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h03eff1b1a9c091dcE+0x14> @ imm = #-2
|
|
3c2: b 0x3f4 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h03eff1b1a9c091dcE+0x46> @ imm = #46
|
|
3c4: trap
|
|
3c6: ldr r1, [sp, #4]
|
|
3c8: ldr r0, [sp]
|
|
3ca: adds r2, r0, #4
|
|
3cc: add r3, sp, #8
|
|
3ce: mov r0, r3
|
|
3d0: ldm r2!, {r4, r5, r6}
|
|
3d2: stm r0!, {r4, r5, r6}
|
|
3d4: ldm r2!, {r4, r5, r6}
|
|
3d6: stm r0!, {r4, r5, r6}
|
|
3d8: add r2, sp, #32
|
|
3da: mov r0, r2
|
|
3dc: ldm r3!, {r4, r5, r6}
|
|
3de: stm r0!, {r4, r5, r6}
|
|
3e0: ldm r3!, {r4, r5, r6}
|
|
3e2: stm r0!, {r4, r5, r6}
|
|
3e4: adds r0, r1, #4
|
|
3e6: ldm r2!, {r3, r4, r5}
|
|
3e8: stm r0!, {r3, r4, r5}
|
|
3ea: ldm r2!, {r3, r4, r5}
|
|
3ec: stm r0!, {r3, r4, r5}
|
|
3ee: movs r0, #0
|
|
3f0: strb r0, [r1]
|
|
3f2: b 0x40c <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h03eff1b1a9c091dcE+0x5e> @ imm = #22
|
|
3f4: ldr r1, [sp, #4]
|
|
3f6: ldr r0, [sp]
|
|
3f8: ldrb r0, [r0, #1]
|
|
3fa: add r2, sp, #60
|
|
3fc: strb r0, [r2]
|
|
3fe: add r2, sp, #56
|
|
400: strb r0, [r2]
|
|
402: ldr r0, [sp, #56]
|
|
404: strb r0, [r1, #1]
|
|
406: movs r0, #1
|
|
408: strb r0, [r1]
|
|
40a: b 0x40c <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h03eff1b1a9c091dcE+0x5e> @ imm = #-2
|
|
40c: add sp, #64
|
|
40e: pop {r4, r5, r6, r7, pc}
|
|
|
|
00000410 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h17eaa2cd8a173bf2E>:
|
|
410: sub sp, #40
|
|
412: str r1, [sp, #12]
|
|
414: str r0, [sp, #8]
|
|
416: ldr r0, [sp, #12]
|
|
418: str r0, [sp, #4]
|
|
41a: ldr r0, [sp, #8]
|
|
41c: str r0, [sp]
|
|
41e: mov r0, sp
|
|
420: ldrb r0, [r0]
|
|
422: lsls r0, r0, #31
|
|
424: cmp r0, #0
|
|
426: beq 0x42e <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h17eaa2cd8a173bf2E+0x1e> @ imm = #4
|
|
428: b 0x42a <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h17eaa2cd8a173bf2E+0x1a> @ imm = #-2
|
|
42a: b 0x43c <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h17eaa2cd8a173bf2E+0x2c> @ imm = #14
|
|
42c: trap
|
|
42e: ldr r0, [sp, #4]
|
|
430: str r0, [sp, #36]
|
|
432: str r0, [sp, #24]
|
|
434: add r1, sp, #20
|
|
436: movs r0, #0
|
|
438: strb r0, [r1]
|
|
43a: b 0x454 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h17eaa2cd8a173bf2E+0x44> @ imm = #22
|
|
43c: mov r0, sp
|
|
43e: ldrb r0, [r0, #1]
|
|
440: add r1, sp, #32
|
|
442: strb r0, [r1]
|
|
444: add r1, sp, #28
|
|
446: strb r0, [r1]
|
|
448: ldr r0, [sp, #28]
|
|
44a: add r1, sp, #20
|
|
44c: strb r0, [r1, #1]
|
|
44e: movs r0, #1
|
|
450: strb r0, [r1]
|
|
452: b 0x454 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h17eaa2cd8a173bf2E+0x44> @ imm = #-2
|
|
454: ldr r0, [sp, #20]
|
|
456: ldr r1, [sp, #24]
|
|
458: add sp, #40
|
|
45a: bx lr
|
|
|
|
0000045c <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h338082970efc5187E>:
|
|
45c: sub sp, #20
|
|
45e: mov r1, r0
|
|
460: mov r0, sp
|
|
462: strb r1, [r0]
|
|
464: ldrb r0, [r0]
|
|
466: subs r1, r0, #7
|
|
468: subs r2, r1, #1
|
|
46a: sbcs r1, r2
|
|
46c: cmp r0, #7
|
|
46e: beq 0x476 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h338082970efc5187E+0x1a> @ imm = #4
|
|
470: b 0x472 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h338082970efc5187E+0x16> @ imm = #-2
|
|
472: b 0x482 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h338082970efc5187E+0x26> @ imm = #12
|
|
474: trap
|
|
476: add r1, sp, #4
|
|
478: movs r0, #0
|
|
47a: strb r0, [r1]
|
|
47c: movs r0, #7
|
|
47e: strb r0, [r1]
|
|
480: b 0x494 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h338082970efc5187E+0x38> @ imm = #16
|
|
482: ldr r0, [sp]
|
|
484: add r1, sp, #16
|
|
486: strb r0, [r1]
|
|
488: add r1, sp, #8
|
|
48a: strb r0, [r1]
|
|
48c: ldr r0, [sp, #8]
|
|
48e: add r1, sp, #4
|
|
490: strb r0, [r1]
|
|
492: b 0x494 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h338082970efc5187E+0x38> @ imm = #-2
|
|
494: ldr r0, [sp, #4]
|
|
496: add sp, #20
|
|
498: bx lr
|
|
|
|
0000049a <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h6af079890abca98aE>:
|
|
49a: sub sp, #40
|
|
49c: str r1, [sp, #12]
|
|
49e: str r0, [sp, #8]
|
|
4a0: ldr r0, [sp, #12]
|
|
4a2: str r0, [sp, #4]
|
|
4a4: ldr r0, [sp, #8]
|
|
4a6: str r0, [sp]
|
|
4a8: mov r0, sp
|
|
4aa: ldrb r0, [r0]
|
|
4ac: lsls r0, r0, #31
|
|
4ae: cmp r0, #0
|
|
4b0: beq 0x4b8 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h6af079890abca98aE+0x1e> @ imm = #4
|
|
4b2: b 0x4b4 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h6af079890abca98aE+0x1a> @ imm = #-2
|
|
4b4: b 0x4c6 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h6af079890abca98aE+0x2c> @ imm = #14
|
|
4b6: trap
|
|
4b8: ldr r0, [sp, #4]
|
|
4ba: str r0, [sp, #36]
|
|
4bc: str r0, [sp, #24]
|
|
4be: add r1, sp, #20
|
|
4c0: movs r0, #0
|
|
4c2: strb r0, [r1]
|
|
4c4: b 0x4de <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h6af079890abca98aE+0x44> @ imm = #22
|
|
4c6: mov r0, sp
|
|
4c8: ldrb r0, [r0, #1]
|
|
4ca: add r1, sp, #32
|
|
4cc: strb r0, [r1]
|
|
4ce: add r1, sp, #28
|
|
4d0: strb r0, [r1]
|
|
4d2: ldr r0, [sp, #28]
|
|
4d4: add r1, sp, #20
|
|
4d6: strb r0, [r1, #1]
|
|
4d8: movs r0, #1
|
|
4da: strb r0, [r1]
|
|
4dc: b 0x4de <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h6af079890abca98aE+0x44> @ imm = #-2
|
|
4de: ldr r0, [sp, #20]
|
|
4e0: ldr r1, [sp, #24]
|
|
4e2: add sp, #40
|
|
4e4: bx lr
|
|
|
|
000004e6 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hc3644b3e57563e31E>:
|
|
4e6: sub sp, #24
|
|
4e8: str r1, [sp]
|
|
4ea: str r0, [sp, #4]
|
|
4ec: ldrb r0, [r1]
|
|
4ee: lsls r0, r0, #31
|
|
4f0: cmp r0, #0
|
|
4f2: beq 0x4fa <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hc3644b3e57563e31E+0x14> @ imm = #4
|
|
4f4: b 0x4f6 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hc3644b3e57563e31E+0x10> @ imm = #-2
|
|
4f6: b 0x510 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hc3644b3e57563e31E+0x2a> @ imm = #22
|
|
4f8: trap
|
|
4fa: ldr r1, [sp, #4]
|
|
4fc: ldr r0, [sp]
|
|
4fe: ldr r2, [r0, #4]
|
|
500: ldr r0, [r0, #8]
|
|
502: str r2, [sp, #16]
|
|
504: str r0, [sp, #20]
|
|
506: str r2, [r1, #4]
|
|
508: str r0, [r1, #8]
|
|
50a: movs r0, #0
|
|
50c: strb r0, [r1]
|
|
50e: b 0x528 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hc3644b3e57563e31E+0x42> @ imm = #22
|
|
510: ldr r1, [sp, #4]
|
|
512: ldr r0, [sp]
|
|
514: ldrb r0, [r0, #1]
|
|
516: add r2, sp, #12
|
|
518: strb r0, [r2]
|
|
51a: add r2, sp, #8
|
|
51c: strb r0, [r2]
|
|
51e: ldr r0, [sp, #8]
|
|
520: strb r0, [r1, #1]
|
|
522: movs r0, #1
|
|
524: strb r0, [r1]
|
|
526: b 0x528 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hc3644b3e57563e31E+0x42> @ imm = #-2
|
|
528: add sp, #24
|
|
52a: bx lr
|
|
|
|
0000052c <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hd072381b3388b3ddE>:
|
|
52c: sub sp, #20
|
|
52e: mov r2, r0
|
|
530: mov r0, sp
|
|
532: strb r2, [r0]
|
|
534: strb r1, [r0, #1]
|
|
536: ldrb r0, [r0]
|
|
538: lsls r0, r0, #31
|
|
53a: cmp r0, #0
|
|
53c: beq 0x544 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hd072381b3388b3ddE+0x18> @ imm = #4
|
|
53e: b 0x540 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hd072381b3388b3ddE+0x14> @ imm = #-2
|
|
540: b 0x556 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hd072381b3388b3ddE+0x2a> @ imm = #18
|
|
542: trap
|
|
544: mov r0, sp
|
|
546: ldrb r0, [r0, #1]
|
|
548: add r1, sp, #16
|
|
54a: strb r0, [r1]
|
|
54c: add r1, sp, #4
|
|
54e: strb r0, [r1, #1]
|
|
550: movs r0, #0
|
|
552: strb r0, [r1]
|
|
554: b 0x56e <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hd072381b3388b3ddE+0x42> @ imm = #22
|
|
556: mov r0, sp
|
|
558: ldrb r0, [r0, #1]
|
|
55a: add r1, sp, #12
|
|
55c: strb r0, [r1]
|
|
55e: add r1, sp, #8
|
|
560: strb r0, [r1]
|
|
562: ldr r0, [sp, #8]
|
|
564: add r1, sp, #4
|
|
566: strb r0, [r1, #1]
|
|
568: movs r0, #1
|
|
56a: strb r0, [r1]
|
|
56c: b 0x56e <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hd072381b3388b3ddE+0x42> @ imm = #-2
|
|
56e: add r1, sp, #4
|
|
570: ldrb r0, [r1]
|
|
572: ldrb r1, [r1, #1]
|
|
574: add sp, #20
|
|
576: bx lr
|
|
|
|
00000578 <<u8 as core::default::Default>::default::hb2792f91b4560cc9>:
|
|
578: movs r0, #0
|
|
57a: bx lr
|
|
|
|
0000057c <<bool as core::default::Default>::default::h6ce1fdee60a85673>:
|
|
57c: movs r0, #0
|
|
57e: bx lr
|
|
|
|
00000580 <core::intrinsics::write_bytes::he9556dc6ad4a2fb1>:
|
|
580: push {r7, lr}
|
|
582: add r7, sp, #0
|
|
584: sub sp, #16
|
|
586: mov r3, r2
|
|
588: mov r2, r1
|
|
58a: str r0, [sp, #4]
|
|
58c: add r1, sp, #8
|
|
58e: strb r2, [r1]
|
|
590: str r3, [sp, #12]
|
|
592: movs r1, #48
|
|
594: muls r1, r3, r1
|
|
596: uxtb r2, r2
|
|
598: bl 0xa678 <__aeabi_memset4> @ imm = #41180
|
|
59c: b 0x59e <core::intrinsics::write_bytes::he9556dc6ad4a2fb1+0x1e> @ imm = #-2
|
|
59e: add sp, #16
|
|
5a0: pop {r7, pc}
|
|
|
|
000005a2 <core::ptr::read::h5948e98be177969d>:
|
|
5a2: sub sp, #32
|
|
5a4: str r0, [sp, #4]
|
|
5a6: str r0, [sp, #12]
|
|
5a8: ldr r0, [sp, #16]
|
|
5aa: add r1, sp, #8
|
|
5ac: strb r0, [r1]
|
|
5ae: b 0x5b0 <core::ptr::read::h5948e98be177969d+0xe> @ imm = #-2
|
|
5b0: add r0, sp, #8
|
|
5b2: str r0, [sp, #28]
|
|
5b4: b 0x5b6 <core::ptr::read::h5948e98be177969d+0x14> @ imm = #-2
|
|
5b6: ldr r0, [sp, #4]
|
|
5b8: ldrb r1, [r0]
|
|
5ba: add r0, sp, #8
|
|
5bc: strb r1, [r0]
|
|
5be: ldrb r0, [r0]
|
|
5c0: str r0, [sp]
|
|
5c2: add r1, sp, #20
|
|
5c4: strb r0, [r1]
|
|
5c6: add r1, sp, #24
|
|
5c8: strb r0, [r1]
|
|
5ca: b 0x5cc <core::ptr::read::h5948e98be177969d+0x2a> @ imm = #-2
|
|
5cc: ldr r0, [sp]
|
|
5ce: add sp, #32
|
|
5d0: bx lr
|
|
|
|
000005d2 <core::ptr::write::hf9047898b6b9eddf>:
|
|
5d2: sub sp, #12
|
|
5d4: str r1, [sp]
|
|
5d6: mov r1, r0
|
|
5d8: ldr r0, [sp]
|
|
5da: add r2, sp, #4
|
|
5dc: strb r0, [r2]
|
|
5de: str r1, [sp, #8]
|
|
5e0: ldr r0, [sp, #4]
|
|
5e2: strb r0, [r1]
|
|
5e4: add sp, #12
|
|
5e6: bx lr
|
|
|
|
000005e8 <core::cmp::PartialEq::ne::hbb814c417ceb0a0e>:
|
|
5e8: push {r7, lr}
|
|
5ea: add r7, sp, #0
|
|
5ec: sub sp, #16
|
|
5ee: str r0, [sp, #8]
|
|
5f0: str r1, [sp, #12]
|
|
5f2: bl 0x9d8 <<va108xx_hal::utility::Funsel as core::cmp::PartialEq>::eq::h3e9e1be30ca41b10> @ imm = #994
|
|
5f6: str r0, [sp, #4]
|
|
5f8: b 0x5fa <core::cmp::PartialEq::ne::hbb814c417ceb0a0e+0x12> @ imm = #-2
|
|
5fa: ldr r1, [sp, #4]
|
|
5fc: movs r0, #1
|
|
5fe: bics r0, r1
|
|
600: add sp, #16
|
|
602: pop {r7, pc}
|
|
|
|
00000604 <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6>:
|
|
604: push {r4, r5, r6, r7, lr}
|
|
606: add r7, sp, #12
|
|
608: sub sp, #180
|
|
60a: str r0, [sp, #8]
|
|
60c: ldr r0, [r1, #8]
|
|
60e: str r0, [sp, #100]
|
|
610: ldr r0, [r1, #4]
|
|
612: str r0, [sp, #96]
|
|
614: ldr r0, [r1]
|
|
616: str r0, [sp, #92]
|
|
618: bl 0x4618 <dummy_pin::dummy::DummyPin::new_low::h44eb1aac66c84527> @ imm = #16380
|
|
61c: b 0x61e <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x1a> @ imm = #-2
|
|
61e: add r0, sp, #64
|
|
620: add r1, sp, #92
|
|
622: bl 0x1a54 <max116xx_10bit::Max116xx10Bit<SPI,CS>::max11619::h108cee7c000e330c> @ imm = #5166
|
|
626: b 0x628 <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x24> @ imm = #-2
|
|
628: add r0, sp, #36
|
|
62a: add r1, sp, #64
|
|
62c: bl 0x3ae <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h03eff1b1a9c091dcE> @ imm = #-642
|
|
630: b 0x632 <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x2e> @ imm = #-2
|
|
632: add r0, sp, #36
|
|
634: ldrb r0, [r0]
|
|
636: lsls r0, r0, #31
|
|
638: cmp r0, #0
|
|
63a: beq 0x642 <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x3e> @ imm = #4
|
|
63c: b 0x63e <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x3a> @ imm = #-2
|
|
63e: b 0x66a <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x66> @ imm = #40
|
|
640: trap
|
|
642: add r0, sp, #36
|
|
644: adds r1, r0, #4
|
|
646: add r2, sp, #104
|
|
648: mov r0, r2
|
|
64a: ldm r1!, {r3, r4, r5}
|
|
64c: stm r0!, {r3, r4, r5}
|
|
64e: ldm r1!, {r3, r4, r5}
|
|
650: stm r0!, {r3, r4, r5}
|
|
652: add r0, sp, #12
|
|
654: mov r1, r0
|
|
656: ldm r2!, {r3, r4, r5}
|
|
658: stm r1!, {r3, r4, r5}
|
|
65a: ldm r2!, {r3, r4, r5}
|
|
65c: stm r1!, {r3, r4, r5}
|
|
65e: movs r1, #0
|
|
660: bl 0x1d98 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::reset::h6445cf02374a70dd> @ imm = #5940
|
|
664: uxtb r0, r0
|
|
666: str r0, [sp, #4]
|
|
668: b 0x680 <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x7c> @ imm = #20
|
|
66a: ldr r0, [sp, #8]
|
|
66c: add r1, sp, #36
|
|
66e: ldrb r1, [r1, #1]
|
|
670: add r2, sp, #168
|
|
672: strb r1, [r2]
|
|
674: bl 0x16a <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hf0b33a7df54d743fE> @ imm = #-1294
|
|
678: b 0x67a <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x76> @ imm = #-2
|
|
67a: b 0x67c <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x78> @ imm = #-2
|
|
67c: add sp, #180
|
|
67e: pop {r4, r5, r6, r7, pc}
|
|
680: ldr r0, [sp, #4]
|
|
682: bl 0x45c <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h338082970efc5187E> @ imm = #-554
|
|
686: uxtb r0, r0
|
|
688: add r1, sp, #128
|
|
68a: strb r0, [r1]
|
|
68c: b 0x68e <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x8a> @ imm = #-2
|
|
68e: add r0, sp, #128
|
|
690: ldrb r0, [r0]
|
|
692: subs r1, r0, #7
|
|
694: subs r2, r1, #1
|
|
696: sbcs r1, r2
|
|
698: cmp r0, #7
|
|
69a: beq 0x6a2 <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x9e> @ imm = #4
|
|
69c: b 0x69e <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x9a> @ imm = #-2
|
|
69e: b 0x6ae <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0xaa> @ imm = #12
|
|
6a0: trap
|
|
6a2: add r0, sp, #12
|
|
6a4: bl 0x1dd2 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::setup::h2b9af7e788767d10> @ imm = #5930
|
|
6a8: uxtb r0, r0
|
|
6aa: str r0, [sp]
|
|
6ac: b 0x6c0 <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0xbc> @ imm = #16
|
|
6ae: ldr r0, [sp, #8]
|
|
6b0: ldr r1, [sp, #128]
|
|
6b2: add r2, sp, #172
|
|
6b4: strb r1, [r2]
|
|
6b6: bl 0x16a <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hf0b33a7df54d743fE> @ imm = #-1360
|
|
6ba: b 0x6bc <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0xb8> @ imm = #-2
|
|
6bc: b 0x6be <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0xba> @ imm = #-2
|
|
6be: b 0x67c <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x78> @ imm = #-70
|
|
6c0: ldr r0, [sp]
|
|
6c2: bl 0x45c <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h338082970efc5187E> @ imm = #-618
|
|
6c6: uxtb r0, r0
|
|
6c8: add r1, sp, #132
|
|
6ca: strb r0, [r1]
|
|
6cc: b 0x6ce <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0xca> @ imm = #-2
|
|
6ce: add r0, sp, #132
|
|
6d0: ldrb r0, [r0]
|
|
6d2: subs r1, r0, #7
|
|
6d4: subs r2, r1, #1
|
|
6d6: sbcs r1, r2
|
|
6d8: cmp r0, #7
|
|
6da: beq 0x6e2 <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0xde> @ imm = #4
|
|
6dc: b 0x6de <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0xda> @ imm = #-2
|
|
6de: b 0x702 <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0xfe> @ imm = #32
|
|
6e0: trap
|
|
6e2: ldr r1, [sp, #8]
|
|
6e4: add r3, sp, #12
|
|
6e6: add r2, sp, #136
|
|
6e8: mov r0, r2
|
|
6ea: ldm r3!, {r4, r5, r6}
|
|
6ec: stm r0!, {r4, r5, r6}
|
|
6ee: ldm r3!, {r4, r5, r6}
|
|
6f0: stm r0!, {r4, r5, r6}
|
|
6f2: adds r0, r1, #4
|
|
6f4: ldm r2!, {r3, r4, r5}
|
|
6f6: stm r0!, {r3, r4, r5}
|
|
6f8: ldm r2!, {r3, r4, r5}
|
|
6fa: stm r0!, {r3, r4, r5}
|
|
6fc: movs r0, #0
|
|
6fe: strb r0, [r1]
|
|
700: b 0x67c <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x78> @ imm = #-136
|
|
702: ldr r0, [sp, #8]
|
|
704: ldr r1, [sp, #132]
|
|
706: add r2, sp, #176
|
|
708: strb r1, [r2]
|
|
70a: bl 0x16a <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hf0b33a7df54d743fE> @ imm = #-1444
|
|
70e: b 0x710 <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0x10c> @ imm = #-2
|
|
710: b 0x6be <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0xba> @ imm = #-86
|
|
712: bmi 0x6be <vorago_reb1::max11619::max11619_externally_clocked_no_wakeup::hbb67f13da68fa3e6+0xba> @ imm = #-88
|
|
|
|
00000714 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70>:
|
|
714: push {r7, lr}
|
|
716: add r7, sp, #0
|
|
718: sub sp, #96
|
|
71a: mov r2, r1
|
|
71c: str r2, [sp, #4]
|
|
71e: str r0, [sp, #12]
|
|
720: add r2, sp, #16
|
|
722: strb r1, [r2]
|
|
724: str r0, [sp, #24]
|
|
726: b 0x728 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x14> @ imm = #-2
|
|
728: ldr r0, [pc, #280] <$d.1>
|
|
72a: str r0, [sp]
|
|
72c: str r0, [sp, #52]
|
|
72e: str r0, [sp, #60]
|
|
730: str r0, [sp, #64]
|
|
732: bl 0x8070 <core::ptr::read_volatile::hf4c692006cd65b29> @ imm = #31034
|
|
736: str r0, [sp, #56]
|
|
738: str r0, [sp, #40]
|
|
73a: ldr r1, [sp, #40]
|
|
73c: str r1, [sp, #72]
|
|
73e: str r1, [sp, #68]
|
|
740: ldr r1, [sp, #68]
|
|
742: str r1, [sp, #36]
|
|
744: str r0, [sp, #48]
|
|
746: ldr r0, [sp, #48]
|
|
748: str r0, [sp, #92]
|
|
74a: str r0, [sp, #88]
|
|
74c: ldr r0, [sp, #88]
|
|
74e: str r0, [sp, #44]
|
|
750: add r0, sp, #36
|
|
752: str r0, [sp, #28]
|
|
754: add r0, sp, #44
|
|
756: str r0, [sp, #32]
|
|
758: ldr r0, [sp, #28]
|
|
75a: ldr r1, [sp, #32]
|
|
75c: bl 0x3df0 <va108xx_hal::gpio::pins::PinsA::new::{{closure}}::hf626c193cc0edba5> @ imm = #13968
|
|
760: mov r1, r0
|
|
762: ldr r0, [sp]
|
|
764: ldr r1, [r1]
|
|
766: str r0, [sp, #76]
|
|
768: str r1, [sp, #80]
|
|
76a: str r0, [sp, #84]
|
|
76c: bl 0x8084 <core::ptr::write_volatile::h8d4daf2714a04997> @ imm = #30996
|
|
770: b 0x772 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x5e> @ imm = #-2
|
|
772: bl 0x3a58 <va108xx_hal::gpio::pins::Pin<I,M>::new::h64715132fd133831> @ imm = #13026
|
|
776: b 0x778 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x64> @ imm = #-2
|
|
778: bl 0x3a94 <va108xx_hal::gpio::pins::Pin<I,M>::new::h7d51278e7f56056d> @ imm = #13080
|
|
77c: b 0x77e <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x6a> @ imm = #-2
|
|
77e: bl 0x3a64 <va108xx_hal::gpio::pins::Pin<I,M>::new::h650c37744f8489ae> @ imm = #13026
|
|
782: b 0x784 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x70> @ imm = #-2
|
|
784: bl 0x3a40 <va108xx_hal::gpio::pins::Pin<I,M>::new::h45e011f5ea5d3bdc> @ imm = #12984
|
|
788: b 0x78a <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x76> @ imm = #-2
|
|
78a: bl 0x3ad0 <va108xx_hal::gpio::pins::Pin<I,M>::new::h908f3b669f15dfdf> @ imm = #13122
|
|
78e: b 0x790 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x7c> @ imm = #-2
|
|
790: bl 0x3a10 <va108xx_hal::gpio::pins::Pin<I,M>::new::h18eb5f607c4e3b6a> @ imm = #12924
|
|
794: b 0x796 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x82> @ imm = #-2
|
|
796: bl 0x3b6c <va108xx_hal::gpio::pins::Pin<I,M>::new::hda10b6a26e856d16> @ imm = #13266
|
|
79a: b 0x79c <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x88> @ imm = #-2
|
|
79c: bl 0x3b30 <va108xx_hal::gpio::pins::Pin<I,M>::new::hc700a86ca7326b11> @ imm = #13200
|
|
7a0: b 0x7a2 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x8e> @ imm = #-2
|
|
7a2: bl 0x3ae8 <va108xx_hal::gpio::pins::Pin<I,M>::new::h9cf26ae7ed0ab65c> @ imm = #13122
|
|
7a6: b 0x7a8 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x94> @ imm = #-2
|
|
7a8: bl 0x3b54 <va108xx_hal::gpio::pins::Pin<I,M>::new::hd3eadb3b051279a3> @ imm = #13224
|
|
7ac: b 0x7ae <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x9a> @ imm = #-2
|
|
7ae: bl 0x3b3c <va108xx_hal::gpio::pins::Pin<I,M>::new::hccaa9b3f205c4166> @ imm = #13194
|
|
7b2: b 0x7b4 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xa0> @ imm = #-2
|
|
7b4: bl 0x3af4 <va108xx_hal::gpio::pins::Pin<I,M>::new::ha0b449f7fbf71e3d> @ imm = #13116
|
|
7b8: b 0x7ba <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xa6> @ imm = #-2
|
|
7ba: bl 0x3a70 <va108xx_hal::gpio::pins::Pin<I,M>::new::h69a28e0f07999afb> @ imm = #12978
|
|
7be: b 0x7c0 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xac> @ imm = #-2
|
|
7c0: bl 0x3b24 <va108xx_hal::gpio::pins::Pin<I,M>::new::hc56534f9bc4f5f98> @ imm = #13152
|
|
7c4: b 0x7c6 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xb2> @ imm = #-2
|
|
7c6: bl 0x3a4c <va108xx_hal::gpio::pins::Pin<I,M>::new::h58edf0006af20877> @ imm = #12930
|
|
7ca: b 0x7cc <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xb8> @ imm = #-2
|
|
7cc: bl 0x3adc <va108xx_hal::gpio::pins::Pin<I,M>::new::h9afd2bd61f6c7977> @ imm = #13068
|
|
7d0: b 0x7d2 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xbe> @ imm = #-2
|
|
7d2: bl 0x39f8 <va108xx_hal::gpio::pins::Pin<I,M>::new::h0e947d8f70a5c4ee> @ imm = #12834
|
|
7d6: b 0x7d8 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xc4> @ imm = #-2
|
|
7d8: bl 0x3a1c <va108xx_hal::gpio::pins::Pin<I,M>::new::h1cb8688bb646f501> @ imm = #12864
|
|
7dc: b 0x7de <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xca> @ imm = #-2
|
|
7de: bl 0x3aac <va108xx_hal::gpio::pins::Pin<I,M>::new::h89205fae5478f36f> @ imm = #13002
|
|
7e2: b 0x7e4 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xd0> @ imm = #-2
|
|
7e4: bl 0x3aa0 <va108xx_hal::gpio::pins::Pin<I,M>::new::h8275ab7bcbb6a54a> @ imm = #12984
|
|
7e8: b 0x7ea <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xd6> @ imm = #-2
|
|
7ea: bl 0x3a7c <va108xx_hal::gpio::pins::Pin<I,M>::new::h7201b256be9742a4> @ imm = #12942
|
|
7ee: b 0x7f0 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xdc> @ imm = #-2
|
|
7f0: bl 0x3a28 <va108xx_hal::gpio::pins::Pin<I,M>::new::h2396cd2530aebe96> @ imm = #12852
|
|
7f4: b 0x7f6 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xe2> @ imm = #-2
|
|
7f6: bl 0x3a88 <va108xx_hal::gpio::pins::Pin<I,M>::new::h7aa3553f211620ac> @ imm = #12942
|
|
7fa: b 0x7fc <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xe8> @ imm = #-2
|
|
7fc: bl 0x3b0c <va108xx_hal::gpio::pins::Pin<I,M>::new::hbf033e46699cdbbc> @ imm = #13068
|
|
800: b 0x802 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xee> @ imm = #-2
|
|
802: bl 0x3b60 <va108xx_hal::gpio::pins::Pin<I,M>::new::hd6ad579ade87ada7> @ imm = #13146
|
|
806: b 0x808 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xf4> @ imm = #-2
|
|
808: bl 0x3b84 <va108xx_hal::gpio::pins::Pin<I,M>::new::he1b9d5f2ef973f75> @ imm = #13176
|
|
80c: b 0x80e <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0xfa> @ imm = #-2
|
|
80e: bl 0x3b18 <va108xx_hal::gpio::pins::Pin<I,M>::new::hc1b8b25c992f8f59> @ imm = #13062
|
|
812: b 0x814 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x100> @ imm = #-2
|
|
814: bl 0x3b78 <va108xx_hal::gpio::pins::Pin<I,M>::new::he19b1ce5ac8003d5> @ imm = #13152
|
|
818: b 0x81a <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x106> @ imm = #-2
|
|
81a: bl 0x3b9c <va108xx_hal::gpio::pins::Pin<I,M>::new::hf528d82e2890ec98> @ imm = #13182
|
|
81e: b 0x820 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x10c> @ imm = #-2
|
|
820: bl 0x3ac4 <va108xx_hal::gpio::pins::Pin<I,M>::new::h8b80fc4d66623596> @ imm = #12960
|
|
824: b 0x826 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x112> @ imm = #-2
|
|
826: bl 0x3b48 <va108xx_hal::gpio::pins::Pin<I,M>::new::hd22393e3b7f5ef05> @ imm = #13086
|
|
82a: b 0x82c <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x118> @ imm = #-2
|
|
82c: bl 0x3a34 <va108xx_hal::gpio::pins::Pin<I,M>::new::h3a848f637e0dd407> @ imm = #12804
|
|
830: b 0x832 <va108xx_hal::gpio::pins::PinsA::new::h2626fe2f1b4e3e70+0x11e> @ imm = #-2
|
|
832: ldr r1, [sp, #4]
|
|
834: movs r0, #1
|
|
836: ands r1, r0
|
|
838: add r0, sp, #8
|
|
83a: strb r1, [r0]
|
|
83c: ldrb r0, [r0]
|
|
83e: add sp, #96
|
|
840: pop {r7, pc}
|
|
842: mov r8, r8
|
|
|
|
00000844 <$d.1>:
|
|
844: 7c 00 00 40 .word 0x4000007c
|
|
|
|
00000848 <core::fmt::Arguments::new_v1::h2fca5f745a17c9bb>:
|
|
848: push {r4, r5, r7, lr}
|
|
84a: add r7, sp, #8
|
|
84c: sub sp, #56
|
|
84e: str r3, [sp, #8]
|
|
850: str r2, [sp, #12]
|
|
852: str r1, [sp, #16]
|
|
854: str r0, [sp, #20]
|
|
856: ldr r0, [r7, #8]
|
|
858: str r0, [sp, #24]
|
|
85a: str r1, [sp, #40]
|
|
85c: str r2, [sp, #44]
|
|
85e: str r3, [sp, #48]
|
|
860: str r0, [sp, #52]
|
|
862: cmp r2, r0
|
|
864: blo 0x886 <core::fmt::Arguments::new_v1::h2fca5f745a17c9bb+0x3e> @ imm = #30
|
|
866: b 0x868 <core::fmt::Arguments::new_v1::h2fca5f745a17c9bb+0x20> @ imm = #-2
|
|
868: ldr r1, [sp, #12]
|
|
86a: ldr r0, [sp, #24]
|
|
86c: adds r2, r0, #1
|
|
86e: movs r0, #1
|
|
870: movs r3, #0
|
|
872: str r3, [sp]
|
|
874: cmp r1, r2
|
|
876: str r0, [sp, #4]
|
|
878: bhi 0x87e <core::fmt::Arguments::new_v1::h2fca5f745a17c9bb+0x36> @ imm = #2
|
|
87a: ldr r0, [sp]
|
|
87c: str r0, [sp, #4]
|
|
87e: ldr r0, [sp, #4]
|
|
880: add r1, sp, #28
|
|
882: strb r0, [r1]
|
|
884: b 0x88e <core::fmt::Arguments::new_v1::h2fca5f745a17c9bb+0x46> @ imm = #6
|
|
886: add r1, sp, #28
|
|
888: movs r0, #1
|
|
88a: strb r0, [r1]
|
|
88c: b 0x88e <core::fmt::Arguments::new_v1::h2fca5f745a17c9bb+0x46> @ imm = #-2
|
|
88e: add r0, sp, #28
|
|
890: ldrb r0, [r0]
|
|
892: lsls r0, r0, #31
|
|
894: cmp r0, #0
|
|
896: bne 0x8c0 <core::fmt::Arguments::new_v1::h2fca5f745a17c9bb+0x78> @ imm = #38
|
|
898: b 0x89a <core::fmt::Arguments::new_v1::h2fca5f745a17c9bb+0x52> @ imm = #-2
|
|
89a: ldr r0, [sp, #24]
|
|
89c: ldr r1, [sp, #20]
|
|
89e: ldr r2, [sp, #8]
|
|
8a0: ldr r3, [sp, #12]
|
|
8a2: ldr r4, [sp, #16]
|
|
8a4: movs r5, #0
|
|
8a6: str r5, [sp, #36]
|
|
8a8: str r5, [sp, #32]
|
|
8aa: str r5, [sp, #32]
|
|
8ac: str r4, [r1]
|
|
8ae: str r3, [r1, #4]
|
|
8b0: ldr r4, [sp, #32]
|
|
8b2: ldr r3, [sp, #36]
|
|
8b4: str r4, [r1, #8]
|
|
8b6: str r3, [r1, #12]
|
|
8b8: str r2, [r1, #16]
|
|
8ba: str r0, [r1, #20]
|
|
8bc: add sp, #56
|
|
8be: pop {r4, r5, r7, pc}
|
|
8c0: ldr r0, [pc, #8] <$d.1>
|
|
8c2: ldr r2, [pc, #12] <$d.1+0x6>
|
|
8c4: movs r1, #12
|
|
8c6: bl 0x8548 <core::panicking::panic::hd188a7f3102defa3> @ imm = #31870
|
|
8ca: trap
|
|
|
|
000008cc <$d.1>:
|
|
8cc: 10 a9 00 00 .word 0x0000a910
|
|
8d0: 68 a9 00 00 .word 0x0000a968
|
|
|
|
000008d4 <<va108xx_hal::gpio::dynpins::DynInput as core::cmp::PartialEq>::eq::hf566ff60b6aa11fe>:
|
|
8d4: sub sp, #20
|
|
8d6: str r0, [sp, #4]
|
|
8d8: str r1, [sp, #8]
|
|
8da: ldrb r0, [r0]
|
|
8dc: str r0, [sp, #12]
|
|
8de: ldrb r1, [r1]
|
|
8e0: str r1, [sp, #16]
|
|
8e2: cmp r0, r1
|
|
8e4: beq 0x8f0 <<va108xx_hal::gpio::dynpins::DynInput as core::cmp::PartialEq>::eq::hf566ff60b6aa11fe+0x1c> @ imm = #8
|
|
8e6: b 0x8e8 <<va108xx_hal::gpio::dynpins::DynInput as core::cmp::PartialEq>::eq::hf566ff60b6aa11fe+0x14> @ imm = #-2
|
|
8e8: mov r1, sp
|
|
8ea: movs r0, #0
|
|
8ec: strb r0, [r1]
|
|
8ee: b 0x8f8 <<va108xx_hal::gpio::dynpins::DynInput as core::cmp::PartialEq>::eq::hf566ff60b6aa11fe+0x24> @ imm = #6
|
|
8f0: mov r1, sp
|
|
8f2: movs r0, #1
|
|
8f4: strb r0, [r1]
|
|
8f6: b 0x8f8 <<va108xx_hal::gpio::dynpins::DynInput as core::cmp::PartialEq>::eq::hf566ff60b6aa11fe+0x24> @ imm = #-2
|
|
8f8: mov r0, sp
|
|
8fa: ldrb r0, [r0]
|
|
8fc: add sp, #20
|
|
8fe: bx lr
|
|
|
|
00000900 <<va108xx_hal::gpio::dynpins::DynOutput as core::cmp::PartialEq>::eq::hf1273109ef798499>:
|
|
900: sub sp, #20
|
|
902: str r0, [sp, #4]
|
|
904: str r1, [sp, #8]
|
|
906: ldrb r0, [r0]
|
|
908: str r0, [sp, #12]
|
|
90a: ldrb r1, [r1]
|
|
90c: str r1, [sp, #16]
|
|
90e: cmp r0, r1
|
|
910: beq 0x91c <<va108xx_hal::gpio::dynpins::DynOutput as core::cmp::PartialEq>::eq::hf1273109ef798499+0x1c> @ imm = #8
|
|
912: b 0x914 <<va108xx_hal::gpio::dynpins::DynOutput as core::cmp::PartialEq>::eq::hf1273109ef798499+0x14> @ imm = #-2
|
|
914: mov r1, sp
|
|
916: movs r0, #0
|
|
918: strb r0, [r1]
|
|
91a: b 0x924 <<va108xx_hal::gpio::dynpins::DynOutput as core::cmp::PartialEq>::eq::hf1273109ef798499+0x24> @ imm = #6
|
|
91c: mov r1, sp
|
|
91e: movs r0, #1
|
|
920: strb r0, [r1]
|
|
922: b 0x924 <<va108xx_hal::gpio::dynpins::DynOutput as core::cmp::PartialEq>::eq::hf1273109ef798499+0x24> @ imm = #-2
|
|
924: mov r0, sp
|
|
926: ldrb r0, [r0]
|
|
928: add sp, #20
|
|
92a: bx lr
|
|
|
|
0000092c <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d>:
|
|
92c: push {r7, lr}
|
|
92e: add r7, sp, #0
|
|
930: sub sp, #64
|
|
932: str r1, [sp, #4]
|
|
934: str r0, [sp, #8]
|
|
936: str r0, [sp, #24]
|
|
938: str r1, [sp, #28]
|
|
93a: ldrb r0, [r0]
|
|
93c: str r0, [sp, #32]
|
|
93e: ldrb r1, [r1]
|
|
940: str r1, [sp, #36]
|
|
942: cmp r0, r1
|
|
944: beq 0x950 <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x24> @ imm = #8
|
|
946: b 0x948 <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x1c> @ imm = #-2
|
|
948: add r1, sp, #12
|
|
94a: movs r0, #1
|
|
94c: strb r0, [r1]
|
|
94e: b 0x9a4 <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x78> @ imm = #82
|
|
950: ldr r0, [sp, #4]
|
|
952: ldr r1, [sp, #8]
|
|
954: str r1, [sp, #16]
|
|
956: str r0, [sp, #20]
|
|
958: ldr r0, [sp, #16]
|
|
95a: ldrb r0, [r0]
|
|
95c: str r0, [sp]
|
|
95e: cmp r0, #0
|
|
960: beq 0x970 <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x44> @ imm = #12
|
|
962: b 0x964 <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x38> @ imm = #-2
|
|
964: ldr r0, [sp]
|
|
966: cmp r0, #1
|
|
968: beq 0x97a <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x4e> @ imm = #14
|
|
96a: b 0x96c <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x40> @ imm = #-2
|
|
96c: b 0x984 <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x58> @ imm = #20
|
|
96e: trap
|
|
970: ldr r0, [sp, #20]
|
|
972: ldrb r0, [r0]
|
|
974: cmp r0, #0
|
|
976: beq 0x9c2 <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x96> @ imm = #72
|
|
978: b 0x96e <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x42> @ imm = #-14
|
|
97a: ldr r0, [sp, #20]
|
|
97c: ldrb r0, [r0]
|
|
97e: cmp r0, #1
|
|
980: beq 0x9ac <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x80> @ imm = #40
|
|
982: b 0x96e <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x42> @ imm = #-24
|
|
984: ldr r0, [sp, #20]
|
|
986: ldrb r0, [r0]
|
|
988: cmp r0, #2
|
|
98a: bne 0x96e <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x42> @ imm = #-32
|
|
98c: b 0x98e <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x62> @ imm = #-2
|
|
98e: ldr r0, [sp, #16]
|
|
990: adds r0, r0, #1
|
|
992: str r0, [sp, #40]
|
|
994: ldr r1, [sp, #20]
|
|
996: adds r1, r1, #1
|
|
998: str r1, [sp, #44]
|
|
99a: bl 0x5e8 <core::cmp::PartialEq::ne::hbb814c417ceb0a0e> @ imm = #-950
|
|
99e: add r1, sp, #12
|
|
9a0: strb r0, [r1]
|
|
9a2: b 0x9a4 <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x78> @ imm = #-2
|
|
9a4: add r0, sp, #12
|
|
9a6: ldrb r0, [r0]
|
|
9a8: add sp, #64
|
|
9aa: pop {r7, pc}
|
|
9ac: ldr r0, [sp, #16]
|
|
9ae: adds r0, r0, #1
|
|
9b0: str r0, [sp, #48]
|
|
9b2: ldr r1, [sp, #20]
|
|
9b4: adds r1, r1, #1
|
|
9b6: str r1, [sp, #52]
|
|
9b8: bl 0x2034 <core::cmp::PartialEq::ne::h12c2ee69d5902ab8> @ imm = #5752
|
|
9bc: add r1, sp, #12
|
|
9be: strb r0, [r1]
|
|
9c0: b 0x9a4 <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x78> @ imm = #-32
|
|
9c2: ldr r0, [sp, #16]
|
|
9c4: adds r0, r0, #1
|
|
9c6: str r0, [sp, #56]
|
|
9c8: ldr r1, [sp, #20]
|
|
9ca: adds r1, r1, #1
|
|
9cc: str r1, [sp, #60]
|
|
9ce: bl 0x2050 <core::cmp::PartialEq::ne::h7227460b38c673f8> @ imm = #5758
|
|
9d2: add r1, sp, #12
|
|
9d4: strb r0, [r1]
|
|
9d6: b 0x9a4 <<va108xx_hal::gpio::dynpins::DynPinMode as core::cmp::PartialEq>::ne::h9557062a1ebbf52d+0x78> @ imm = #-54
|
|
|
|
000009d8 <<va108xx_hal::utility::Funsel as core::cmp::PartialEq>::eq::h3e9e1be30ca41b10>:
|
|
9d8: sub sp, #20
|
|
9da: str r0, [sp, #4]
|
|
9dc: str r1, [sp, #8]
|
|
9de: ldrb r0, [r0]
|
|
9e0: str r0, [sp, #12]
|
|
9e2: ldrb r1, [r1]
|
|
9e4: str r1, [sp, #16]
|
|
9e6: cmp r0, r1
|
|
9e8: beq 0x9f4 <<va108xx_hal::utility::Funsel as core::cmp::PartialEq>::eq::h3e9e1be30ca41b10+0x1c> @ imm = #8
|
|
9ea: b 0x9ec <<va108xx_hal::utility::Funsel as core::cmp::PartialEq>::eq::h3e9e1be30ca41b10+0x14> @ imm = #-2
|
|
9ec: mov r1, sp
|
|
9ee: movs r0, #0
|
|
9f0: strb r0, [r1]
|
|
9f2: b 0x9fc <<va108xx_hal::utility::Funsel as core::cmp::PartialEq>::eq::h3e9e1be30ca41b10+0x24> @ imm = #6
|
|
9f4: mov r1, sp
|
|
9f6: movs r0, #1
|
|
9f8: strb r0, [r1]
|
|
9fa: b 0x9fc <<va108xx_hal::utility::Funsel as core::cmp::PartialEq>::eq::h3e9e1be30ca41b10+0x24> @ imm = #-2
|
|
9fc: mov r0, sp
|
|
9fe: ldrb r0, [r0]
|
|
a00: add sp, #20
|
|
a02: bx lr
|
|
|
|
00000a04 <core::option::Option<T>::ok_or::h5474822a3a86c46c>:
|
|
a04: sub sp, #28
|
|
a06: mov r2, r1
|
|
a08: str r2, [sp]
|
|
a0a: str r0, [sp, #4]
|
|
a0c: add r0, sp, #20
|
|
a0e: strb r1, [r0]
|
|
a10: add r1, sp, #16
|
|
a12: movs r0, #0
|
|
a14: strb r0, [r1]
|
|
a16: movs r0, #1
|
|
a18: strb r0, [r1]
|
|
a1a: ldr r0, [sp, #4]
|
|
a1c: subs r2, r0, #1
|
|
a1e: mov r1, r0
|
|
a20: sbcs r1, r2
|
|
a22: cmp r0, #0
|
|
a24: beq 0xa2c <core::option::Option<T>::ok_or::h5474822a3a86c46c+0x28> @ imm = #4
|
|
a26: b 0xa28 <core::option::Option<T>::ok_or::h5474822a3a86c46c+0x24> @ imm = #-2
|
|
a28: b 0xa3e <core::option::Option<T>::ok_or::h5474822a3a86c46c+0x3a> @ imm = #18
|
|
a2a: trap
|
|
a2c: ldr r0, [sp]
|
|
a2e: add r2, sp, #16
|
|
a30: movs r1, #0
|
|
a32: strb r1, [r2]
|
|
a34: add r1, sp, #8
|
|
a36: strb r0, [r1, #1]
|
|
a38: movs r0, #1
|
|
a3a: strb r0, [r1]
|
|
a3c: b 0xa4c <core::option::Option<T>::ok_or::h5474822a3a86c46c+0x48> @ imm = #12
|
|
a3e: ldr r0, [sp, #4]
|
|
a40: str r0, [sp, #24]
|
|
a42: str r0, [sp, #12]
|
|
a44: add r1, sp, #8
|
|
a46: movs r0, #0
|
|
a48: strb r0, [r1]
|
|
a4a: b 0xa4c <core::option::Option<T>::ok_or::h5474822a3a86c46c+0x48> @ imm = #-2
|
|
a4c: add r0, sp, #16
|
|
a4e: ldrb r0, [r0]
|
|
a50: lsls r0, r0, #31
|
|
a52: cmp r0, #0
|
|
a54: bne 0xa60 <core::option::Option<T>::ok_or::h5474822a3a86c46c+0x5c> @ imm = #8
|
|
a56: b 0xa58 <core::option::Option<T>::ok_or::h5474822a3a86c46c+0x54> @ imm = #-2
|
|
a58: ldr r0, [sp, #8]
|
|
a5a: ldr r1, [sp, #12]
|
|
a5c: add sp, #28
|
|
a5e: bx lr
|
|
a60: b 0xa58 <core::option::Option<T>::ok_or::h5474822a3a86c46c+0x54> @ imm = #-12
|
|
|
|
00000a62 <core::option::Option<T>::ok_or::h7600f9cbeca56c74>:
|
|
a62: sub sp, #28
|
|
a64: mov r2, r1
|
|
a66: str r2, [sp]
|
|
a68: str r0, [sp, #4]
|
|
a6a: add r0, sp, #20
|
|
a6c: strb r1, [r0]
|
|
a6e: add r1, sp, #16
|
|
a70: movs r0, #0
|
|
a72: strb r0, [r1]
|
|
a74: movs r0, #1
|
|
a76: strb r0, [r1]
|
|
a78: ldr r0, [sp, #4]
|
|
a7a: subs r2, r0, #1
|
|
a7c: mov r1, r0
|
|
a7e: sbcs r1, r2
|
|
a80: cmp r0, #0
|
|
a82: beq 0xa8a <core::option::Option<T>::ok_or::h7600f9cbeca56c74+0x28> @ imm = #4
|
|
a84: b 0xa86 <core::option::Option<T>::ok_or::h7600f9cbeca56c74+0x24> @ imm = #-2
|
|
a86: b 0xa9c <core::option::Option<T>::ok_or::h7600f9cbeca56c74+0x3a> @ imm = #18
|
|
a88: trap
|
|
a8a: ldr r0, [sp]
|
|
a8c: add r2, sp, #16
|
|
a8e: movs r1, #0
|
|
a90: strb r1, [r2]
|
|
a92: add r1, sp, #8
|
|
a94: strb r0, [r1, #1]
|
|
a96: movs r0, #1
|
|
a98: strb r0, [r1]
|
|
a9a: b 0xaaa <core::option::Option<T>::ok_or::h7600f9cbeca56c74+0x48> @ imm = #12
|
|
a9c: ldr r0, [sp, #4]
|
|
a9e: str r0, [sp, #24]
|
|
aa0: str r0, [sp, #12]
|
|
aa2: add r1, sp, #8
|
|
aa4: movs r0, #0
|
|
aa6: strb r0, [r1]
|
|
aa8: b 0xaaa <core::option::Option<T>::ok_or::h7600f9cbeca56c74+0x48> @ imm = #-2
|
|
aaa: add r0, sp, #16
|
|
aac: ldrb r0, [r0]
|
|
aae: lsls r0, r0, #31
|
|
ab0: cmp r0, #0
|
|
ab2: bne 0xabe <core::option::Option<T>::ok_or::h7600f9cbeca56c74+0x5c> @ imm = #8
|
|
ab4: b 0xab6 <core::option::Option<T>::ok_or::h7600f9cbeca56c74+0x54> @ imm = #-2
|
|
ab6: ldr r0, [sp, #8]
|
|
ab8: ldr r1, [sp, #12]
|
|
aba: add sp, #28
|
|
abc: bx lr
|
|
abe: b 0xab6 <core::option::Option<T>::ok_or::h7600f9cbeca56c74+0x54> @ imm = #-12
|
|
|
|
00000ac0 <core::option::Option<T>::unwrap::h4a61a13bc106e812>:
|
|
ac0: push {r7, lr}
|
|
ac2: add r7, sp, #0
|
|
ac4: sub sp, #16
|
|
ac6: str r1, [sp, #4]
|
|
ac8: mov r1, r0
|
|
aca: add r0, sp, #8
|
|
acc: strb r1, [r0]
|
|
ace: ldrb r0, [r0]
|
|
ad0: lsls r0, r0, #31
|
|
ad2: cmp r0, #0
|
|
ad4: beq 0xadc <core::option::Option<T>::unwrap::h4a61a13bc106e812+0x1c> @ imm = #4
|
|
ad6: b 0xad8 <core::option::Option<T>::unwrap::h4a61a13bc106e812+0x18> @ imm = #-2
|
|
ad8: b 0xae8 <core::option::Option<T>::unwrap::h4a61a13bc106e812+0x28> @ imm = #12
|
|
ada: trap
|
|
adc: ldr r2, [sp, #4]
|
|
ade: ldr r0, [pc, #12] <$d.3+0x2>
|
|
ae0: movs r1, #43
|
|
ae2: bl 0x8548 <core::panicking::panic::hd188a7f3102defa3> @ imm = #31330
|
|
ae6: trap
|
|
ae8: add sp, #16
|
|
aea: pop {r7, pc}
|
|
|
|
00000aec <$d.3>:
|
|
aec: 78 a9 00 00 .word 0x0000a978
|
|
|
|
00000af0 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h0749be06a56a00e3>:
|
|
af0: sub sp, #32
|
|
af2: str r1, [sp]
|
|
af4: str r0, [sp, #4]
|
|
af6: str r1, [sp, #8]
|
|
af8: ldr r0, [r0]
|
|
afa: str r1, [sp, #12]
|
|
afc: str r0, [sp, #16]
|
|
afe: str r1, [sp, #20]
|
|
b00: str r0, [sp, #24]
|
|
b02: str r0, [r1]
|
|
b04: b 0xb06 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h0749be06a56a00e3+0x16> @ imm = #-2
|
|
b06: ldr r0, [sp]
|
|
b08: str r0, [sp, #28]
|
|
b0a: b 0xb0c <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h0749be06a56a00e3+0x1c> @ imm = #-2
|
|
b0c: ldr r0, [sp]
|
|
b0e: add sp, #32
|
|
b10: bx lr
|
|
|
|
00000b12 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h1da809e59f2f513d>:
|
|
b12: sub sp, #56
|
|
b14: str r2, [sp, #4]
|
|
b16: str r1, [sp, #8]
|
|
b18: str r0, [sp, #12]
|
|
b1a: str r0, [sp, #16]
|
|
b1c: str r1, [sp, #20]
|
|
b1e: str r2, [sp, #24]
|
|
b20: str r1, [sp, #28]
|
|
b22: b 0xb24 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h1da809e59f2f513d+0x12> @ imm = #-2
|
|
b24: ldr r0, [sp, #8]
|
|
b26: str r0, [sp, #52]
|
|
b28: ldr r0, [r0]
|
|
b2a: str r0, [sp]
|
|
b2c: b 0xb2e <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h1da809e59f2f513d+0x1c> @ imm = #-2
|
|
b2e: ldr r1, [sp, #4]
|
|
b30: ldr r0, [sp]
|
|
b32: ldr r2, [sp, #12]
|
|
b34: ldr r2, [r2]
|
|
b36: orrs r0, r2
|
|
b38: str r1, [sp, #36]
|
|
b3a: str r0, [sp, #40]
|
|
b3c: str r1, [sp, #44]
|
|
b3e: str r0, [sp, #48]
|
|
b40: str r0, [r1]
|
|
b42: b 0xb44 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h1da809e59f2f513d+0x32> @ imm = #-2
|
|
b44: ldr r0, [sp, #4]
|
|
b46: str r0, [sp, #32]
|
|
b48: b 0xb4a <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h1da809e59f2f513d+0x38> @ imm = #-2
|
|
b4a: ldr r0, [sp, #4]
|
|
b4c: add sp, #56
|
|
b4e: bx lr
|
|
|
|
00000b50 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h1dbb3ecca469fca4>:
|
|
b50: sub sp, #56
|
|
b52: str r2, [sp, #4]
|
|
b54: str r1, [sp, #8]
|
|
b56: str r0, [sp, #12]
|
|
b58: str r0, [sp, #16]
|
|
b5a: str r1, [sp, #20]
|
|
b5c: str r2, [sp, #24]
|
|
b5e: str r1, [sp, #28]
|
|
b60: b 0xb62 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h1dbb3ecca469fca4+0x12> @ imm = #-2
|
|
b62: ldr r0, [sp, #8]
|
|
b64: str r0, [sp, #52]
|
|
b66: ldr r0, [r0]
|
|
b68: str r0, [sp]
|
|
b6a: b 0xb6c <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h1dbb3ecca469fca4+0x1c> @ imm = #-2
|
|
b6c: ldr r1, [sp, #4]
|
|
b6e: ldr r0, [sp]
|
|
b70: ldr r2, [sp, #12]
|
|
b72: ldr r2, [r2]
|
|
b74: orrs r0, r2
|
|
b76: str r1, [sp, #36]
|
|
b78: str r0, [sp, #40]
|
|
b7a: str r1, [sp, #44]
|
|
b7c: str r0, [sp, #48]
|
|
b7e: str r0, [r1]
|
|
b80: b 0xb82 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h1dbb3ecca469fca4+0x32> @ imm = #-2
|
|
b82: ldr r0, [sp, #4]
|
|
b84: str r0, [sp, #32]
|
|
b86: b 0xb88 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h1dbb3ecca469fca4+0x38> @ imm = #-2
|
|
b88: ldr r0, [sp, #4]
|
|
b8a: add sp, #56
|
|
b8c: bx lr
|
|
|
|
00000b8e <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2a2e7ae71d5d4391>:
|
|
b8e: sub sp, #32
|
|
b90: str r1, [sp]
|
|
b92: str r0, [sp, #4]
|
|
b94: str r1, [sp, #8]
|
|
b96: ldr r0, [r0]
|
|
b98: str r1, [sp, #12]
|
|
b9a: str r0, [sp, #16]
|
|
b9c: str r1, [sp, #20]
|
|
b9e: str r0, [sp, #24]
|
|
ba0: str r0, [r1]
|
|
ba2: b 0xba4 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2a2e7ae71d5d4391+0x16> @ imm = #-2
|
|
ba4: ldr r0, [sp]
|
|
ba6: str r0, [sp, #28]
|
|
ba8: b 0xbaa <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2a2e7ae71d5d4391+0x1c> @ imm = #-2
|
|
baa: ldr r0, [sp]
|
|
bac: add sp, #32
|
|
bae: bx lr
|
|
|
|
00000bb0 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2a85ec3a68a3780a>:
|
|
bb0: sub sp, #56
|
|
bb2: str r2, [sp, #4]
|
|
bb4: str r1, [sp, #8]
|
|
bb6: str r0, [sp, #12]
|
|
bb8: str r0, [sp, #16]
|
|
bba: str r1, [sp, #20]
|
|
bbc: str r2, [sp, #24]
|
|
bbe: str r1, [sp, #28]
|
|
bc0: b 0xbc2 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2a85ec3a68a3780a+0x12> @ imm = #-2
|
|
bc2: ldr r0, [sp, #8]
|
|
bc4: str r0, [sp, #52]
|
|
bc6: ldr r0, [r0]
|
|
bc8: str r0, [sp]
|
|
bca: b 0xbcc <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2a85ec3a68a3780a+0x1c> @ imm = #-2
|
|
bcc: ldr r1, [sp, #4]
|
|
bce: ldr r0, [sp]
|
|
bd0: ldr r2, [sp, #12]
|
|
bd2: ldr r2, [r2]
|
|
bd4: bics r0, r2
|
|
bd6: str r1, [sp, #36]
|
|
bd8: str r0, [sp, #40]
|
|
bda: str r1, [sp, #44]
|
|
bdc: str r0, [sp, #48]
|
|
bde: str r0, [r1]
|
|
be0: b 0xbe2 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2a85ec3a68a3780a+0x32> @ imm = #-2
|
|
be2: ldr r0, [sp, #4]
|
|
be4: str r0, [sp, #32]
|
|
be6: b 0xbe8 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2a85ec3a68a3780a+0x38> @ imm = #-2
|
|
be8: ldr r0, [sp, #4]
|
|
bea: add sp, #56
|
|
bec: bx lr
|
|
|
|
00000bee <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2b7975d046532670>:
|
|
bee: sub sp, #156
|
|
bf0: str r1, [sp, #16]
|
|
bf2: str r0, [sp, #20]
|
|
bf4: str r1, [sp, #28]
|
|
bf6: str r1, [sp, #36]
|
|
bf8: str r1, [sp, #32]
|
|
bfa: ldr r0, [sp, #32]
|
|
bfc: str r0, [sp, #24]
|
|
bfe: b 0xc00 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2b7975d046532670+0x12> @ imm = #-2
|
|
c00: ldr r1, [sp, #24]
|
|
c02: ldr r0, [sp, #20]
|
|
c04: ldr r0, [r0]
|
|
c06: ldrb r2, [r0]
|
|
c08: str r1, [sp, #140]
|
|
c0a: add r0, sp, #144
|
|
c0c: strb r2, [r0]
|
|
c0e: str r1, [sp, #148]
|
|
c10: ldr r0, [r1]
|
|
c12: movs r3, #1
|
|
c14: lsls r3, r3, #8
|
|
c16: bics r0, r3
|
|
c18: lsls r2, r2, #8
|
|
c1a: str r1, [sp, #152]
|
|
c1c: orrs r0, r2
|
|
c1e: str r0, [r1]
|
|
c20: b 0xc22 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2b7975d046532670+0x34> @ imm = #-2
|
|
c22: ldr r0, [sp, #16]
|
|
c24: str r0, [sp, #136]
|
|
c26: str r0, [sp, #132]
|
|
c28: ldr r0, [sp, #132]
|
|
c2a: str r0, [sp, #12]
|
|
c2c: b 0xc2e <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2b7975d046532670+0x40> @ imm = #-2
|
|
c2e: ldr r1, [sp, #12]
|
|
c30: ldr r0, [sp, #20]
|
|
c32: ldr r0, [r0, #4]
|
|
c34: ldrb r2, [r0]
|
|
c36: str r1, [sp, #116]
|
|
c38: add r0, sp, #120
|
|
c3a: strb r2, [r0]
|
|
c3c: str r1, [sp, #124]
|
|
c3e: ldr r0, [r1]
|
|
c40: movs r3, #1
|
|
c42: lsls r3, r3, #11
|
|
c44: bics r0, r3
|
|
c46: lsls r2, r2, #11
|
|
c48: str r1, [sp, #128]
|
|
c4a: orrs r0, r2
|
|
c4c: str r0, [r1]
|
|
c4e: b 0xc50 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2b7975d046532670+0x62> @ imm = #-2
|
|
c50: ldr r0, [sp, #16]
|
|
c52: str r0, [sp, #112]
|
|
c54: str r0, [sp, #108]
|
|
c56: ldr r0, [sp, #108]
|
|
c58: str r0, [sp, #8]
|
|
c5a: b 0xc5c <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2b7975d046532670+0x6e> @ imm = #-2
|
|
c5c: ldr r1, [sp, #8]
|
|
c5e: ldr r0, [sp, #20]
|
|
c60: ldr r0, [r0, #8]
|
|
c62: ldrb r2, [r0]
|
|
c64: str r1, [sp, #92]
|
|
c66: add r0, sp, #96
|
|
c68: strb r2, [r0]
|
|
c6a: str r1, [sp, #100]
|
|
c6c: ldr r0, [r1]
|
|
c6e: movs r3, #1
|
|
c70: lsls r3, r3, #10
|
|
c72: bics r0, r3
|
|
c74: lsls r2, r2, #10
|
|
c76: str r1, [sp, #104]
|
|
c78: orrs r0, r2
|
|
c7a: str r0, [r1]
|
|
c7c: b 0xc7e <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2b7975d046532670+0x90> @ imm = #-2
|
|
c7e: ldr r0, [sp, #16]
|
|
c80: str r0, [sp, #88]
|
|
c82: str r0, [sp, #84]
|
|
c84: ldr r0, [sp, #84]
|
|
c86: str r0, [sp, #4]
|
|
c88: b 0xc8a <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2b7975d046532670+0x9c> @ imm = #-2
|
|
c8a: ldr r1, [sp, #4]
|
|
c8c: ldr r0, [sp, #20]
|
|
c8e: ldr r0, [r0, #12]
|
|
c90: ldrb r2, [r0]
|
|
c92: str r1, [sp, #68]
|
|
c94: add r0, sp, #72
|
|
c96: strb r2, [r0]
|
|
c98: str r1, [sp, #76]
|
|
c9a: ldr r0, [r1]
|
|
c9c: movs r3, #128
|
|
c9e: bics r0, r3
|
|
ca0: lsls r2, r2, #7
|
|
ca2: str r1, [sp, #80]
|
|
ca4: orrs r0, r2
|
|
ca6: str r0, [r1]
|
|
ca8: b 0xcaa <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2b7975d046532670+0xbc> @ imm = #-2
|
|
caa: ldr r0, [sp, #16]
|
|
cac: str r0, [sp, #64]
|
|
cae: str r0, [sp, #60]
|
|
cb0: ldr r0, [sp, #60]
|
|
cb2: str r0, [sp]
|
|
cb4: b 0xcb6 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2b7975d046532670+0xc8> @ imm = #-2
|
|
cb6: ldr r1, [sp]
|
|
cb8: ldr r0, [sp, #20]
|
|
cba: ldr r0, [r0, #16]
|
|
cbc: ldrb r2, [r0]
|
|
cbe: str r1, [sp, #44]
|
|
cc0: add r0, sp, #48
|
|
cc2: strb r2, [r0]
|
|
cc4: str r1, [sp, #52]
|
|
cc6: ldr r0, [r1]
|
|
cc8: movs r3, #7
|
|
cca: lsls r3, r3, #13
|
|
ccc: bics r0, r3
|
|
cce: lsls r2, r2, #29
|
|
cd0: lsrs r2, r2, #16
|
|
cd2: str r1, [sp, #56]
|
|
cd4: adds r0, r0, r2
|
|
cd6: str r0, [r1]
|
|
cd8: b 0xcda <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2b7975d046532670+0xec> @ imm = #-2
|
|
cda: ldr r0, [sp]
|
|
cdc: str r0, [sp, #40]
|
|
cde: b 0xce0 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h2b7975d046532670+0xf2> @ imm = #-2
|
|
ce0: ldr r0, [sp]
|
|
ce2: add sp, #156
|
|
ce4: bx lr
|
|
|
|
00000ce6 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h508745a5edd80e9e>:
|
|
ce6: sub sp, #32
|
|
ce8: str r1, [sp]
|
|
cea: str r0, [sp, #4]
|
|
cec: str r1, [sp, #8]
|
|
cee: ldr r0, [r0]
|
|
cf0: str r1, [sp, #12]
|
|
cf2: str r0, [sp, #16]
|
|
cf4: str r1, [sp, #20]
|
|
cf6: str r0, [sp, #24]
|
|
cf8: str r0, [r1]
|
|
cfa: b 0xcfc <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h508745a5edd80e9e+0x16> @ imm = #-2
|
|
cfc: ldr r0, [sp]
|
|
cfe: str r0, [sp, #28]
|
|
d00: b 0xd02 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h508745a5edd80e9e+0x1c> @ imm = #-2
|
|
d02: ldr r0, [sp]
|
|
d04: add sp, #32
|
|
d06: bx lr
|
|
|
|
00000d08 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h596b187473cdcc6a>:
|
|
d08: sub sp, #32
|
|
d0a: str r1, [sp]
|
|
d0c: str r0, [sp, #4]
|
|
d0e: str r1, [sp, #8]
|
|
d10: ldr r0, [r0]
|
|
d12: str r1, [sp, #12]
|
|
d14: str r0, [sp, #16]
|
|
d16: str r1, [sp, #20]
|
|
d18: str r0, [sp, #24]
|
|
d1a: str r0, [r1]
|
|
d1c: b 0xd1e <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h596b187473cdcc6a+0x16> @ imm = #-2
|
|
d1e: ldr r0, [sp]
|
|
d20: str r0, [sp, #28]
|
|
d22: b 0xd24 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h596b187473cdcc6a+0x1c> @ imm = #-2
|
|
d24: ldr r0, [sp]
|
|
d26: add sp, #32
|
|
d28: bx lr
|
|
|
|
00000d2a <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h65afbe282fc9a675>:
|
|
d2a: sub sp, #56
|
|
d2c: str r2, [sp, #4]
|
|
d2e: str r1, [sp, #8]
|
|
d30: str r0, [sp, #12]
|
|
d32: str r0, [sp, #16]
|
|
d34: str r1, [sp, #20]
|
|
d36: str r2, [sp, #24]
|
|
d38: str r1, [sp, #28]
|
|
d3a: b 0xd3c <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h65afbe282fc9a675+0x12> @ imm = #-2
|
|
d3c: ldr r0, [sp, #8]
|
|
d3e: str r0, [sp, #52]
|
|
d40: ldr r0, [r0]
|
|
d42: str r0, [sp]
|
|
d44: b 0xd46 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h65afbe282fc9a675+0x1c> @ imm = #-2
|
|
d46: ldr r1, [sp, #4]
|
|
d48: ldr r0, [sp]
|
|
d4a: ldr r2, [sp, #12]
|
|
d4c: ldr r2, [r2]
|
|
d4e: orrs r0, r2
|
|
d50: str r1, [sp, #36]
|
|
d52: str r0, [sp, #40]
|
|
d54: str r1, [sp, #44]
|
|
d56: str r0, [sp, #48]
|
|
d58: str r0, [r1]
|
|
d5a: b 0xd5c <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h65afbe282fc9a675+0x32> @ imm = #-2
|
|
d5c: ldr r0, [sp, #4]
|
|
d5e: str r0, [sp, #32]
|
|
d60: b 0xd62 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h65afbe282fc9a675+0x38> @ imm = #-2
|
|
d62: ldr r0, [sp, #4]
|
|
d64: add sp, #56
|
|
d66: bx lr
|
|
|
|
00000d68 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h71331b163ae8c41a>:
|
|
d68: sub sp, #56
|
|
d6a: str r2, [sp, #4]
|
|
d6c: str r1, [sp, #8]
|
|
d6e: str r0, [sp, #12]
|
|
d70: str r0, [sp, #16]
|
|
d72: str r1, [sp, #20]
|
|
d74: str r2, [sp, #24]
|
|
d76: str r1, [sp, #28]
|
|
d78: b 0xd7a <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h71331b163ae8c41a+0x12> @ imm = #-2
|
|
d7a: ldr r0, [sp, #8]
|
|
d7c: str r0, [sp, #52]
|
|
d7e: ldr r0, [r0]
|
|
d80: str r0, [sp]
|
|
d82: b 0xd84 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h71331b163ae8c41a+0x1c> @ imm = #-2
|
|
d84: ldr r1, [sp, #4]
|
|
d86: ldr r0, [sp]
|
|
d88: ldr r2, [sp, #12]
|
|
d8a: ldr r2, [r2]
|
|
d8c: orrs r0, r2
|
|
d8e: str r1, [sp, #36]
|
|
d90: str r0, [sp, #40]
|
|
d92: str r1, [sp, #44]
|
|
d94: str r0, [sp, #48]
|
|
d96: str r0, [r1]
|
|
d98: b 0xd9a <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h71331b163ae8c41a+0x32> @ imm = #-2
|
|
d9a: ldr r0, [sp, #4]
|
|
d9c: str r0, [sp, #32]
|
|
d9e: b 0xda0 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h71331b163ae8c41a+0x38> @ imm = #-2
|
|
da0: ldr r0, [sp, #4]
|
|
da2: add sp, #56
|
|
da4: bx lr
|
|
|
|
00000da6 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h79f484a6be3139a3>:
|
|
da6: sub sp, #156
|
|
da8: str r1, [sp, #16]
|
|
daa: str r0, [sp, #20]
|
|
dac: str r1, [sp, #28]
|
|
dae: str r1, [sp, #36]
|
|
db0: str r1, [sp, #32]
|
|
db2: ldr r0, [sp, #32]
|
|
db4: str r0, [sp, #24]
|
|
db6: b 0xdb8 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h79f484a6be3139a3+0x12> @ imm = #-2
|
|
db8: ldr r1, [sp, #24]
|
|
dba: ldr r0, [sp, #20]
|
|
dbc: ldr r0, [r0]
|
|
dbe: ldrb r2, [r0]
|
|
dc0: str r1, [sp, #140]
|
|
dc2: add r0, sp, #144
|
|
dc4: strb r2, [r0]
|
|
dc6: str r1, [sp, #148]
|
|
dc8: ldr r0, [r1]
|
|
dca: movs r3, #1
|
|
dcc: lsls r3, r3, #8
|
|
dce: bics r0, r3
|
|
dd0: lsls r2, r2, #8
|
|
dd2: str r1, [sp, #152]
|
|
dd4: orrs r0, r2
|
|
dd6: str r0, [r1]
|
|
dd8: b 0xdda <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h79f484a6be3139a3+0x34> @ imm = #-2
|
|
dda: ldr r0, [sp, #16]
|
|
ddc: str r0, [sp, #136]
|
|
dde: str r0, [sp, #132]
|
|
de0: ldr r0, [sp, #132]
|
|
de2: str r0, [sp, #12]
|
|
de4: b 0xde6 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h79f484a6be3139a3+0x40> @ imm = #-2
|
|
de6: ldr r1, [sp, #12]
|
|
de8: ldr r0, [sp, #20]
|
|
dea: ldr r0, [r0, #4]
|
|
dec: ldrb r2, [r0]
|
|
dee: str r1, [sp, #116]
|
|
df0: add r0, sp, #120
|
|
df2: strb r2, [r0]
|
|
df4: str r1, [sp, #124]
|
|
df6: ldr r0, [r1]
|
|
df8: movs r3, #1
|
|
dfa: lsls r3, r3, #11
|
|
dfc: bics r0, r3
|
|
dfe: lsls r2, r2, #11
|
|
e00: str r1, [sp, #128]
|
|
e02: orrs r0, r2
|
|
e04: str r0, [r1]
|
|
e06: b 0xe08 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h79f484a6be3139a3+0x62> @ imm = #-2
|
|
e08: ldr r0, [sp, #16]
|
|
e0a: str r0, [sp, #112]
|
|
e0c: str r0, [sp, #108]
|
|
e0e: ldr r0, [sp, #108]
|
|
e10: str r0, [sp, #8]
|
|
e12: b 0xe14 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h79f484a6be3139a3+0x6e> @ imm = #-2
|
|
e14: ldr r1, [sp, #8]
|
|
e16: ldr r0, [sp, #20]
|
|
e18: ldr r0, [r0, #8]
|
|
e1a: ldrb r2, [r0]
|
|
e1c: str r1, [sp, #92]
|
|
e1e: add r0, sp, #96
|
|
e20: strb r2, [r0]
|
|
e22: str r1, [sp, #100]
|
|
e24: ldr r0, [r1]
|
|
e26: movs r3, #1
|
|
e28: lsls r3, r3, #10
|
|
e2a: bics r0, r3
|
|
e2c: lsls r2, r2, #10
|
|
e2e: str r1, [sp, #104]
|
|
e30: orrs r0, r2
|
|
e32: str r0, [r1]
|
|
e34: b 0xe36 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h79f484a6be3139a3+0x90> @ imm = #-2
|
|
e36: ldr r0, [sp, #16]
|
|
e38: str r0, [sp, #88]
|
|
e3a: str r0, [sp, #84]
|
|
e3c: ldr r0, [sp, #84]
|
|
e3e: str r0, [sp, #4]
|
|
e40: b 0xe42 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h79f484a6be3139a3+0x9c> @ imm = #-2
|
|
e42: ldr r1, [sp, #4]
|
|
e44: ldr r0, [sp, #20]
|
|
e46: ldr r0, [r0, #12]
|
|
e48: ldrb r2, [r0]
|
|
e4a: str r1, [sp, #68]
|
|
e4c: add r0, sp, #72
|
|
e4e: strb r2, [r0]
|
|
e50: str r1, [sp, #76]
|
|
e52: ldr r0, [r1]
|
|
e54: movs r3, #128
|
|
e56: bics r0, r3
|
|
e58: lsls r2, r2, #7
|
|
e5a: str r1, [sp, #80]
|
|
e5c: orrs r0, r2
|
|
e5e: str r0, [r1]
|
|
e60: b 0xe62 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h79f484a6be3139a3+0xbc> @ imm = #-2
|
|
e62: ldr r0, [sp, #16]
|
|
e64: str r0, [sp, #64]
|
|
e66: str r0, [sp, #60]
|
|
e68: ldr r0, [sp, #60]
|
|
e6a: str r0, [sp]
|
|
e6c: b 0xe6e <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h79f484a6be3139a3+0xc8> @ imm = #-2
|
|
e6e: ldr r1, [sp]
|
|
e70: ldr r0, [sp, #20]
|
|
e72: ldr r0, [r0, #16]
|
|
e74: ldrb r2, [r0]
|
|
e76: str r1, [sp, #44]
|
|
e78: add r0, sp, #48
|
|
e7a: strb r2, [r0]
|
|
e7c: str r1, [sp, #52]
|
|
e7e: ldr r0, [r1]
|
|
e80: movs r3, #7
|
|
e82: lsls r3, r3, #13
|
|
e84: bics r0, r3
|
|
e86: lsls r2, r2, #29
|
|
e88: lsrs r2, r2, #16
|
|
e8a: str r1, [sp, #56]
|
|
e8c: adds r0, r0, r2
|
|
e8e: str r0, [r1]
|
|
e90: b 0xe92 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h79f484a6be3139a3+0xec> @ imm = #-2
|
|
e92: ldr r0, [sp]
|
|
e94: str r0, [sp, #40]
|
|
e96: b 0xe98 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h79f484a6be3139a3+0xf2> @ imm = #-2
|
|
e98: ldr r0, [sp]
|
|
e9a: add sp, #156
|
|
e9c: bx lr
|
|
|
|
00000e9e <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h89bc1eccc2486d81>:
|
|
e9e: sub sp, #156
|
|
ea0: str r1, [sp, #16]
|
|
ea2: str r0, [sp, #20]
|
|
ea4: str r1, [sp, #28]
|
|
ea6: str r1, [sp, #36]
|
|
ea8: str r1, [sp, #32]
|
|
eaa: ldr r0, [sp, #32]
|
|
eac: str r0, [sp, #24]
|
|
eae: b 0xeb0 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h89bc1eccc2486d81+0x12> @ imm = #-2
|
|
eb0: ldr r1, [sp, #24]
|
|
eb2: ldr r0, [sp, #20]
|
|
eb4: ldr r0, [r0]
|
|
eb6: ldrb r2, [r0]
|
|
eb8: str r1, [sp, #140]
|
|
eba: add r0, sp, #144
|
|
ebc: strb r2, [r0]
|
|
ebe: str r1, [sp, #148]
|
|
ec0: ldr r0, [r1]
|
|
ec2: movs r3, #1
|
|
ec4: lsls r3, r3, #8
|
|
ec6: bics r0, r3
|
|
ec8: lsls r2, r2, #8
|
|
eca: str r1, [sp, #152]
|
|
ecc: orrs r0, r2
|
|
ece: str r0, [r1]
|
|
ed0: b 0xed2 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h89bc1eccc2486d81+0x34> @ imm = #-2
|
|
ed2: ldr r0, [sp, #16]
|
|
ed4: str r0, [sp, #136]
|
|
ed6: str r0, [sp, #132]
|
|
ed8: ldr r0, [sp, #132]
|
|
eda: str r0, [sp, #12]
|
|
edc: b 0xede <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h89bc1eccc2486d81+0x40> @ imm = #-2
|
|
ede: ldr r1, [sp, #12]
|
|
ee0: ldr r0, [sp, #20]
|
|
ee2: ldr r0, [r0, #4]
|
|
ee4: ldrb r2, [r0]
|
|
ee6: str r1, [sp, #116]
|
|
ee8: add r0, sp, #120
|
|
eea: strb r2, [r0]
|
|
eec: str r1, [sp, #124]
|
|
eee: ldr r0, [r1]
|
|
ef0: movs r3, #1
|
|
ef2: lsls r3, r3, #11
|
|
ef4: bics r0, r3
|
|
ef6: lsls r2, r2, #11
|
|
ef8: str r1, [sp, #128]
|
|
efa: orrs r0, r2
|
|
efc: str r0, [r1]
|
|
efe: b 0xf00 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h89bc1eccc2486d81+0x62> @ imm = #-2
|
|
f00: ldr r0, [sp, #16]
|
|
f02: str r0, [sp, #112]
|
|
f04: str r0, [sp, #108]
|
|
f06: ldr r0, [sp, #108]
|
|
f08: str r0, [sp, #8]
|
|
f0a: b 0xf0c <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h89bc1eccc2486d81+0x6e> @ imm = #-2
|
|
f0c: ldr r1, [sp, #8]
|
|
f0e: ldr r0, [sp, #20]
|
|
f10: ldr r0, [r0, #8]
|
|
f12: ldrb r2, [r0]
|
|
f14: str r1, [sp, #92]
|
|
f16: add r0, sp, #96
|
|
f18: strb r2, [r0]
|
|
f1a: str r1, [sp, #100]
|
|
f1c: ldr r0, [r1]
|
|
f1e: movs r3, #1
|
|
f20: lsls r3, r3, #10
|
|
f22: bics r0, r3
|
|
f24: lsls r2, r2, #10
|
|
f26: str r1, [sp, #104]
|
|
f28: orrs r0, r2
|
|
f2a: str r0, [r1]
|
|
f2c: b 0xf2e <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h89bc1eccc2486d81+0x90> @ imm = #-2
|
|
f2e: ldr r0, [sp, #16]
|
|
f30: str r0, [sp, #88]
|
|
f32: str r0, [sp, #84]
|
|
f34: ldr r0, [sp, #84]
|
|
f36: str r0, [sp, #4]
|
|
f38: b 0xf3a <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h89bc1eccc2486d81+0x9c> @ imm = #-2
|
|
f3a: ldr r1, [sp, #4]
|
|
f3c: ldr r0, [sp, #20]
|
|
f3e: ldr r0, [r0, #12]
|
|
f40: ldrb r2, [r0]
|
|
f42: str r1, [sp, #68]
|
|
f44: add r0, sp, #72
|
|
f46: strb r2, [r0]
|
|
f48: str r1, [sp, #76]
|
|
f4a: ldr r0, [r1]
|
|
f4c: movs r3, #128
|
|
f4e: bics r0, r3
|
|
f50: lsls r2, r2, #7
|
|
f52: str r1, [sp, #80]
|
|
f54: orrs r0, r2
|
|
f56: str r0, [r1]
|
|
f58: b 0xf5a <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h89bc1eccc2486d81+0xbc> @ imm = #-2
|
|
f5a: ldr r0, [sp, #16]
|
|
f5c: str r0, [sp, #64]
|
|
f5e: str r0, [sp, #60]
|
|
f60: ldr r0, [sp, #60]
|
|
f62: str r0, [sp]
|
|
f64: b 0xf66 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h89bc1eccc2486d81+0xc8> @ imm = #-2
|
|
f66: ldr r1, [sp]
|
|
f68: ldr r0, [sp, #20]
|
|
f6a: ldr r0, [r0, #16]
|
|
f6c: ldrb r2, [r0]
|
|
f6e: str r1, [sp, #44]
|
|
f70: add r0, sp, #48
|
|
f72: strb r2, [r0]
|
|
f74: str r1, [sp, #52]
|
|
f76: ldr r0, [r1]
|
|
f78: movs r3, #7
|
|
f7a: lsls r3, r3, #13
|
|
f7c: bics r0, r3
|
|
f7e: lsls r2, r2, #29
|
|
f80: lsrs r2, r2, #16
|
|
f82: str r1, [sp, #56]
|
|
f84: adds r0, r0, r2
|
|
f86: str r0, [r1]
|
|
f88: b 0xf8a <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h89bc1eccc2486d81+0xec> @ imm = #-2
|
|
f8a: ldr r0, [sp]
|
|
f8c: str r0, [sp, #40]
|
|
f8e: b 0xf90 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h89bc1eccc2486d81+0xf2> @ imm = #-2
|
|
f90: ldr r0, [sp]
|
|
f92: add sp, #156
|
|
f94: bx lr
|
|
|
|
00000f96 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h9d2e25fa09987069>:
|
|
f96: sub sp, #156
|
|
f98: str r1, [sp, #16]
|
|
f9a: str r0, [sp, #20]
|
|
f9c: str r1, [sp, #28]
|
|
f9e: str r1, [sp, #36]
|
|
fa0: str r1, [sp, #32]
|
|
fa2: ldr r0, [sp, #32]
|
|
fa4: str r0, [sp, #24]
|
|
fa6: b 0xfa8 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h9d2e25fa09987069+0x12> @ imm = #-2
|
|
fa8: ldr r1, [sp, #24]
|
|
faa: ldr r0, [sp, #20]
|
|
fac: ldr r0, [r0]
|
|
fae: ldrb r2, [r0]
|
|
fb0: str r1, [sp, #140]
|
|
fb2: add r0, sp, #144
|
|
fb4: strb r2, [r0]
|
|
fb6: str r1, [sp, #148]
|
|
fb8: ldr r0, [r1]
|
|
fba: movs r3, #1
|
|
fbc: lsls r3, r3, #8
|
|
fbe: bics r0, r3
|
|
fc0: lsls r2, r2, #8
|
|
fc2: str r1, [sp, #152]
|
|
fc4: orrs r0, r2
|
|
fc6: str r0, [r1]
|
|
fc8: b 0xfca <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h9d2e25fa09987069+0x34> @ imm = #-2
|
|
fca: ldr r0, [sp, #16]
|
|
fcc: str r0, [sp, #136]
|
|
fce: str r0, [sp, #132]
|
|
fd0: ldr r0, [sp, #132]
|
|
fd2: str r0, [sp, #12]
|
|
fd4: b 0xfd6 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h9d2e25fa09987069+0x40> @ imm = #-2
|
|
fd6: ldr r1, [sp, #12]
|
|
fd8: ldr r0, [sp, #20]
|
|
fda: ldr r0, [r0, #4]
|
|
fdc: ldrb r2, [r0]
|
|
fde: str r1, [sp, #116]
|
|
fe0: add r0, sp, #120
|
|
fe2: strb r2, [r0]
|
|
fe4: str r1, [sp, #124]
|
|
fe6: ldr r0, [r1]
|
|
fe8: movs r3, #1
|
|
fea: lsls r3, r3, #11
|
|
fec: bics r0, r3
|
|
fee: lsls r2, r2, #11
|
|
ff0: str r1, [sp, #128]
|
|
ff2: orrs r0, r2
|
|
ff4: str r0, [r1]
|
|
ff6: b 0xff8 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h9d2e25fa09987069+0x62> @ imm = #-2
|
|
ff8: ldr r0, [sp, #16]
|
|
ffa: str r0, [sp, #112]
|
|
ffc: str r0, [sp, #108]
|
|
ffe: ldr r0, [sp, #108]
|
|
1000: str r0, [sp, #8]
|
|
1002: b 0x1004 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h9d2e25fa09987069+0x6e> @ imm = #-2
|
|
1004: ldr r1, [sp, #8]
|
|
1006: ldr r0, [sp, #20]
|
|
1008: ldr r0, [r0, #8]
|
|
100a: ldrb r2, [r0]
|
|
100c: str r1, [sp, #92]
|
|
100e: add r0, sp, #96
|
|
1010: strb r2, [r0]
|
|
1012: str r1, [sp, #100]
|
|
1014: ldr r0, [r1]
|
|
1016: movs r3, #1
|
|
1018: lsls r3, r3, #10
|
|
101a: bics r0, r3
|
|
101c: lsls r2, r2, #10
|
|
101e: str r1, [sp, #104]
|
|
1020: orrs r0, r2
|
|
1022: str r0, [r1]
|
|
1024: b 0x1026 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h9d2e25fa09987069+0x90> @ imm = #-2
|
|
1026: ldr r0, [sp, #16]
|
|
1028: str r0, [sp, #88]
|
|
102a: str r0, [sp, #84]
|
|
102c: ldr r0, [sp, #84]
|
|
102e: str r0, [sp, #4]
|
|
1030: b 0x1032 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h9d2e25fa09987069+0x9c> @ imm = #-2
|
|
1032: ldr r1, [sp, #4]
|
|
1034: ldr r0, [sp, #20]
|
|
1036: ldr r0, [r0, #12]
|
|
1038: ldrb r2, [r0]
|
|
103a: str r1, [sp, #68]
|
|
103c: add r0, sp, #72
|
|
103e: strb r2, [r0]
|
|
1040: str r1, [sp, #76]
|
|
1042: ldr r0, [r1]
|
|
1044: movs r3, #128
|
|
1046: bics r0, r3
|
|
1048: lsls r2, r2, #7
|
|
104a: str r1, [sp, #80]
|
|
104c: orrs r0, r2
|
|
104e: str r0, [r1]
|
|
1050: b 0x1052 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h9d2e25fa09987069+0xbc> @ imm = #-2
|
|
1052: ldr r0, [sp, #16]
|
|
1054: str r0, [sp, #64]
|
|
1056: str r0, [sp, #60]
|
|
1058: ldr r0, [sp, #60]
|
|
105a: str r0, [sp]
|
|
105c: b 0x105e <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h9d2e25fa09987069+0xc8> @ imm = #-2
|
|
105e: ldr r1, [sp]
|
|
1060: ldr r0, [sp, #20]
|
|
1062: ldr r0, [r0, #16]
|
|
1064: ldrb r2, [r0]
|
|
1066: str r1, [sp, #44]
|
|
1068: add r0, sp, #48
|
|
106a: strb r2, [r0]
|
|
106c: str r1, [sp, #52]
|
|
106e: ldr r0, [r1]
|
|
1070: movs r3, #7
|
|
1072: lsls r3, r3, #13
|
|
1074: bics r0, r3
|
|
1076: lsls r2, r2, #29
|
|
1078: lsrs r2, r2, #16
|
|
107a: str r1, [sp, #56]
|
|
107c: adds r0, r0, r2
|
|
107e: str r0, [r1]
|
|
1080: b 0x1082 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h9d2e25fa09987069+0xec> @ imm = #-2
|
|
1082: ldr r0, [sp]
|
|
1084: str r0, [sp, #40]
|
|
1086: b 0x1088 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::h9d2e25fa09987069+0xf2> @ imm = #-2
|
|
1088: ldr r0, [sp]
|
|
108a: add sp, #156
|
|
108c: bx lr
|
|
|
|
0000108e <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::haa49f5997c16baa2>:
|
|
108e: sub sp, #56
|
|
1090: str r2, [sp, #4]
|
|
1092: str r1, [sp, #8]
|
|
1094: str r0, [sp, #12]
|
|
1096: str r0, [sp, #16]
|
|
1098: str r1, [sp, #20]
|
|
109a: str r2, [sp, #24]
|
|
109c: str r1, [sp, #28]
|
|
109e: b 0x10a0 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::haa49f5997c16baa2+0x12> @ imm = #-2
|
|
10a0: ldr r0, [sp, #8]
|
|
10a2: str r0, [sp, #52]
|
|
10a4: ldr r0, [r0]
|
|
10a6: str r0, [sp]
|
|
10a8: b 0x10aa <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::haa49f5997c16baa2+0x1c> @ imm = #-2
|
|
10aa: ldr r1, [sp, #4]
|
|
10ac: ldr r0, [sp]
|
|
10ae: ldr r2, [sp, #12]
|
|
10b0: ldr r2, [r2]
|
|
10b2: bics r0, r2
|
|
10b4: str r1, [sp, #36]
|
|
10b6: str r0, [sp, #40]
|
|
10b8: str r1, [sp, #44]
|
|
10ba: str r0, [sp, #48]
|
|
10bc: str r0, [r1]
|
|
10be: b 0x10c0 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::haa49f5997c16baa2+0x32> @ imm = #-2
|
|
10c0: ldr r0, [sp, #4]
|
|
10c2: str r0, [sp, #32]
|
|
10c4: b 0x10c6 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::haa49f5997c16baa2+0x38> @ imm = #-2
|
|
10c6: ldr r0, [sp, #4]
|
|
10c8: add sp, #56
|
|
10ca: bx lr
|
|
|
|
000010cc <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hc973b045d09c06ea>:
|
|
10cc: sub sp, #156
|
|
10ce: str r1, [sp, #16]
|
|
10d0: str r0, [sp, #20]
|
|
10d2: str r1, [sp, #28]
|
|
10d4: str r1, [sp, #36]
|
|
10d6: str r1, [sp, #32]
|
|
10d8: ldr r0, [sp, #32]
|
|
10da: str r0, [sp, #24]
|
|
10dc: b 0x10de <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hc973b045d09c06ea+0x12> @ imm = #-2
|
|
10de: ldr r1, [sp, #24]
|
|
10e0: ldr r0, [sp, #20]
|
|
10e2: ldr r0, [r0]
|
|
10e4: ldrb r2, [r0]
|
|
10e6: str r1, [sp, #140]
|
|
10e8: add r0, sp, #144
|
|
10ea: strb r2, [r0]
|
|
10ec: str r1, [sp, #148]
|
|
10ee: ldr r0, [r1]
|
|
10f0: movs r3, #1
|
|
10f2: lsls r3, r3, #8
|
|
10f4: bics r0, r3
|
|
10f6: lsls r2, r2, #8
|
|
10f8: str r1, [sp, #152]
|
|
10fa: orrs r0, r2
|
|
10fc: str r0, [r1]
|
|
10fe: b 0x1100 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hc973b045d09c06ea+0x34> @ imm = #-2
|
|
1100: ldr r0, [sp, #16]
|
|
1102: str r0, [sp, #136]
|
|
1104: str r0, [sp, #132]
|
|
1106: ldr r0, [sp, #132]
|
|
1108: str r0, [sp, #12]
|
|
110a: b 0x110c <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hc973b045d09c06ea+0x40> @ imm = #-2
|
|
110c: ldr r1, [sp, #12]
|
|
110e: ldr r0, [sp, #20]
|
|
1110: ldr r0, [r0, #4]
|
|
1112: ldrb r2, [r0]
|
|
1114: str r1, [sp, #116]
|
|
1116: add r0, sp, #120
|
|
1118: strb r2, [r0]
|
|
111a: str r1, [sp, #124]
|
|
111c: ldr r0, [r1]
|
|
111e: movs r3, #1
|
|
1120: lsls r3, r3, #11
|
|
1122: bics r0, r3
|
|
1124: lsls r2, r2, #11
|
|
1126: str r1, [sp, #128]
|
|
1128: orrs r0, r2
|
|
112a: str r0, [r1]
|
|
112c: b 0x112e <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hc973b045d09c06ea+0x62> @ imm = #-2
|
|
112e: ldr r0, [sp, #16]
|
|
1130: str r0, [sp, #112]
|
|
1132: str r0, [sp, #108]
|
|
1134: ldr r0, [sp, #108]
|
|
1136: str r0, [sp, #8]
|
|
1138: b 0x113a <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hc973b045d09c06ea+0x6e> @ imm = #-2
|
|
113a: ldr r1, [sp, #8]
|
|
113c: ldr r0, [sp, #20]
|
|
113e: ldr r0, [r0, #8]
|
|
1140: ldrb r2, [r0]
|
|
1142: str r1, [sp, #92]
|
|
1144: add r0, sp, #96
|
|
1146: strb r2, [r0]
|
|
1148: str r1, [sp, #100]
|
|
114a: ldr r0, [r1]
|
|
114c: movs r3, #1
|
|
114e: lsls r3, r3, #10
|
|
1150: bics r0, r3
|
|
1152: lsls r2, r2, #10
|
|
1154: str r1, [sp, #104]
|
|
1156: orrs r0, r2
|
|
1158: str r0, [r1]
|
|
115a: b 0x115c <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hc973b045d09c06ea+0x90> @ imm = #-2
|
|
115c: ldr r0, [sp, #16]
|
|
115e: str r0, [sp, #88]
|
|
1160: str r0, [sp, #84]
|
|
1162: ldr r0, [sp, #84]
|
|
1164: str r0, [sp, #4]
|
|
1166: b 0x1168 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hc973b045d09c06ea+0x9c> @ imm = #-2
|
|
1168: ldr r1, [sp, #4]
|
|
116a: ldr r0, [sp, #20]
|
|
116c: ldr r0, [r0, #12]
|
|
116e: ldrb r2, [r0]
|
|
1170: str r1, [sp, #68]
|
|
1172: add r0, sp, #72
|
|
1174: strb r2, [r0]
|
|
1176: str r1, [sp, #76]
|
|
1178: ldr r0, [r1]
|
|
117a: movs r3, #128
|
|
117c: bics r0, r3
|
|
117e: lsls r2, r2, #7
|
|
1180: str r1, [sp, #80]
|
|
1182: orrs r0, r2
|
|
1184: str r0, [r1]
|
|
1186: b 0x1188 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hc973b045d09c06ea+0xbc> @ imm = #-2
|
|
1188: ldr r0, [sp, #16]
|
|
118a: str r0, [sp, #64]
|
|
118c: str r0, [sp, #60]
|
|
118e: ldr r0, [sp, #60]
|
|
1190: str r0, [sp]
|
|
1192: b 0x1194 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hc973b045d09c06ea+0xc8> @ imm = #-2
|
|
1194: ldr r1, [sp]
|
|
1196: ldr r0, [sp, #20]
|
|
1198: ldr r0, [r0, #16]
|
|
119a: ldrb r2, [r0]
|
|
119c: str r1, [sp, #44]
|
|
119e: add r0, sp, #48
|
|
11a0: strb r2, [r0]
|
|
11a2: str r1, [sp, #52]
|
|
11a4: ldr r0, [r1]
|
|
11a6: movs r3, #7
|
|
11a8: lsls r3, r3, #13
|
|
11aa: bics r0, r3
|
|
11ac: lsls r2, r2, #29
|
|
11ae: lsrs r2, r2, #16
|
|
11b0: str r1, [sp, #56]
|
|
11b2: adds r0, r0, r2
|
|
11b4: str r0, [r1]
|
|
11b6: b 0x11b8 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hc973b045d09c06ea+0xec> @ imm = #-2
|
|
11b8: ldr r0, [sp]
|
|
11ba: str r0, [sp, #40]
|
|
11bc: b 0x11be <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hc973b045d09c06ea+0xf2> @ imm = #-2
|
|
11be: ldr r0, [sp]
|
|
11c0: add sp, #156
|
|
11c2: bx lr
|
|
|
|
000011c4 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hca9233633cf4eef3>:
|
|
11c4: sub sp, #56
|
|
11c6: str r2, [sp, #4]
|
|
11c8: str r1, [sp, #8]
|
|
11ca: str r0, [sp, #12]
|
|
11cc: str r0, [sp, #16]
|
|
11ce: str r1, [sp, #20]
|
|
11d0: str r2, [sp, #24]
|
|
11d2: str r1, [sp, #28]
|
|
11d4: b 0x11d6 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hca9233633cf4eef3+0x12> @ imm = #-2
|
|
11d6: ldr r0, [sp, #8]
|
|
11d8: str r0, [sp, #52]
|
|
11da: ldr r0, [r0]
|
|
11dc: str r0, [sp]
|
|
11de: b 0x11e0 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hca9233633cf4eef3+0x1c> @ imm = #-2
|
|
11e0: ldr r1, [sp, #4]
|
|
11e2: ldr r0, [sp]
|
|
11e4: ldr r2, [sp, #12]
|
|
11e6: ldr r2, [r2]
|
|
11e8: bics r0, r2
|
|
11ea: str r1, [sp, #36]
|
|
11ec: str r0, [sp, #40]
|
|
11ee: str r1, [sp, #44]
|
|
11f0: str r0, [sp, #48]
|
|
11f2: str r0, [r1]
|
|
11f4: b 0x11f6 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hca9233633cf4eef3+0x32> @ imm = #-2
|
|
11f6: ldr r0, [sp, #4]
|
|
11f8: str r0, [sp, #32]
|
|
11fa: b 0x11fc <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hca9233633cf4eef3+0x38> @ imm = #-2
|
|
11fc: ldr r0, [sp, #4]
|
|
11fe: add sp, #56
|
|
1200: bx lr
|
|
|
|
00001202 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hcb4c105b78483c5c>:
|
|
1202: sub sp, #56
|
|
1204: str r2, [sp, #4]
|
|
1206: str r1, [sp, #8]
|
|
1208: str r0, [sp, #12]
|
|
120a: str r0, [sp, #16]
|
|
120c: str r1, [sp, #20]
|
|
120e: str r2, [sp, #24]
|
|
1210: str r1, [sp, #28]
|
|
1212: b 0x1214 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hcb4c105b78483c5c+0x12> @ imm = #-2
|
|
1214: ldr r0, [sp, #8]
|
|
1216: str r0, [sp, #52]
|
|
1218: ldr r0, [r0]
|
|
121a: str r0, [sp]
|
|
121c: b 0x121e <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hcb4c105b78483c5c+0x1c> @ imm = #-2
|
|
121e: ldr r1, [sp, #4]
|
|
1220: ldr r0, [sp]
|
|
1222: ldr r2, [sp, #12]
|
|
1224: ldr r2, [r2]
|
|
1226: bics r0, r2
|
|
1228: str r1, [sp, #36]
|
|
122a: str r0, [sp, #40]
|
|
122c: str r1, [sp, #44]
|
|
122e: str r0, [sp, #48]
|
|
1230: str r0, [r1]
|
|
1232: b 0x1234 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hcb4c105b78483c5c+0x32> @ imm = #-2
|
|
1234: ldr r0, [sp, #4]
|
|
1236: str r0, [sp, #32]
|
|
1238: b 0x123a <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hcb4c105b78483c5c+0x38> @ imm = #-2
|
|
123a: ldr r0, [sp, #4]
|
|
123c: add sp, #56
|
|
123e: bx lr
|
|
|
|
00001240 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hd4d34508588b5aab>:
|
|
1240: sub sp, #56
|
|
1242: str r2, [sp, #4]
|
|
1244: str r1, [sp, #8]
|
|
1246: str r0, [sp, #12]
|
|
1248: str r0, [sp, #16]
|
|
124a: str r1, [sp, #20]
|
|
124c: str r2, [sp, #24]
|
|
124e: str r1, [sp, #28]
|
|
1250: b 0x1252 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hd4d34508588b5aab+0x12> @ imm = #-2
|
|
1252: ldr r0, [sp, #8]
|
|
1254: str r0, [sp, #52]
|
|
1256: ldr r0, [r0]
|
|
1258: str r0, [sp]
|
|
125a: b 0x125c <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hd4d34508588b5aab+0x1c> @ imm = #-2
|
|
125c: ldr r1, [sp, #4]
|
|
125e: ldr r0, [sp]
|
|
1260: ldr r2, [sp, #12]
|
|
1262: ldr r2, [r2]
|
|
1264: bics r0, r2
|
|
1266: str r1, [sp, #36]
|
|
1268: str r0, [sp, #40]
|
|
126a: str r1, [sp, #44]
|
|
126c: str r0, [sp, #48]
|
|
126e: str r0, [r1]
|
|
1270: b 0x1272 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hd4d34508588b5aab+0x32> @ imm = #-2
|
|
1272: ldr r0, [sp, #4]
|
|
1274: str r0, [sp, #32]
|
|
1276: b 0x1278 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hd4d34508588b5aab+0x38> @ imm = #-2
|
|
1278: ldr r0, [sp, #4]
|
|
127a: add sp, #56
|
|
127c: bx lr
|
|
|
|
0000127e <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hdf2551c38320ba25>:
|
|
127e: sub sp, #56
|
|
1280: str r2, [sp, #4]
|
|
1282: str r1, [sp, #8]
|
|
1284: str r0, [sp, #12]
|
|
1286: str r0, [sp, #16]
|
|
1288: str r1, [sp, #20]
|
|
128a: str r2, [sp, #24]
|
|
128c: str r1, [sp, #28]
|
|
128e: b 0x1290 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hdf2551c38320ba25+0x12> @ imm = #-2
|
|
1290: ldr r0, [sp, #8]
|
|
1292: str r0, [sp, #52]
|
|
1294: ldr r0, [r0]
|
|
1296: str r0, [sp]
|
|
1298: b 0x129a <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hdf2551c38320ba25+0x1c> @ imm = #-2
|
|
129a: ldr r1, [sp, #4]
|
|
129c: ldr r0, [sp]
|
|
129e: ldr r2, [sp, #12]
|
|
12a0: ldr r2, [r2]
|
|
12a2: orrs r0, r2
|
|
12a4: str r1, [sp, #36]
|
|
12a6: str r0, [sp, #40]
|
|
12a8: str r1, [sp, #44]
|
|
12aa: str r0, [sp, #48]
|
|
12ac: str r0, [r1]
|
|
12ae: b 0x12b0 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hdf2551c38320ba25+0x32> @ imm = #-2
|
|
12b0: ldr r0, [sp, #4]
|
|
12b2: str r0, [sp, #32]
|
|
12b4: b 0x12b6 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hdf2551c38320ba25+0x38> @ imm = #-2
|
|
12b6: ldr r0, [sp, #4]
|
|
12b8: add sp, #56
|
|
12ba: bx lr
|
|
|
|
000012bc <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hf1632c7badd66729>:
|
|
12bc: sub sp, #32
|
|
12be: str r1, [sp]
|
|
12c0: str r0, [sp, #4]
|
|
12c2: str r1, [sp, #8]
|
|
12c4: ldr r0, [r0]
|
|
12c6: str r1, [sp, #12]
|
|
12c8: str r0, [sp, #16]
|
|
12ca: str r1, [sp, #20]
|
|
12cc: str r0, [sp, #24]
|
|
12ce: str r0, [r1]
|
|
12d0: b 0x12d2 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hf1632c7badd66729+0x16> @ imm = #-2
|
|
12d2: ldr r0, [sp]
|
|
12d4: str r0, [sp, #28]
|
|
12d6: b 0x12d8 <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hf1632c7badd66729+0x1c> @ imm = #-2
|
|
12d8: ldr r0, [sp]
|
|
12da: add sp, #32
|
|
12dc: bx lr
|
|
|
|
000012de <va108xx_hal::gpio::reg::RegisterInterface::write_pin::{{closure}}::hc5bf496c3e19651b>:
|
|
12de: push {r7, lr}
|
|
12e0: add r7, sp, #0
|
|
12e2: sub sp, #40
|
|
12e4: str r1, [sp, #4]
|
|
12e6: str r0, [sp, #12]
|
|
12e8: str r1, [sp, #16]
|
|
12ea: bl 0x3790 <va108xx_hal::gpio::reg::RegisterInterface::mask_32::h8a718548d138d583> @ imm = #9378
|
|
12ee: str r0, [sp, #8]
|
|
12f0: b 0x12f2 <va108xx_hal::gpio::reg::RegisterInterface::write_pin::{{closure}}::hc5bf496c3e19651b+0x14> @ imm = #-2
|
|
12f2: ldr r0, [sp, #8]
|
|
12f4: ldr r1, [sp, #4]
|
|
12f6: str r1, [sp, #20]
|
|
12f8: str r0, [sp, #24]
|
|
12fa: str r1, [sp, #28]
|
|
12fc: str r0, [sp, #32]
|
|
12fe: str r0, [r1]
|
|
1300: b 0x1302 <va108xx_hal::gpio::reg::RegisterInterface::write_pin::{{closure}}::hc5bf496c3e19651b+0x24> @ imm = #-2
|
|
1302: ldr r0, [sp, #4]
|
|
1304: str r0, [sp, #36]
|
|
1306: b 0x1308 <va108xx_hal::gpio::reg::RegisterInterface::write_pin::{{closure}}::hc5bf496c3e19651b+0x2a> @ imm = #-2
|
|
1308: ldr r0, [sp, #4]
|
|
130a: add sp, #40
|
|
130c: pop {r7, pc}
|
|
|
|
0000130e <<dummy_pin::dummy::DummyPin<L> as embedded_hal::digital::v2::OutputPin>::set_low::hb543f757bce9f448>:
|
|
130e: sub sp, #8
|
|
1310: str r0, [sp, #4]
|
|
1312: add sp, #8
|
|
1314: bx lr
|
|
|
|
00001316 <<dummy_pin::dummy::DummyPin<L> as embedded_hal::digital::v2::OutputPin>::set_high::h7185e627752c569a>:
|
|
1316: sub sp, #8
|
|
1318: str r0, [sp, #4]
|
|
131a: add sp, #8
|
|
131c: bx lr
|
|
131e: bmi 0x12ca <va108xx_hal::gpio::reg::RegisterInterface::change_mode::{{closure}}::hf1632c7badd66729+0xe> @ imm = #-88
|
|
|
|
00001320 <<va108xx_hal::gpio::reg::ModeFields as core::convert::From<va108xx_hal::gpio::dynpins::DynPinMode>>::from::hff894586e60702b8>:
|
|
1320: push {r7, lr}
|
|
1322: add r7, sp, #0
|
|
1324: sub sp, #48
|
|
1326: mov r2, r0
|
|
1328: add r0, sp, #12
|
|
132a: strb r2, [r0]
|
|
132c: strb r1, [r0, #1]
|
|
132e: bl 0x140c <<va108xx_hal::gpio::reg::ModeFields as core::default::Default>::default::h15370db3c3e40568> @ imm = #218
|
|
1332: add r2, sp, #32
|
|
1334: strh r1, [r2, #4]
|
|
1336: str r0, [sp, #32]
|
|
1338: ldr r0, [sp, #36]
|
|
133a: add r1, sp, #16
|
|
133c: strh r0, [r1, #4]
|
|
133e: ldr r0, [sp, #32]
|
|
1340: str r0, [sp, #16]
|
|
1342: b 0x1344 <<va108xx_hal::gpio::reg::ModeFields as core::convert::From<va108xx_hal::gpio::dynpins::DynPinMode>>::from::hff894586e60702b8+0x24> @ imm = #-2
|
|
1344: add r0, sp, #12
|
|
1346: ldrb r0, [r0]
|
|
1348: str r0, [sp, #8]
|
|
134a: cmp r0, #0
|
|
134c: beq 0x135c <<va108xx_hal::gpio::reg::ModeFields as core::convert::From<va108xx_hal::gpio::dynpins::DynPinMode>>::from::hff894586e60702b8+0x3c> @ imm = #12
|
|
134e: b 0x1350 <<va108xx_hal::gpio::reg::ModeFields as core::convert::From<va108xx_hal::gpio::dynpins::DynPinMode>>::from::hff894586e60702b8+0x30> @ imm = #-2
|
|
1350: ldr r0, [sp, #8]
|
|
1352: cmp r0, #1
|
|
1354: beq 0x137e <<va108xx_hal::gpio::reg::ModeFields as core::convert::From<va108xx_hal::gpio::dynpins::DynPinMode>>::from::hff894586e60702b8+0x5e> @ imm = #38
|
|
1356: b 0x1358 <<va108xx_hal::gpio::reg::ModeFields as core::convert::From<va108xx_hal::gpio::dynpins::DynPinMode>>::from::hff894586e60702b8+0x38> @ imm = #-2
|
|
1358: b 0x13ac <$t.2> @ imm = #80
|
|
135a: trap
|
|
135c: add r0, sp, #12
|
|
135e: ldrb r1, [r0, #1]
|
|
1360: add r0, sp, #24
|
|
1362: strb r1, [r0]
|
|
1364: add r2, sp, #16
|
|
1366: movs r1, #0
|
|
1368: strb r1, [r2]
|
|
136a: ldrb r0, [r0]
|
|
136c: str r0, [sp, #4]
|
|
136e: cmp r0, #0
|
|
1370: beq 0x13ba <$t.2+0xe> @ imm = #70
|
|
1372: b 0x1374 <<va108xx_hal::gpio::reg::ModeFields as core::convert::From<va108xx_hal::gpio::dynpins::DynPinMode>>::from::hff894586e60702b8+0x54> @ imm = #-2
|
|
1374: ldr r0, [sp, #4]
|
|
1376: cmp r0, #1
|
|
1378: beq 0x13fa <$t.2+0x4e> @ imm = #126
|
|
137a: b 0x137c <<va108xx_hal::gpio::reg::ModeFields as core::convert::From<va108xx_hal::gpio::dynpins::DynPinMode>>::from::hff894586e60702b8+0x5c> @ imm = #-2
|
|
137c: b 0x1402 <$t.2+0x56> @ imm = #130
|
|
137e: add r0, sp, #12
|
|
1380: ldrb r1, [r0, #1]
|
|
1382: add r0, sp, #28
|
|
1384: strb r1, [r0]
|
|
1386: add r2, sp, #16
|
|
1388: movs r1, #1
|
|
138a: strb r1, [r2]
|
|
138c: ldrb r0, [r0]
|
|
138e: str r0, [sp]
|
|
1390: ldr r0, [sp]
|
|
1392: lsls r1, r0, #2
|
|
1394: adr r0, #4 <<va108xx_hal::gpio::reg::ModeFields as core::convert::From<va108xx_hal::gpio::dynpins::DynPinMode>>::from::hff894586e60702b8+0x79>
|
|
1396: ldr r0, [r0, r1]
|
|
1398: mov pc, r0
|
|
139a: mov r8, r8
|
|
|
|
0000139c <$d.1>:
|
|
139c: bb 13 00 00 .word 0x000013bb
|
|
13a0: df 13 00 00 .word 0x000013df
|
|
13a4: e7 13 00 00 .word 0x000013e7
|
|
13a8: ef 13 00 00 .word 0x000013ef
|
|
|
|
000013ac <$t.2>:
|
|
13ac: add r0, sp, #12
|
|
13ae: ldrb r0, [r0, #1]
|
|
13b0: add r1, sp, #44
|
|
13b2: strb r0, [r1]
|
|
13b4: add r1, sp, #16
|
|
13b6: strb r0, [r1, #4]
|
|
13b8: b 0x13ba <$t.2+0xe> @ imm = #-2
|
|
13ba: add r1, sp, #16
|
|
13bc: ldrb r2, [r1]
|
|
13be: ldrb r0, [r1, #1]
|
|
13c0: lsls r0, r0, #8
|
|
13c2: adds r2, r0, r2
|
|
13c4: ldrb r3, [r1, #2]
|
|
13c6: ldrb r0, [r1, #3]
|
|
13c8: lsls r0, r0, #8
|
|
13ca: adds r0, r0, r3
|
|
13cc: lsls r0, r0, #16
|
|
13ce: adds r0, r0, r2
|
|
13d0: ldrb r2, [r1, #4]
|
|
13d2: ldrb r1, [r1, #5]
|
|
13d4: lsls r1, r1, #8
|
|
13d6: adds r1, r1, r2
|
|
13d8: add sp, #48
|
|
13da: pop {r7, pc}
|
|
13dc: trap
|
|
13de: add r1, sp, #16
|
|
13e0: movs r0, #1
|
|
13e2: strb r0, [r1, #1]
|
|
13e4: b 0x13ba <$t.2+0xe> @ imm = #-46
|
|
13e6: add r1, sp, #16
|
|
13e8: movs r0, #1
|
|
13ea: strb r0, [r1, #5]
|
|
13ec: b 0x13ba <$t.2+0xe> @ imm = #-54
|
|
13ee: add r1, sp, #16
|
|
13f0: movs r0, #1
|
|
13f2: strb r0, [r1, #5]
|
|
13f4: strb r0, [r1, #1]
|
|
13f6: b 0x13ba <$t.2+0xe> @ imm = #-64
|
|
13f8: trap
|
|
13fa: add r1, sp, #16
|
|
13fc: movs r0, #1
|
|
13fe: strb r0, [r1, #2]
|
|
1400: b 0x13ba <$t.2+0xe> @ imm = #-74
|
|
1402: add r1, sp, #16
|
|
1404: movs r0, #1
|
|
1406: strb r0, [r1, #2]
|
|
1408: strb r0, [r1, #3]
|
|
140a: b 0x13ba <$t.2+0xe> @ imm = #-84
|
|
|
|
0000140c <<va108xx_hal::gpio::reg::ModeFields as core::default::Default>::default::h15370db3c3e40568>:
|
|
140c: push {r4, r5, r6, r7, lr}
|
|
140e: add r7, sp, #12
|
|
1410: sub sp, #36
|
|
1412: bl 0x57c <<bool as core::default::Default>::default::h6ce1fdee60a85673> @ imm = #-3738
|
|
1416: str r0, [sp, #24]
|
|
1418: b 0x141a <<va108xx_hal::gpio::reg::ModeFields as core::default::Default>::default::h15370db3c3e40568+0xe> @ imm = #-2
|
|
141a: bl 0x57c <<bool as core::default::Default>::default::h6ce1fdee60a85673> @ imm = #-3746
|
|
141e: str r0, [sp, #20]
|
|
1420: b 0x1422 <<va108xx_hal::gpio::reg::ModeFields as core::default::Default>::default::h15370db3c3e40568+0x16> @ imm = #-2
|
|
1422: bl 0x57c <<bool as core::default::Default>::default::h6ce1fdee60a85673> @ imm = #-3754
|
|
1426: str r0, [sp, #16]
|
|
1428: b 0x142a <<va108xx_hal::gpio::reg::ModeFields as core::default::Default>::default::h15370db3c3e40568+0x1e> @ imm = #-2
|
|
142a: bl 0x57c <<bool as core::default::Default>::default::h6ce1fdee60a85673> @ imm = #-3762
|
|
142e: str r0, [sp, #12]
|
|
1430: b 0x1432 <<va108xx_hal::gpio::reg::ModeFields as core::default::Default>::default::h15370db3c3e40568+0x26> @ imm = #-2
|
|
1432: bl 0x578 <<u8 as core::default::Default>::default::hb2792f91b4560cc9> @ imm = #-3774
|
|
1436: str r0, [sp, #8]
|
|
1438: b 0x143a <<va108xx_hal::gpio::reg::ModeFields as core::default::Default>::default::h15370db3c3e40568+0x2e> @ imm = #-2
|
|
143a: bl 0x57c <<bool as core::default::Default>::default::h6ce1fdee60a85673> @ imm = #-3778
|
|
143e: str r0, [sp, #4]
|
|
1440: b 0x1442 <<va108xx_hal::gpio::reg::ModeFields as core::default::Default>::default::h15370db3c3e40568+0x36> @ imm = #-2
|
|
1442: ldr r3, [sp, #8]
|
|
1444: ldr r4, [sp, #12]
|
|
1446: ldr r5, [sp, #16]
|
|
1448: ldr r6, [sp, #20]
|
|
144a: ldr r0, [sp, #24]
|
|
144c: movs r2, #1
|
|
144e: ands r0, r2
|
|
1450: add r1, sp, #28
|
|
1452: strb r0, [r1]
|
|
1454: ldr r0, [sp, #4]
|
|
1456: ands r6, r2
|
|
1458: strb r6, [r1, #1]
|
|
145a: ands r5, r2
|
|
145c: strb r5, [r1, #2]
|
|
145e: ands r4, r2
|
|
1460: strb r4, [r1, #3]
|
|
1462: strb r3, [r1, #4]
|
|
1464: ands r0, r2
|
|
1466: strb r0, [r1, #5]
|
|
1468: ldrb r2, [r1]
|
|
146a: ldrb r0, [r1, #1]
|
|
146c: lsls r0, r0, #8
|
|
146e: adds r2, r0, r2
|
|
1470: ldrb r3, [r1, #2]
|
|
1472: ldrb r0, [r1, #3]
|
|
1474: lsls r0, r0, #8
|
|
1476: adds r0, r0, r3
|
|
1478: lsls r0, r0, #16
|
|
147a: adds r0, r0, r2
|
|
147c: ldrb r2, [r1, #4]
|
|
147e: ldrb r1, [r1, #5]
|
|
1480: lsls r1, r1, #8
|
|
1482: adds r1, r1, r2
|
|
1484: add sp, #36
|
|
1486: pop {r4, r5, r6, r7, pc}
|
|
|
|
00001488 <_ZN112_$LT$max116xx_10bit..Error$LT$SpiE$C$PinE$GT$$u20$as$u20$core..convert..From$LT$max116xx_10bit..AdcError$GT$$GT$4from17h13b2f106daae083dE>:
|
|
1488: sub sp, #8
|
|
148a: add r1, sp, #4
|
|
148c: strb r0, [r1]
|
|
148e: mov r1, sp
|
|
1490: strb r0, [r1]
|
|
1492: ldr r0, [sp]
|
|
1494: add sp, #8
|
|
1496: bx lr
|
|
|
|
00001498 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d>:
|
|
1498: push {r4, r6, r7, lr}
|
|
149a: add r7, sp, #8
|
|
149c: sub sp, #508
|
|
149e: sub sp, #36
|
|
14a0: str r3, [sp, #140]
|
|
14a2: str r2, [sp, #144]
|
|
14a4: mov r2, r1
|
|
14a6: ldr r1, [sp, #144]
|
|
14a8: str r2, [sp, #148]
|
|
14aa: mov r4, r0
|
|
14ac: ldr r0, [sp, #148]
|
|
14ae: str r4, [sp, #152]
|
|
14b0: ldr r2, [r7, #8]
|
|
14b2: str r2, [sp, #156]
|
|
14b4: str r4, [sp, #352]
|
|
14b6: str r0, [sp, #356]
|
|
14b8: str r1, [sp, #360]
|
|
14ba: str r3, [sp, #364]
|
|
14bc: add r3, sp, #368
|
|
14be: strb r2, [r3]
|
|
14c0: bl 0x64c8 <core::slice::<impl [T]>::iter_mut::h0c9d630705430598> @ imm = #20484
|
|
14c4: str r1, [sp, #168]
|
|
14c6: str r0, [sp, #164]
|
|
14c8: b 0x14ca <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x32> @ imm = #-2
|
|
14ca: ldr r0, [sp, #156]
|
|
14cc: uxtb r0, r0
|
|
14ce: adds r1, r0, #1
|
|
14d0: str r1, [sp, #136]
|
|
14d2: uxtb r0, r1
|
|
14d4: cmp r0, r1
|
|
14d6: bne 0x14f2 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x5a> @ imm = #24
|
|
14d8: b 0x14da <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x42> @ imm = #-2
|
|
14da: ldr r1, [sp, #136]
|
|
14dc: add r0, sp, #176
|
|
14de: movs r2, #0
|
|
14e0: strb r2, [r0]
|
|
14e2: strb r1, [r0, #1]
|
|
14e4: ldrb r1, [r0, #1]
|
|
14e6: ldr r0, [sp, #176]
|
|
14e8: bl 0x21e4 <<I as core::iter::traits::collect::IntoIterator>::into_iter::h394fa755b7de161a> @ imm = #3320
|
|
14ec: str r0, [sp, #128]
|
|
14ee: str r1, [sp, #132]
|
|
14f0: b 0x14fe <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x66> @ imm = #10
|
|
14f2: ldr r0, [pc, #1008] <$d.2+0x6>
|
|
14f4: ldr r2, [pc, #1000] <$d.2>
|
|
14f6: movs r1, #28
|
|
14f8: bl 0x8548 <core::panicking::panic::hd188a7f3102defa3> @ imm = #28748
|
|
14fc: trap
|
|
14fe: ldr r0, [sp, #132]
|
|
1500: ldr r2, [sp, #128]
|
|
1502: add r1, sp, #180
|
|
1504: strb r2, [r1]
|
|
1506: strb r0, [r1, #1]
|
|
1508: b 0x150a <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x72> @ imm = #-2
|
|
150a: add r0, sp, #180
|
|
150c: bl 0x21c6 <core::iter::range::<impl core::iter::traits::iterator::Iterator for core::ops::range::Range<A>>::next::hdc3d7bd7b0883915> @ imm = #3254
|
|
1510: mov r2, r1
|
|
1512: add r1, sp, #184
|
|
1514: strb r2, [r1, #1]
|
|
1516: strb r0, [r1]
|
|
1518: b 0x151a <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x82> @ imm = #-2
|
|
151a: add r0, sp, #184
|
|
151c: ldrb r0, [r0]
|
|
151e: lsls r0, r0, #31
|
|
1520: cmp r0, #0
|
|
1522: beq 0x152a <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x92> @ imm = #4
|
|
1524: b 0x1526 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x8e> @ imm = #-2
|
|
1526: b 0x1534 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x9c> @ imm = #10
|
|
1528: trap
|
|
152a: add r0, sp, #164
|
|
152c: bl 0x572c <<core::slice::iter::IterMut<T> as core::iter::traits::iterator::Iterator>::next::hb1dbd48c35961a04> @ imm = #16892
|
|
1530: str r0, [sp, #124]
|
|
1532: b 0x1690 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x1f8> @ imm = #346
|
|
1534: add r0, sp, #184
|
|
1536: ldrb r0, [r0, #1]
|
|
1538: str r0, [sp, #116]
|
|
153a: add r1, sp, #380
|
|
153c: strb r0, [r1]
|
|
153e: add r1, sp, #384
|
|
1540: strb r0, [r1]
|
|
1542: add r1, sp, #388
|
|
1544: strb r0, [r1]
|
|
1546: add r0, sp, #164
|
|
1548: bl 0x572c <<core::slice::iter::IterMut<T> as core::iter::traits::iterator::Iterator>::next::hb1dbd48c35961a04> @ imm = #16864
|
|
154c: str r0, [sp, #120]
|
|
154e: b 0x1550 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0xb8> @ imm = #-2
|
|
1550: ldr r0, [sp, #120]
|
|
1552: add r2, sp, #208
|
|
1554: movs r1, #2
|
|
1556: strb r1, [r2]
|
|
1558: ldr r1, [sp, #208]
|
|
155a: add r2, sp, #204
|
|
155c: strb r1, [r2]
|
|
155e: ldr r1, [sp, #204]
|
|
1560: bl 0xa62 <core::option::Option<T>::ok_or::h7600f9cbeca56c74> @ imm = #-2818
|
|
1564: str r1, [sp, #396]
|
|
1566: str r0, [sp, #392]
|
|
1568: ldr r0, [sp, #396]
|
|
156a: str r0, [sp, #200]
|
|
156c: ldr r0, [sp, #392]
|
|
156e: str r0, [sp, #196]
|
|
1570: b 0x1572 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0xda> @ imm = #-2
|
|
1572: ldr r1, [sp, #200]
|
|
1574: ldr r0, [sp, #196]
|
|
1576: bl 0x410 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h17eaa2cd8a173bf2E> @ imm = #-4458
|
|
157a: str r1, [sp, #404]
|
|
157c: str r0, [sp, #400]
|
|
157e: ldr r0, [sp, #404]
|
|
1580: str r0, [sp, #192]
|
|
1582: ldr r0, [sp, #400]
|
|
1584: str r0, [sp, #188]
|
|
1586: b 0x1588 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0xf0> @ imm = #-2
|
|
1588: add r0, sp, #188
|
|
158a: ldrb r0, [r0]
|
|
158c: lsls r0, r0, #31
|
|
158e: cmp r0, #0
|
|
1590: beq 0x1598 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x100> @ imm = #4
|
|
1592: b 0x1594 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0xfc> @ imm = #-2
|
|
1594: b 0x15b4 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x11c> @ imm = #28
|
|
1596: trap
|
|
1598: ldr r2, [sp, #116]
|
|
159a: ldr r0, [sp, #152]
|
|
159c: ldr r1, [sp, #192]
|
|
159e: str r1, [sp, #412]
|
|
15a0: str r1, [sp, #172]
|
|
15a2: add r3, sp, #216
|
|
15a4: movs r1, #3
|
|
15a6: strb r1, [r3]
|
|
15a8: ldr r1, [sp, #216]
|
|
15aa: bl 0x1d32 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_conversion_byte::hb7ec64df4edb09f6> @ imm = #1924
|
|
15ae: str r0, [sp, #108]
|
|
15b0: str r1, [sp, #112]
|
|
15b2: b 0x15d4 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x13c> @ imm = #30
|
|
15b4: add r0, sp, #188
|
|
15b6: ldrb r0, [r0, #1]
|
|
15b8: add r1, sp, #408
|
|
15ba: strb r0, [r1]
|
|
15bc: bl 0x144 <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hde03a568dc94affdE> @ imm = #-5244
|
|
15c0: uxtb r0, r0
|
|
15c2: add r1, sp, #160
|
|
15c4: strb r0, [r1]
|
|
15c6: b 0x15c8 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x130> @ imm = #-2
|
|
15c8: b 0x15ca <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x132> @ imm = #-2
|
|
15ca: ldr r0, [sp, #160]
|
|
15cc: subs r4, r7, #7
|
|
15ce: subs r4, #1
|
|
15d0: mov sp, r4
|
|
15d2: pop {r4, r6, r7, pc}
|
|
15d4: ldr r1, [sp, #112]
|
|
15d6: ldr r0, [sp, #108]
|
|
15d8: movs r2, #1
|
|
15da: ands r0, r2
|
|
15dc: bl 0x52c <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hd072381b3388b3ddE> @ imm = #-4276
|
|
15e0: mov r2, r1
|
|
15e2: add r1, sp, #212
|
|
15e4: strb r2, [r1, #1]
|
|
15e6: strb r0, [r1]
|
|
15e8: b 0x15ea <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x152> @ imm = #-2
|
|
15ea: add r0, sp, #212
|
|
15ec: ldrb r0, [r0]
|
|
15ee: lsls r0, r0, #31
|
|
15f0: cmp r0, #0
|
|
15f2: beq 0x15fa <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x162> @ imm = #4
|
|
15f4: b 0x15f6 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x15e> @ imm = #-2
|
|
15f6: b 0x1610 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x178> @ imm = #22
|
|
15f8: trap
|
|
15fa: add r0, sp, #212
|
|
15fc: ldrb r0, [r0, #1]
|
|
15fe: add r1, sp, #420
|
|
1600: strb r0, [r1]
|
|
1602: ldr r1, [sp, #172]
|
|
1604: strb r0, [r1]
|
|
1606: add r0, sp, #164
|
|
1608: bl 0x572c <<core::slice::iter::IterMut<T> as core::iter::traits::iterator::Iterator>::next::hb1dbd48c35961a04> @ imm = #16672
|
|
160c: str r0, [sp, #104]
|
|
160e: b 0x1624 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x18c> @ imm = #18
|
|
1610: add r0, sp, #212
|
|
1612: ldrb r0, [r0, #1]
|
|
1614: add r1, sp, #416
|
|
1616: strb r0, [r1]
|
|
1618: bl 0x11e <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17h09721f9c421c6e2bE> @ imm = #-5374
|
|
161c: uxtb r0, r0
|
|
161e: add r1, sp, #160
|
|
1620: strb r0, [r1]
|
|
1622: b 0x15ca <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x132> @ imm = #-92
|
|
1624: ldr r0, [sp, #104]
|
|
1626: add r2, sp, #240
|
|
1628: movs r1, #2
|
|
162a: strb r1, [r2]
|
|
162c: ldr r1, [sp, #240]
|
|
162e: add r2, sp, #236
|
|
1630: strb r1, [r2]
|
|
1632: ldr r1, [sp, #236]
|
|
1634: bl 0xa62 <core::option::Option<T>::ok_or::h7600f9cbeca56c74> @ imm = #-3030
|
|
1638: str r1, [sp, #428]
|
|
163a: str r0, [sp, #424]
|
|
163c: ldr r0, [sp, #428]
|
|
163e: str r0, [sp, #232]
|
|
1640: ldr r0, [sp, #424]
|
|
1642: str r0, [sp, #228]
|
|
1644: b 0x1646 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x1ae> @ imm = #-2
|
|
1646: ldr r1, [sp, #232]
|
|
1648: ldr r0, [sp, #228]
|
|
164a: bl 0x410 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h17eaa2cd8a173bf2E> @ imm = #-4670
|
|
164e: str r1, [sp, #436]
|
|
1650: str r0, [sp, #432]
|
|
1652: ldr r0, [sp, #436]
|
|
1654: str r0, [sp, #224]
|
|
1656: ldr r0, [sp, #432]
|
|
1658: str r0, [sp, #220]
|
|
165a: b 0x165c <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x1c4> @ imm = #-2
|
|
165c: add r0, sp, #220
|
|
165e: ldrb r0, [r0]
|
|
1660: lsls r0, r0, #31
|
|
1662: cmp r0, #0
|
|
1664: beq 0x166c <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x1d4> @ imm = #4
|
|
1666: b 0x1668 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x1d0> @ imm = #-2
|
|
1668: b 0x167a <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x1e2> @ imm = #14
|
|
166a: trap
|
|
166c: ldr r0, [sp, #224]
|
|
166e: str r0, [sp, #444]
|
|
1670: str r0, [sp, #172]
|
|
1672: ldr r1, [sp, #172]
|
|
1674: movs r0, #0
|
|
1676: strb r0, [r1]
|
|
1678: b 0x150a <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x72> @ imm = #-370
|
|
167a: add r0, sp, #220
|
|
167c: ldrb r0, [r0, #1]
|
|
167e: add r1, sp, #440
|
|
1680: strb r0, [r1]
|
|
1682: bl 0x144 <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hde03a568dc94affdE> @ imm = #-5442
|
|
1686: uxtb r0, r0
|
|
1688: add r1, sp, #160
|
|
168a: strb r0, [r1]
|
|
168c: b 0x168e <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x1f6> @ imm = #-2
|
|
168e: b 0x15ca <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x132> @ imm = #-200
|
|
1690: ldr r0, [sp, #124]
|
|
1692: add r2, sp, #264
|
|
1694: movs r1, #2
|
|
1696: strb r1, [r2]
|
|
1698: ldr r1, [sp, #264]
|
|
169a: add r2, sp, #260
|
|
169c: strb r1, [r2]
|
|
169e: ldr r1, [sp, #260]
|
|
16a0: bl 0xa62 <core::option::Option<T>::ok_or::h7600f9cbeca56c74> @ imm = #-3138
|
|
16a4: str r1, [sp, #452]
|
|
16a6: str r0, [sp, #448]
|
|
16a8: ldr r0, [sp, #452]
|
|
16aa: str r0, [sp, #256]
|
|
16ac: ldr r0, [sp, #448]
|
|
16ae: str r0, [sp, #252]
|
|
16b0: b 0x16b2 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x21a> @ imm = #-2
|
|
16b2: ldr r1, [sp, #256]
|
|
16b4: ldr r0, [sp, #252]
|
|
16b6: bl 0x410 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h17eaa2cd8a173bf2E> @ imm = #-4778
|
|
16ba: str r1, [sp, #460]
|
|
16bc: str r0, [sp, #456]
|
|
16be: ldr r0, [sp, #460]
|
|
16c0: str r0, [sp, #248]
|
|
16c2: ldr r0, [sp, #456]
|
|
16c4: str r0, [sp, #244]
|
|
16c6: b 0x16c8 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x230> @ imm = #-2
|
|
16c8: add r0, sp, #244
|
|
16ca: ldrb r0, [r0]
|
|
16cc: lsls r0, r0, #31
|
|
16ce: cmp r0, #0
|
|
16d0: beq 0x16d8 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x240> @ imm = #4
|
|
16d2: b 0x16d4 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x23c> @ imm = #-2
|
|
16d4: b 0x16ec <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x254> @ imm = #20
|
|
16d6: trap
|
|
16d8: ldr r0, [sp, #152]
|
|
16da: ldr r1, [sp, #248]
|
|
16dc: str r1, [sp, #472]
|
|
16de: str r1, [sp, #172]
|
|
16e0: ldr r2, [sp, #172]
|
|
16e2: movs r1, #0
|
|
16e4: strb r1, [r2]
|
|
16e6: bl 0x130e <<dummy_pin::dummy::DummyPin<L> as embedded_hal::digital::v2::OutputPin>::set_low::hb543f757bce9f448> @ imm = #-988
|
|
16ea: b 0x1702 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x26a> @ imm = #20
|
|
16ec: add r0, sp, #244
|
|
16ee: ldrb r0, [r0, #1]
|
|
16f0: add r1, sp, #468
|
|
16f2: strb r0, [r1]
|
|
16f4: bl 0x144 <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hde03a568dc94affdE> @ imm = #-5556
|
|
16f8: uxtb r0, r0
|
|
16fa: add r1, sp, #160
|
|
16fc: strb r0, [r1]
|
|
16fe: b 0x1700 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x268> @ imm = #-2
|
|
1700: b 0x15ca <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x132> @ imm = #-314
|
|
1702: bl 0x30a <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE> @ imm = #-5116
|
|
1706: uxtb r0, r0
|
|
1708: str r0, [sp, #100]
|
|
170a: b 0x170c <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x274> @ imm = #-2
|
|
170c: ldr r0, [sp, #100]
|
|
170e: bl 0x45c <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h338082970efc5187E> @ imm = #-4790
|
|
1712: uxtb r0, r0
|
|
1714: add r1, sp, #268
|
|
1716: strb r0, [r1]
|
|
1718: b 0x171a <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x282> @ imm = #-2
|
|
171a: add r0, sp, #268
|
|
171c: ldrb r0, [r0]
|
|
171e: subs r1, r0, #7
|
|
1720: subs r2, r1, #1
|
|
1722: sbcs r1, r2
|
|
1724: cmp r0, #7
|
|
1726: beq 0x172e <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x296> @ imm = #4
|
|
1728: b 0x172a <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x292> @ imm = #-2
|
|
172a: b 0x1742 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x2aa> @ imm = #20
|
|
172c: trap
|
|
172e: ldr r0, [sp, #156]
|
|
1730: ldr r1, [sp, #152]
|
|
1732: str r1, [sp, #92]
|
|
1734: uxtb r0, r0
|
|
1736: adds r1, r0, #1
|
|
1738: str r1, [sp, #96]
|
|
173a: uxtb r0, r1
|
|
173c: cmp r0, r1
|
|
173e: bne 0x1766 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x2ce> @ imm = #36
|
|
1740: b 0x1756 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x2be> @ imm = #18
|
|
1742: ldr r0, [sp, #268]
|
|
1744: add r1, sp, #476
|
|
1746: strb r0, [r1]
|
|
1748: bl 0x144 <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hde03a568dc94affdE> @ imm = #-5640
|
|
174c: uxtb r0, r0
|
|
174e: add r1, sp, #160
|
|
1750: strb r0, [r1]
|
|
1752: b 0x1754 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x2bc> @ imm = #-2
|
|
1754: b 0x15ca <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x132> @ imm = #-398
|
|
1756: ldr r0, [sp, #96]
|
|
1758: uxtb r0, r0
|
|
175a: adds r1, r0, r0
|
|
175c: str r1, [sp, #88]
|
|
175e: uxtb r0, r1
|
|
1760: cmp r0, r1
|
|
1762: bne 0x1782 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x2ea> @ imm = #28
|
|
1764: b 0x1772 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x2da> @ imm = #10
|
|
1766: ldr r0, [pc, #612] <$d.4+0x12>
|
|
1768: ldr r2, [pc, #624] <$d.4+0x20>
|
|
176a: movs r1, #28
|
|
176c: bl 0x8548 <core::panicking::panic::hd188a7f3102defa3> @ imm = #28120
|
|
1770: trap
|
|
1772: ldr r0, [sp, #88]
|
|
1774: uxtb r0, r0
|
|
1776: adds r1, r0, #1
|
|
1778: str r1, [sp, #84]
|
|
177a: uxtb r0, r1
|
|
177c: cmp r0, r1
|
|
177e: bne 0x17ae <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x316> @ imm = #44
|
|
1780: b 0x178e <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x2f6> @ imm = #10
|
|
1782: ldr r0, [pc, #596] <$d.4+0x1e>
|
|
1784: ldr r2, [pc, #596] <$d.4+0x20>
|
|
1786: movs r1, #33
|
|
1788: bl 0x8548 <core::panicking::panic::hd188a7f3102defa3> @ imm = #28092
|
|
178c: trap
|
|
178e: ldr r1, [sp, #144]
|
|
1790: ldr r0, [sp, #148]
|
|
1792: ldr r2, [sp, #84]
|
|
1794: uxtb r2, r2
|
|
1796: movs r3, #0
|
|
1798: str r3, [sp, #296]
|
|
179a: str r2, [sp, #300]
|
|
179c: ldr r2, [sp, #296]
|
|
179e: ldr r3, [sp, #300]
|
|
17a0: ldr r4, [pc, #536] <$d.4>
|
|
17a2: str r4, [sp]
|
|
17a4: bl 0x22d8 <core::slice::index::<impl core::ops::index::IndexMut<I> for [T]>::index_mut::h8f173158539a9526> @ imm = #2864
|
|
17a8: str r0, [sp, #76]
|
|
17aa: str r1, [sp, #80]
|
|
17ac: b 0x17ba <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x322> @ imm = #10
|
|
17ae: ldr r0, [pc, #540] <$d.4+0x12>
|
|
17b0: ldr r2, [pc, #544] <$d.4+0x18>
|
|
17b2: movs r1, #28
|
|
17b4: bl 0x8548 <core::panicking::panic::hd188a7f3102defa3> @ imm = #28048
|
|
17b8: trap
|
|
17ba: ldr r2, [sp, #80]
|
|
17bc: ldr r1, [sp, #76]
|
|
17be: ldr r0, [sp, #92]
|
|
17c0: bl 0x51ca <<va108xx_hal::spi::SpiBase<va108xx::SPIB> as embedded_hal::blocking::spi::Transfer<u8>>::transfer::h705ad216a8f85d03> @ imm = #14854
|
|
17c4: str r0, [sp, #68]
|
|
17c6: str r1, [sp, #72]
|
|
17c8: b 0x17ca <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x332> @ imm = #-2
|
|
17ca: ldr r2, [sp, #72]
|
|
17cc: ldr r1, [sp, #68]
|
|
17ce: add r0, sp, #284
|
|
17d0: bl 0x2a8 <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h2f75cf6a7249e271E> @ imm = #-5420
|
|
17d4: b 0x17d6 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x33e> @ imm = #-2
|
|
17d6: add r0, sp, #272
|
|
17d8: add r1, sp, #284
|
|
17da: bl 0x4e6 <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17hc3644b3e57563e31E> @ imm = #-4856
|
|
17de: b 0x17e0 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x348> @ imm = #-2
|
|
17e0: add r0, sp, #272
|
|
17e2: ldrb r0, [r0]
|
|
17e4: lsls r0, r0, #31
|
|
17e6: cmp r0, #0
|
|
17e8: beq 0x17f0 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x358> @ imm = #4
|
|
17ea: b 0x17ec <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x354> @ imm = #-2
|
|
17ec: b 0x1808 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x370> @ imm = #24
|
|
17ee: trap
|
|
17f0: ldr r0, [sp, #152]
|
|
17f2: ldr r2, [sp, #276]
|
|
17f4: str r2, [sp, #60]
|
|
17f6: ldr r1, [sp, #280]
|
|
17f8: str r1, [sp, #64]
|
|
17fa: str r2, [sp, #484]
|
|
17fc: str r1, [sp, #488]
|
|
17fe: str r2, [sp, #492]
|
|
1800: str r1, [sp, #496]
|
|
1802: bl 0x1316 <<dummy_pin::dummy::DummyPin<L> as embedded_hal::digital::v2::OutputPin>::set_high::h7185e627752c569a> @ imm = #-1264
|
|
1806: b 0x181e <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x386> @ imm = #20
|
|
1808: add r0, sp, #272
|
|
180a: ldrb r0, [r0, #1]
|
|
180c: add r1, sp, #480
|
|
180e: strb r0, [r1]
|
|
1810: bl 0x144 <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hde03a568dc94affdE> @ imm = #-5840
|
|
1814: uxtb r0, r0
|
|
1816: add r1, sp, #160
|
|
1818: strb r0, [r1]
|
|
181a: b 0x181c <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x384> @ imm = #-2
|
|
181c: b 0x15ca <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x132> @ imm = #-598
|
|
181e: bl 0x30a <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE> @ imm = #-5400
|
|
1822: uxtb r0, r0
|
|
1824: str r0, [sp, #56]
|
|
1826: b 0x1828 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x390> @ imm = #-2
|
|
1828: ldr r0, [sp, #56]
|
|
182a: bl 0x45c <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h338082970efc5187E> @ imm = #-5074
|
|
182e: uxtb r0, r0
|
|
1830: add r1, sp, #304
|
|
1832: strb r0, [r1]
|
|
1834: b 0x1836 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x39e> @ imm = #-2
|
|
1836: add r0, sp, #304
|
|
1838: ldrb r0, [r0]
|
|
183a: subs r1, r0, #7
|
|
183c: subs r2, r1, #1
|
|
183e: sbcs r1, r2
|
|
1840: cmp r0, #7
|
|
1842: beq 0x184a <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x3b2> @ imm = #4
|
|
1844: b 0x1846 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x3ae> @ imm = #-2
|
|
1846: b 0x1858 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x3c0> @ imm = #14
|
|
1848: trap
|
|
184a: ldr r1, [sp, #64]
|
|
184c: ldr r0, [sp, #60]
|
|
184e: bl 0x817c <core::slice::<impl [T]>::iter::hcf5f5b4e98ae1b51> @ imm = #26922
|
|
1852: str r1, [sp, #312]
|
|
1854: str r0, [sp, #308]
|
|
1856: b 0x186c <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x3d4> @ imm = #18
|
|
1858: ldr r0, [sp, #304]
|
|
185a: add r1, sp, #500
|
|
185c: strb r0, [r1]
|
|
185e: bl 0x144 <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hde03a568dc94affdE> @ imm = #-5918
|
|
1862: uxtb r0, r0
|
|
1864: add r1, sp, #160
|
|
1866: strb r0, [r1]
|
|
1868: b 0x186a <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x3d2> @ imm = #-2
|
|
186a: b 0x15ca <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x132> @ imm = #-676
|
|
186c: add r0, sp, #308
|
|
186e: bl 0x82be <<core::slice::iter::Iter<T> as core::iter::traits::iterator::Iterator>::next::h2fbdd815f4eb5b6f> @ imm = #27212
|
|
1872: str r0, [sp, #52]
|
|
1874: b 0x1876 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x3de> @ imm = #-2
|
|
1876: ldr r0, [sp, #52]
|
|
1878: ldr r1, [pc, #324] <$d.4+0x4>
|
|
187a: bl 0x52f4 <core::option::Option<T>::unwrap::hfb7c9ddfaa6dfdbd> @ imm = #14966
|
|
187e: b 0x1880 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x3e8> @ imm = #-2
|
|
1880: ldr r0, [sp, #156]
|
|
1882: uxtb r0, r0
|
|
1884: adds r1, r0, #1
|
|
1886: str r1, [sp, #48]
|
|
1888: uxtb r0, r1
|
|
188a: cmp r0, r1
|
|
188c: bne 0x18a8 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x410> @ imm = #24
|
|
188e: b 0x1890 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x3f8> @ imm = #-2
|
|
1890: ldr r1, [sp, #48]
|
|
1892: add r0, sp, #316
|
|
1894: movs r2, #0
|
|
1896: strb r2, [r0]
|
|
1898: strb r1, [r0, #1]
|
|
189a: ldrb r1, [r0, #1]
|
|
189c: ldr r0, [sp, #316]
|
|
189e: bl 0x21e4 <<I as core::iter::traits::collect::IntoIterator>::into_iter::h394fa755b7de161a> @ imm = #2370
|
|
18a2: str r0, [sp, #40]
|
|
18a4: str r1, [sp, #44]
|
|
18a6: b 0x18b4 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x41c> @ imm = #10
|
|
18a8: ldr r0, [pc, #288] <$d.4+0x10>
|
|
18aa: ldr r2, [pc, #292] <$d.4+0x16>
|
|
18ac: movs r1, #28
|
|
18ae: bl 0x8548 <core::panicking::panic::hd188a7f3102defa3> @ imm = #27798
|
|
18b2: trap
|
|
18b4: ldr r0, [sp, #44]
|
|
18b6: ldr r2, [sp, #40]
|
|
18b8: add r1, sp, #320
|
|
18ba: strb r2, [r1]
|
|
18bc: strb r0, [r1, #1]
|
|
18be: b 0x18c0 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x428> @ imm = #-2
|
|
18c0: add r0, sp, #320
|
|
18c2: bl 0x21c6 <core::iter::range::<impl core::iter::traits::iterator::Iterator for core::ops::range::Range<A>>::next::hdc3d7bd7b0883915> @ imm = #2304
|
|
18c6: mov r2, r1
|
|
18c8: add r1, sp, #324
|
|
18ca: strb r2, [r1, #1]
|
|
18cc: strb r0, [r1]
|
|
18ce: b 0x18d0 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x438> @ imm = #-2
|
|
18d0: add r0, sp, #324
|
|
18d2: ldrb r0, [r0]
|
|
18d4: lsls r0, r0, #31
|
|
18d6: cmp r0, #0
|
|
18d8: beq 0x18e8 <$t.3> @ imm = #12
|
|
18da: b 0x18dc <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x444> @ imm = #-2
|
|
18dc: b 0x18f4 <$t.3+0xc> @ imm = #20
|
|
18de: trap
|
|
|
|
000018e0 <$d.2>:
|
|
18e0: 04 aa 00 00 .word 0x0000aa04
|
|
18e4: 20 aa 00 00 .word 0x0000aa20
|
|
|
|
000018e8 <$t.3>:
|
|
18e8: add r1, sp, #160
|
|
18ea: movs r0, #0
|
|
18ec: strb r0, [r1]
|
|
18ee: movs r0, #7
|
|
18f0: strb r0, [r1]
|
|
18f2: b 0x15ca <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x132> @ imm = #-812
|
|
18f4: ldr r0, [sp, #140]
|
|
18f6: add r1, sp, #324
|
|
18f8: ldrb r1, [r1, #1]
|
|
18fa: add r2, sp, #504
|
|
18fc: strb r1, [r2]
|
|
18fe: add r2, sp, #508
|
|
1900: strb r1, [r2]
|
|
1902: bl 0x57cc <<core::slice::iter::IterMut<T> as core::iter::traits::iterator::Iterator>::next::hcb8505d022ea0231> @ imm = #16070
|
|
1906: str r0, [sp, #36]
|
|
1908: b 0x190a <$t.3+0x22> @ imm = #-2
|
|
190a: ldr r0, [sp, #36]
|
|
190c: add r2, sp, #348
|
|
190e: movs r1, #3
|
|
1910: strb r1, [r2]
|
|
1912: ldr r1, [sp, #348]
|
|
1914: add r2, sp, #344
|
|
1916: strb r1, [r2]
|
|
1918: ldr r1, [sp, #344]
|
|
191a: bl 0xa04 <core::option::Option<T>::ok_or::h5474822a3a86c46c> @ imm = #-3866
|
|
191e: str r1, [sp, #516]
|
|
1920: str r0, [sp, #512]
|
|
1922: ldr r0, [sp, #516]
|
|
1924: str r0, [sp, #340]
|
|
1926: ldr r0, [sp, #512]
|
|
1928: str r0, [sp, #336]
|
|
192a: b 0x192c <$t.3+0x44> @ imm = #-2
|
|
192c: ldr r1, [sp, #340]
|
|
192e: ldr r0, [sp, #336]
|
|
1930: bl 0x49a <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h6af079890abca98aE> @ imm = #-5274
|
|
1934: str r1, [sp, #524]
|
|
1936: str r0, [sp, #520]
|
|
1938: ldr r0, [sp, #524]
|
|
193a: str r0, [sp, #332]
|
|
193c: ldr r0, [sp, #520]
|
|
193e: str r0, [sp, #328]
|
|
1940: b 0x1942 <$t.3+0x5a> @ imm = #-2
|
|
1942: add r0, sp, #328
|
|
1944: ldrb r0, [r0]
|
|
1946: lsls r0, r0, #31
|
|
1948: cmp r0, #0
|
|
194a: beq 0x1952 <$t.3+0x6a> @ imm = #4
|
|
194c: b 0x194e <$t.3+0x66> @ imm = #-2
|
|
194e: b 0x1964 <$t.3+0x7c> @ imm = #18
|
|
1950: trap
|
|
1952: ldr r0, [sp, #332]
|
|
1954: str r0, [sp, #28]
|
|
1956: str r0, [sp, #536]
|
|
1958: str r0, [sp, #540]
|
|
195a: add r0, sp, #308
|
|
195c: bl 0x82be <<core::slice::iter::Iter<T> as core::iter::traits::iterator::Iterator>::next::h2fbdd815f4eb5b6f> @ imm = #26974
|
|
1960: str r0, [sp, #32]
|
|
1962: b 0x197a <$t.3+0x92> @ imm = #20
|
|
1964: add r0, sp, #328
|
|
1966: ldrb r0, [r0, #1]
|
|
1968: add r1, sp, #532
|
|
196a: strb r0, [r1]
|
|
196c: bl 0x144 <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hde03a568dc94affdE> @ imm = #-6188
|
|
1970: uxtb r0, r0
|
|
1972: add r1, sp, #160
|
|
1974: strb r0, [r1]
|
|
1976: b 0x1978 <$t.3+0x90> @ imm = #-2
|
|
1978: b 0x15ca <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x132> @ imm = #-946
|
|
197a: ldr r0, [sp, #32]
|
|
197c: ldr r1, [pc, #68] <$d.4+0x8>
|
|
197e: bl 0x52f4 <core::option::Option<T>::unwrap::hfb7c9ddfaa6dfdbd> @ imm = #14706
|
|
1982: str r0, [sp, #24]
|
|
1984: b 0x1986 <$t.3+0x9e> @ imm = #-2
|
|
1986: ldr r0, [sp, #24]
|
|
1988: ldrb r0, [r0]
|
|
198a: lsls r0, r0, #6
|
|
198c: str r0, [sp, #20]
|
|
198e: b 0x1990 <$t.3+0xa8> @ imm = #-2
|
|
1990: add r0, sp, #308
|
|
1992: bl 0x82be <<core::slice::iter::Iter<T> as core::iter::traits::iterator::Iterator>::next::h2fbdd815f4eb5b6f> @ imm = #26920
|
|
1996: str r0, [sp, #16]
|
|
1998: b 0x199a <$t.3+0xb2> @ imm = #-2
|
|
199a: ldr r0, [sp, #16]
|
|
199c: ldr r1, [pc, #40] <$d.4+0xc>
|
|
199e: bl 0x52f4 <core::option::Option<T>::unwrap::hfb7c9ddfaa6dfdbd> @ imm = #14674
|
|
19a2: str r0, [sp, #12]
|
|
19a4: b 0x19a6 <$t.3+0xbe> @ imm = #-2
|
|
19a6: ldr r0, [sp, #12]
|
|
19a8: ldrb r0, [r0]
|
|
19aa: lsrs r0, r0, #2
|
|
19ac: str r0, [sp, #8]
|
|
19ae: b 0x19b0 <$t.3+0xc8> @ imm = #-2
|
|
19b0: ldr r1, [sp, #28]
|
|
19b2: ldr r2, [sp, #8]
|
|
19b4: ldr r0, [sp, #20]
|
|
19b6: orrs r0, r2
|
|
19b8: strh r0, [r1]
|
|
19ba: b 0x18c0 <max116xx_10bit::Max116xx10Bit<SPI,CS>::read_multiple_channels_0_to_n::h95ec57d91a5a773d+0x428> @ imm = #-254
|
|
|
|
000019bc <$d.4>:
|
|
19bc: 84 aa 00 00 .word 0x0000aa84
|
|
19c0: 94 aa 00 00 .word 0x0000aa94
|
|
19c4: b4 aa 00 00 .word 0x0000aab4
|
|
19c8: c4 aa 00 00 .word 0x0000aac4
|
|
19cc: 20 aa 00 00 .word 0x0000aa20
|
|
19d0: a4 aa 00 00 .word 0x0000aaa4
|
|
19d4: 74 aa 00 00 .word 0x0000aa74
|
|
19d8: 50 aa 00 00 .word 0x0000aa50
|
|
19dc: 3c aa 00 00 .word 0x0000aa3c
|
|
|
|
000019e0 <max116xx_10bit::Max116xx10Bit<SPI,CS>::new::h943c44bd332c47a7>:
|
|
19e0: push {r4, r5, r6, r7, lr}
|
|
19e2: add r7, sp, #12
|
|
19e4: sub sp, #92
|
|
19e6: str r0, [sp, #4]
|
|
19e8: ldr r0, [r1, #8]
|
|
19ea: str r0, [sp, #44]
|
|
19ec: ldr r0, [r1, #4]
|
|
19ee: str r0, [sp, #40]
|
|
19f0: ldr r0, [r1]
|
|
19f2: str r0, [sp, #36]
|
|
19f4: add r1, sp, #60
|
|
19f6: movs r0, #0
|
|
19f8: strb r0, [r1]
|
|
19fa: ldr r0, [sp, #60]
|
|
19fc: bl 0x1cbc <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_results_len::hd3b62b85ca1163d0> @ imm = #700
|
|
1a00: str r0, [sp, #8]
|
|
1a02: b 0x1a04 <max116xx_10bit::Max116xx10Bit<SPI,CS>::new::h943c44bd332c47a7+0x24> @ imm = #-2
|
|
1a04: ldr r0, [sp, #8]
|
|
1a06: add r1, sp, #48
|
|
1a08: movs r2, #3
|
|
1a0a: strb r2, [r1, #4]
|
|
1a0c: movs r2, #1
|
|
1a0e: strb r2, [r1, #5]
|
|
1a10: movs r2, #4
|
|
1a12: strb r2, [r1, #6]
|
|
1a14: strb r2, [r1, #7]
|
|
1a16: strb r0, [r1, #8]
|
|
1a18: movs r0, #0
|
|
1a1a: str r0, [sp, #48]
|
|
1a1c: ldr r1, [sp, #44]
|
|
1a1e: str r1, [sp, #20]
|
|
1a20: ldr r1, [sp, #40]
|
|
1a22: str r1, [sp, #16]
|
|
1a24: ldr r1, [sp, #36]
|
|
1a26: str r1, [sp, #12]
|
|
1a28: ldr r1, [sp, #56]
|
|
1a2a: str r1, [sp, #32]
|
|
1a2c: ldr r1, [sp, #52]
|
|
1a2e: str r1, [sp, #28]
|
|
1a30: ldr r1, [sp, #48]
|
|
1a32: str r1, [sp, #24]
|
|
1a34: add r4, sp, #12
|
|
1a36: add r3, sp, #64
|
|
1a38: mov r2, r3
|
|
1a3a: ldm r4!, {r1, r5, r6}
|
|
1a3c: stm r2!, {r1, r5, r6}
|
|
1a3e: ldm r4!, {r1, r5, r6}
|
|
1a40: stm r2!, {r1, r5, r6}
|
|
1a42: ldr r1, [sp, #4]
|
|
1a44: adds r2, r1, #4
|
|
1a46: ldm r3!, {r4, r5, r6}
|
|
1a48: stm r2!, {r4, r5, r6}
|
|
1a4a: ldm r3!, {r4, r5, r6}
|
|
1a4c: stm r2!, {r4, r5, r6}
|
|
1a4e: strb r0, [r1]
|
|
1a50: add sp, #92
|
|
1a52: pop {r4, r5, r6, r7, pc}
|
|
|
|
00001a54 <max116xx_10bit::Max116xx10Bit<SPI,CS>::max11619::h108cee7c000e330c>:
|
|
1a54: push {r7, lr}
|
|
1a56: add r7, sp, #0
|
|
1a58: sub sp, #16
|
|
1a5a: ldr r2, [r1, #8]
|
|
1a5c: str r2, [sp, #8]
|
|
1a5e: ldr r2, [r1, #4]
|
|
1a60: str r2, [sp, #4]
|
|
1a62: ldr r1, [r1]
|
|
1a64: str r1, [sp]
|
|
1a66: mov r1, sp
|
|
1a68: bl 0x19e0 <max116xx_10bit::Max116xx10Bit<SPI,CS>::new::h943c44bd332c47a7> @ imm = #-140
|
|
1a6c: b 0x1a6e <max116xx_10bit::Max116xx10Bit<SPI,CS>::max11619::h108cee7c000e330c+0x1a> @ imm = #-2
|
|
1a6e: add sp, #16
|
|
1a70: pop {r7, pc}
|
|
1a72: bmi 0x1a1e <max116xx_10bit::Max116xx10Bit<SPI,CS>::new::h943c44bd332c47a7+0x3e> @ imm = #-88
|
|
|
|
00001a74 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37>:
|
|
1a74: push {r7, lr}
|
|
1a76: add r7, sp, #0
|
|
1a78: sub sp, #232
|
|
1a7a: str r0, [sp, #24]
|
|
1a7c: mov r2, r1
|
|
1a7e: str r2, [sp, #28]
|
|
1a80: str r0, [sp, #60]
|
|
1a82: add r2, sp, #64
|
|
1a84: strb r1, [r2]
|
|
1a86: add r2, sp, #56
|
|
1a88: movs r1, #0
|
|
1a8a: strb r1, [r2]
|
|
1a8c: bl 0x130e <<dummy_pin::dummy::DummyPin<L> as embedded_hal::digital::v2::OutputPin>::set_low::hb543f757bce9f448> @ imm = #-1922
|
|
1a90: b 0x1a92 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x1e> @ imm = #-2
|
|
1a92: bl 0x30a <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE> @ imm = #-6028
|
|
1a96: uxtb r0, r0
|
|
1a98: str r0, [sp, #20]
|
|
1a9a: b 0x1a9c <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x28> @ imm = #-2
|
|
1a9c: ldr r0, [sp, #20]
|
|
1a9e: bl 0x45c <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h338082970efc5187E> @ imm = #-5702
|
|
1aa2: uxtb r0, r0
|
|
1aa4: add r1, sp, #36
|
|
1aa6: strb r0, [r1]
|
|
1aa8: b 0x1aaa <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x36> @ imm = #-2
|
|
1aaa: add r0, sp, #36
|
|
1aac: ldrb r0, [r0]
|
|
1aae: subs r1, r0, #7
|
|
1ab0: subs r2, r1, #1
|
|
1ab2: sbcs r1, r2
|
|
1ab4: cmp r0, #7
|
|
1ab6: beq 0x1abe <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x4a> @ imm = #4
|
|
1ab8: b 0x1aba <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x46> @ imm = #-2
|
|
1aba: b 0x1ac0 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x4c> @ imm = #2
|
|
1abc: trap
|
|
1abe: b 0x1ada <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x66> @ imm = #24
|
|
1ac0: ldr r0, [sp, #36]
|
|
1ac2: add r1, sp, #88
|
|
1ac4: strb r0, [r1]
|
|
1ac6: bl 0x144 <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hde03a568dc94affdE> @ imm = #-6534
|
|
1aca: uxtb r0, r0
|
|
1acc: add r1, sp, #32
|
|
1ace: strb r0, [r1]
|
|
1ad0: b 0x1ad2 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x5e> @ imm = #-2
|
|
1ad2: b 0x1ad4 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x60> @ imm = #-2
|
|
1ad4: ldr r0, [sp, #32]
|
|
1ad6: add sp, #232
|
|
1ad8: pop {r7, pc}
|
|
1ada: ldr r0, [sp, #24]
|
|
1adc: ldr r1, [sp, #28]
|
|
1ade: mov r2, r0
|
|
1ae0: str r2, [sp, #16]
|
|
1ae2: add r2, sp, #100
|
|
1ae4: strb r1, [r2]
|
|
1ae6: str r0, [sp, #120]
|
|
1ae8: str r0, [sp, #124]
|
|
1aea: ldr r0, [pc, #412] <$d.8+0x2>
|
|
1aec: str r0, [sp, #172]
|
|
1aee: str r0, [sp, #176]
|
|
1af0: str r0, [sp, #180]
|
|
1af2: bl 0x8070 <core::ptr::read_volatile::hf4c692006cd65b29> @ imm = #25978
|
|
1af6: str r0, [sp, #168]
|
|
1af8: ldr r0, [sp, #168]
|
|
1afa: str r0, [sp, #188]
|
|
1afc: str r0, [sp, #184]
|
|
1afe: ldr r0, [sp, #184]
|
|
1b00: str r0, [sp, #112]
|
|
1b02: add r0, sp, #112
|
|
1b04: str r0, [sp, #192]
|
|
1b06: str r0, [sp, #196]
|
|
1b08: ldr r0, [sp, #112]
|
|
1b0a: lsls r0, r0, #30
|
|
1b0c: lsrs r0, r0, #31
|
|
1b0e: add r1, sp, #204
|
|
1b10: strb r0, [r1]
|
|
1b12: add r1, sp, #212
|
|
1b14: strb r0, [r1]
|
|
1b16: add r1, sp, #208
|
|
1b18: strb r0, [r1]
|
|
1b1a: ldr r0, [sp, #208]
|
|
1b1c: add r1, sp, #200
|
|
1b1e: strb r0, [r1]
|
|
1b20: ldr r1, [sp, #200]
|
|
1b22: add r0, sp, #108
|
|
1b24: strb r1, [r0]
|
|
1b26: str r0, [sp, #216]
|
|
1b28: str r0, [sp, #224]
|
|
1b2a: str r0, [sp, #228]
|
|
1b2c: ldrb r0, [r0]
|
|
1b2e: lsls r0, r0, #31
|
|
1b30: cmp r0, #0
|
|
1b32: beq 0x1b7a <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x106> @ imm = #68
|
|
1b34: b 0x1b36 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0xc2> @ imm = #-2
|
|
1b36: ldr r0, [sp, #16]
|
|
1b38: str r0, [sp, #220]
|
|
1b3a: add r0, sp, #100
|
|
1b3c: str r0, [sp, #116]
|
|
1b3e: ldr r0, [sp, #116]
|
|
1b40: ldr r1, [pc, #328] <$d.8+0x4>
|
|
1b42: str r1, [sp, #8]
|
|
1b44: str r1, [sp, #140]
|
|
1b46: str r0, [sp, #144]
|
|
1b48: movs r1, #0
|
|
1b4a: str r1, [sp, #12]
|
|
1b4c: str r1, [sp, #136]
|
|
1b4e: ldr r1, [sp, #136]
|
|
1b50: str r1, [sp, #164]
|
|
1b52: str r1, [sp, #160]
|
|
1b54: ldr r1, [sp, #160]
|
|
1b56: str r1, [sp, #132]
|
|
1b58: add r1, sp, #132
|
|
1b5a: str r1, [sp, #128]
|
|
1b5c: ldr r1, [sp, #128]
|
|
1b5e: bl 0x3f28 <<va108xx_hal::spi::SpiBase<va108xx::SPIB> as embedded_hal::spi::FullDuplex<u8>>::send::{{closure}}::h1c05d4bbd98f482c> @ imm = #9158
|
|
1b62: mov r1, r0
|
|
1b64: ldr r0, [sp, #8]
|
|
1b66: ldr r1, [r1]
|
|
1b68: str r0, [sp, #148]
|
|
1b6a: str r1, [sp, #152]
|
|
1b6c: str r0, [sp, #156]
|
|
1b6e: bl 0x8084 <core::ptr::write_volatile::h8d4daf2714a04997> @ imm = #25874
|
|
1b72: ldr r0, [sp, #12]
|
|
1b74: add r1, sp, #104
|
|
1b76: strb r0, [r1]
|
|
1b78: b 0x1b82 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x10e> @ imm = #6
|
|
1b7a: add r1, sp, #104
|
|
1b7c: movs r0, #1
|
|
1b7e: strb r0, [r1]
|
|
1b80: b 0x1b82 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x10e> @ imm = #-2
|
|
1b82: ldr r0, [sp, #104]
|
|
1b84: add r1, sp, #48
|
|
1b86: strb r0, [r1]
|
|
1b88: b 0x1b8a <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x116> @ imm = #-2
|
|
1b8a: add r1, sp, #56
|
|
1b8c: movs r0, #1
|
|
1b8e: strb r0, [r1]
|
|
1b90: add r0, sp, #48
|
|
1b92: ldrb r0, [r0]
|
|
1b94: lsls r0, r0, #31
|
|
1b96: cmp r0, #0
|
|
1b98: beq 0x1ba0 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x12c> @ imm = #4
|
|
1b9a: b 0x1b9c <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x128> @ imm = #-2
|
|
1b9c: b 0x1ba2 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x12e> @ imm = #2
|
|
1b9e: trap
|
|
1ba0: b 0x1bcc <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x158> @ imm = #40
|
|
1ba2: movs r0, #0
|
|
1ba4: cmp r0, #0
|
|
1ba6: bne 0x1bac <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x138> @ imm = #2
|
|
1ba8: b 0x1baa <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x136> @ imm = #-2
|
|
1baa: b 0x1bb0 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x13c> @ imm = #2
|
|
1bac: trap
|
|
1bae: b 0x1bcc <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x158> @ imm = #26
|
|
1bb0: add r0, sp, #48
|
|
1bb2: ldrb r0, [r0]
|
|
1bb4: lsls r0, r0, #31
|
|
1bb6: cmp r0, #0
|
|
1bb8: beq 0x1bc4 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x150> @ imm = #8
|
|
1bba: b 0x1bbc <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x148> @ imm = #-2
|
|
1bbc: add r1, sp, #56
|
|
1bbe: movs r0, #0
|
|
1bc0: strb r0, [r1]
|
|
1bc2: b 0x1bc4 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x150> @ imm = #-2
|
|
1bc4: add r1, sp, #56
|
|
1bc6: movs r0, #0
|
|
1bc8: strb r0, [r1]
|
|
1bca: b 0x1ada <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x66> @ imm = #-244
|
|
1bcc: add r0, sp, #48
|
|
1bce: ldrb r0, [r0]
|
|
1bd0: lsls r0, r0, #31
|
|
1bd2: cmp r0, #0
|
|
1bd4: beq 0x1be4 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x170> @ imm = #12
|
|
1bd6: b 0x1bd8 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x164> @ imm = #-2
|
|
1bd8: add r0, sp, #56
|
|
1bda: ldrb r0, [r0]
|
|
1bdc: lsls r0, r0, #31
|
|
1bde: cmp r0, #0
|
|
1be0: bne 0x1bfc <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x188> @ imm = #24
|
|
1be2: b 0x1bf4 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x180> @ imm = #14
|
|
1be4: add r1, sp, #56
|
|
1be6: movs r0, #0
|
|
1be8: strb r0, [r1]
|
|
1bea: bl 0x35c <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17hf0e429eaa3a37c4aE> @ imm = #-6290
|
|
1bee: uxtb r0, r0
|
|
1bf0: str r0, [sp, #4]
|
|
1bf2: b 0x1bfe <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x18a> @ imm = #8
|
|
1bf4: add r1, sp, #56
|
|
1bf6: movs r0, #0
|
|
1bf8: strb r0, [r1]
|
|
1bfa: b 0x1be4 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x170> @ imm = #-26
|
|
1bfc: b 0x1bf4 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x180> @ imm = #-12
|
|
1bfe: ldr r0, [sp, #4]
|
|
1c00: bl 0x45c <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h338082970efc5187E> @ imm = #-6056
|
|
1c04: uxtb r0, r0
|
|
1c06: add r1, sp, #40
|
|
1c08: strb r0, [r1]
|
|
1c0a: b 0x1c0c <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x198> @ imm = #-2
|
|
1c0c: add r0, sp, #40
|
|
1c0e: ldrb r0, [r0]
|
|
1c10: subs r1, r0, #7
|
|
1c12: subs r2, r1, #1
|
|
1c14: sbcs r1, r2
|
|
1c16: cmp r0, #7
|
|
1c18: beq 0x1c20 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x1ac> @ imm = #4
|
|
1c1a: b 0x1c1c <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x1a8> @ imm = #-2
|
|
1c1c: b 0x1c28 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x1b4> @ imm = #8
|
|
1c1e: trap
|
|
1c20: ldr r0, [sp, #24]
|
|
1c22: bl 0x1316 <<dummy_pin::dummy::DummyPin<L> as embedded_hal::digital::v2::OutputPin>::set_high::h7185e627752c569a> @ imm = #-2320
|
|
1c26: b 0x1c3c <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x1c8> @ imm = #18
|
|
1c28: ldr r0, [sp, #40]
|
|
1c2a: add r1, sp, #92
|
|
1c2c: strb r0, [r1]
|
|
1c2e: bl 0x144 <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hde03a568dc94affdE> @ imm = #-6894
|
|
1c32: uxtb r0, r0
|
|
1c34: add r1, sp, #32
|
|
1c36: strb r0, [r1]
|
|
1c38: b 0x1c3a <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x1c6> @ imm = #-2
|
|
1c3a: b 0x1ad4 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x60> @ imm = #-362
|
|
1c3c: bl 0x30a <_ZN4core6result19Result$LT$T$C$E$GT$7map_err17h99eb9539e0a1ad8eE> @ imm = #-6454
|
|
1c40: uxtb r0, r0
|
|
1c42: str r0, [sp]
|
|
1c44: b 0x1c46 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x1d2> @ imm = #-2
|
|
1c46: ldr r0, [sp]
|
|
1c48: bl 0x45c <_ZN79_$LT$core..result..Result$LT$T$C$E$GT$$u20$as$u20$core..ops..try_trait..Try$GT$6branch17h338082970efc5187E> @ imm = #-6128
|
|
1c4c: uxtb r0, r0
|
|
1c4e: add r1, sp, #52
|
|
1c50: strb r0, [r1]
|
|
1c52: b 0x1c54 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x1e0> @ imm = #-2
|
|
1c54: add r0, sp, #52
|
|
1c56: ldrb r0, [r0]
|
|
1c58: subs r1, r0, #7
|
|
1c5a: subs r2, r1, #1
|
|
1c5c: sbcs r1, r2
|
|
1c5e: cmp r0, #7
|
|
1c60: beq 0x1c68 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x1f4> @ imm = #4
|
|
1c62: b 0x1c64 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x1f0> @ imm = #-2
|
|
1c64: b 0x1c74 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x200> @ imm = #12
|
|
1c66: trap
|
|
1c68: add r1, sp, #32
|
|
1c6a: movs r0, #0
|
|
1c6c: strb r0, [r1]
|
|
1c6e: movs r0, #7
|
|
1c70: strb r0, [r1]
|
|
1c72: b 0x1ad4 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x60> @ imm = #-418
|
|
1c74: ldr r0, [sp, #52]
|
|
1c76: add r1, sp, #96
|
|
1c78: strb r0, [r1]
|
|
1c7a: bl 0x144 <_ZN153_$LT$core..result..Result$LT$T$C$F$GT$$u20$as$u20$core..ops..try_trait..FromResidual$LT$core..result..Result$LT$core..convert..Infallible$C$E$GT$$GT$$GT$13from_residual17hde03a568dc94affdE> @ imm = #-6970
|
|
1c7e: uxtb r0, r0
|
|
1c80: add r1, sp, #32
|
|
1c82: strb r0, [r1]
|
|
1c84: b 0x1c86 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x212> @ imm = #-2
|
|
1c86: b 0x1ad4 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x60> @ imm = #-438
|
|
|
|
00001c88 <$d.8>:
|
|
1c88: 0c 10 05 40 .word 0x4005100c
|
|
1c8c: 08 10 05 40 .word 0x40051008
|
|
|
|
00001c90 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_setup_byte::hb467d2b0075cb186>:
|
|
1c90: sub sp, #20
|
|
1c92: str r0, [sp, #8]
|
|
1c94: str r0, [sp, #16]
|
|
1c96: ldrb r0, [r0, #16]
|
|
1c98: lsls r0, r0, #4
|
|
1c9a: str r0, [sp, #12]
|
|
1c9c: b 0x1c9e <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_setup_byte::hb467d2b0075cb186+0xe> @ imm = #-2
|
|
1c9e: ldr r0, [sp, #8]
|
|
1ca0: ldr r1, [sp, #12]
|
|
1ca2: movs r2, #64
|
|
1ca4: orrs r1, r2
|
|
1ca6: str r1, [sp]
|
|
1ca8: ldrb r0, [r0, #17]
|
|
1caa: lsls r0, r0, #2
|
|
1cac: str r0, [sp, #4]
|
|
1cae: b 0x1cb0 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_setup_byte::hb467d2b0075cb186+0x20> @ imm = #-2
|
|
1cb0: ldr r1, [sp, #4]
|
|
1cb2: ldr r0, [sp]
|
|
1cb4: orrs r0, r1
|
|
1cb6: add sp, #20
|
|
1cb8: bx lr
|
|
1cba: bmi 0x1c66 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37+0x1f2> @ imm = #-88
|
|
|
|
00001cbc <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_results_len::hd3b62b85ca1163d0>:
|
|
1cbc: push {r7, lr}
|
|
1cbe: add r7, sp, #0
|
|
1cc0: sub sp, #16
|
|
1cc2: mov r1, r0
|
|
1cc4: uxtb r0, r1
|
|
1cc6: add r2, sp, #12
|
|
1cc8: strb r1, [r2]
|
|
1cca: adds r1, r0, #1
|
|
1ccc: str r1, [sp, #8]
|
|
1cce: uxtb r0, r1
|
|
1cd0: cmp r0, r1
|
|
1cd2: bne 0x1ce6 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_results_len::hd3b62b85ca1163d0+0x2a> @ imm = #16
|
|
1cd4: b 0x1cd6 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_results_len::hd3b62b85ca1163d0+0x1a> @ imm = #-2
|
|
1cd6: ldr r0, [sp, #8]
|
|
1cd8: uxtb r0, r0
|
|
1cda: lsls r0, r0, #2
|
|
1cdc: str r0, [sp, #4]
|
|
1cde: lsrs r0, r0, #8
|
|
1ce0: cmp r0, #0
|
|
1ce2: bne 0x1cf8 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_results_len::hd3b62b85ca1163d0+0x3c> @ imm = #18
|
|
1ce4: b 0x1cf2 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_results_len::hd3b62b85ca1163d0+0x36> @ imm = #10
|
|
1ce6: ldr r0, [pc, #36] <$d.11+0xa>
|
|
1ce8: ldr r2, [pc, #28] <$d.11+0x4>
|
|
1cea: movs r1, #28
|
|
1cec: bl 0x8548 <core::panicking::panic::hd188a7f3102defa3> @ imm = #26712
|
|
1cf0: trap
|
|
1cf2: ldr r0, [sp, #4]
|
|
1cf4: add sp, #16
|
|
1cf6: pop {r7, pc}
|
|
1cf8: ldr r0, [pc, #8] <$d.11>
|
|
1cfa: ldr r2, [pc, #12] <$d.11+0x6>
|
|
1cfc: movs r1, #33
|
|
1cfe: bl 0x8548 <core::panicking::panic::hd188a7f3102defa3> @ imm = #26694
|
|
1d02: trap
|
|
|
|
00001d04 <$d.11>:
|
|
1d04: 50 aa 00 00 .word 0x0000aa50
|
|
1d08: d4 aa 00 00 .word 0x0000aad4
|
|
1d0c: 20 aa 00 00 .word 0x0000aa20
|
|
|
|
00001d10 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_averaging_byte::ha55eaab71c306b31>:
|
|
1d10: sub sp, #16
|
|
1d12: mov r2, r1
|
|
1d14: str r2, [sp]
|
|
1d16: add r2, sp, #8
|
|
1d18: strb r0, [r2]
|
|
1d1a: add r2, sp, #12
|
|
1d1c: strb r1, [r2]
|
|
1d1e: lsls r0, r0, #2
|
|
1d20: str r0, [sp, #4]
|
|
1d22: b 0x1d24 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_averaging_byte::ha55eaab71c306b31+0x14> @ imm = #-2
|
|
1d24: ldr r1, [sp]
|
|
1d26: ldr r0, [sp, #4]
|
|
1d28: orrs r0, r1
|
|
1d2a: movs r1, #32
|
|
1d2c: orrs r0, r1
|
|
1d2e: add sp, #16
|
|
1d30: bx lr
|
|
|
|
00001d32 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_conversion_byte::hb7ec64df4edb09f6>:
|
|
1d32: push {r4, r6, r7, lr}
|
|
1d34: add r7, sp, #8
|
|
1d36: sub sp, #36
|
|
1d38: mov r3, r1
|
|
1d3a: mov r1, r0
|
|
1d3c: uxtb r0, r2
|
|
1d3e: mov r4, r2
|
|
1d40: str r4, [sp, #12]
|
|
1d42: mov r4, r3
|
|
1d44: str r4, [sp, #16]
|
|
1d46: str r1, [sp, #24]
|
|
1d48: add r4, sp, #28
|
|
1d4a: strb r3, [r4]
|
|
1d4c: add r3, sp, #32
|
|
1d4e: strb r2, [r3]
|
|
1d50: ldrb r1, [r1, #19]
|
|
1d52: cmp r0, r1
|
|
1d54: bhi 0x1d60 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_conversion_byte::hb7ec64df4edb09f6+0x2e> @ imm = #8
|
|
1d56: b 0x1d58 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_conversion_byte::hb7ec64df4edb09f6+0x26> @ imm = #-2
|
|
1d58: ldr r0, [sp, #12]
|
|
1d5a: lsls r0, r0, #3
|
|
1d5c: str r0, [sp, #8]
|
|
1d5e: b 0x1d76 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_conversion_byte::hb7ec64df4edb09f6+0x44> @ imm = #20
|
|
1d60: add r1, sp, #20
|
|
1d62: movs r0, #0
|
|
1d64: strb r0, [r1, #1]
|
|
1d66: movs r0, #1
|
|
1d68: strb r0, [r1]
|
|
1d6a: b 0x1d6c <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_conversion_byte::hb7ec64df4edb09f6+0x3a> @ imm = #-2
|
|
1d6c: add r1, sp, #20
|
|
1d6e: ldrb r0, [r1]
|
|
1d70: ldrb r1, [r1, #1]
|
|
1d72: add sp, #36
|
|
1d74: pop {r4, r6, r7, pc}
|
|
1d76: ldr r0, [sp, #16]
|
|
1d78: ldr r1, [sp, #8]
|
|
1d7a: movs r2, #127
|
|
1d7c: mvns r2, r2
|
|
1d7e: orrs r1, r2
|
|
1d80: str r1, [sp]
|
|
1d82: lsls r0, r0, #1
|
|
1d84: str r0, [sp, #4]
|
|
1d86: b 0x1d88 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_conversion_byte::hb7ec64df4edb09f6+0x56> @ imm = #-2
|
|
1d88: ldr r1, [sp, #4]
|
|
1d8a: ldr r0, [sp]
|
|
1d8c: orrs r0, r1
|
|
1d8e: add r1, sp, #20
|
|
1d90: strb r0, [r1, #1]
|
|
1d92: movs r0, #0
|
|
1d94: strb r0, [r1]
|
|
1d96: b 0x1d6c <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_conversion_byte::hb7ec64df4edb09f6+0x3a> @ imm = #-46
|
|
|
|
00001d98 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::reset::h6445cf02374a70dd>:
|
|
1d98: push {r7, lr}
|
|
1d9a: add r7, sp, #0
|
|
1d9c: sub sp, #24
|
|
1d9e: str r0, [sp, #8]
|
|
1da0: str r0, [sp, #16]
|
|
1da2: add r0, sp, #20
|
|
1da4: strb r1, [r0]
|
|
1da6: add r2, sp, #12
|
|
1da8: movs r0, #16
|
|
1daa: strb r0, [r2]
|
|
1dac: cmp r1, #0
|
|
1dae: bne 0x1dc0 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::reset::h6445cf02374a70dd+0x28> @ imm = #14
|
|
1db0: b 0x1db2 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::reset::h6445cf02374a70dd+0x1a> @ imm = #-2
|
|
1db2: ldr r0, [sp, #8]
|
|
1db4: ldr r1, [sp, #12]
|
|
1db6: bl 0x1a74 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37> @ imm = #-838
|
|
1dba: uxtb r0, r0
|
|
1dbc: str r0, [sp, #4]
|
|
1dbe: b 0x1dcc <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::reset::h6445cf02374a70dd+0x34> @ imm = #10
|
|
1dc0: ldr r0, [sp, #12]
|
|
1dc2: movs r1, #8
|
|
1dc4: orrs r0, r1
|
|
1dc6: add r1, sp, #12
|
|
1dc8: strb r0, [r1]
|
|
1dca: b 0x1db2 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::reset::h6445cf02374a70dd+0x1a> @ imm = #-28
|
|
1dcc: ldr r0, [sp, #4]
|
|
1dce: add sp, #24
|
|
1dd0: pop {r7, pc}
|
|
|
|
00001dd2 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::setup::h2b9af7e788767d10>:
|
|
1dd2: push {r7, lr}
|
|
1dd4: add r7, sp, #0
|
|
1dd6: sub sp, #16
|
|
1dd8: str r0, [sp, #4]
|
|
1dda: str r0, [sp, #12]
|
|
1ddc: bl 0x1c90 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::get_setup_byte::hb467d2b0075cb186> @ imm = #-336
|
|
1de0: str r0, [sp, #8]
|
|
1de2: b 0x1de4 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::setup::h2b9af7e788767d10+0x12> @ imm = #-2
|
|
1de4: ldr r1, [sp, #8]
|
|
1de6: ldr r0, [sp, #4]
|
|
1de8: bl 0x1a74 <max116xx_10bit::Max116xx10Bit<SPI,CS,CLOCKED,WAKEUP>::send_wrapper::h71d16716f3accb37> @ imm = #-888
|
|
1dec: uxtb r0, r0
|
|
1dee: str r0, [sp]
|