271 lines
8.6 KiB
Markdown
271 lines
8.6 KiB
Markdown
Change Log
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=======
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All notable changes to this project will be documented in this file.
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The format is based on [Keep a Changelog](http://keepachangelog.com/)
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and this project adheres to [Semantic Versioning](http://semver.org/).
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## [unreleased]
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## [v0.11.1] 2025-03-10
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## Fixed
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- Fix `embedded_io` UART implementation to implement the documented contract properly.
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The implementation will now block until at least one byte is available or can be written, unless
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the send or receive buffer is empty.
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## [v0.11.0] 2025-03-07
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## Changed
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- Bugfix for I2C `TimingCfg::reg`
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- Simplified UART error handling. All APIs are now infallible because writing to a FIFO or
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reading from a FIFO never fails. Users can either poll errors using `Rx::poll_errors` or
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`Uart::poll_rx_errors` / `UartBase::poll_rx_errors`, or detect errors using the provided
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interrupt handlers.
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## [v0.10.0] 2025-02-17
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## Added
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- A lot of missing `defmt::Format` implementations.
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## Changed
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- Larger refactoring of GPIO library. The edge and level interrupt configurator functions do not
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enable interrupts anymore. Instead, there are explicit `enbable_interrupt` and
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`disable_interrupt` methods
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- Renamed GPIO `DynGroup` to `Port`
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- Rename generic GPIO interrupt handler into `on_interrupt_for_asynch_gpio`
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into `on_interrupt_for_async_gpio_for_port` which expects a Port argument
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## Fixed
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- Bug in async GPIO interrupt handler where all enabled interrupts, even the ones which might
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be unrelated to the pin, were disabled.
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## [v0.9.0] 2025-02-13
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## Fixed
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- Important bugfix for UART driver which causes UART B drivers not to work.
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## Removed
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- Deleted some HAL re-exports in the PWM module
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## Changed
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- GPIO API: Interrupt, pulse and filter and `set_datamask` and `clear_datamask` APIs are now
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methods which mutable modify the pin instead of consuming and returning it.
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- Simplified PWM module implementation.
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- All error types now implement `core::error::Error` by using the `thiserror::Error` derive.
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- `InvalidPinTypeError` now wraps the pin mode.
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- I2C `TimingCfg` constructor now returns explicit error instead of generic Error.
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Removed the timing configuration error type from the generic I2C error enumeration.
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- `PinsA` and `PinsB` constructor do not expect an optional `pac::Ioconfig` argument anymore.
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- `IrqCfg` renamed to `InterruptConfig`, kept alias for old name.
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- All library provided interrupt handlers now start with common prefix `on_interrupt_*`
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- `RxWithIrq` renamed to `RxWithInterrupt`
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- `Rx::into_rx_with_irq` does not expect any arguments any more.
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- `filter_type` renamed to `configure_filter_type`.
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- `level_irq` renamed to `configure_level_interrupt`.
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- `edge_irq` renamed to `configure_edge_interrupt`.
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- `PinsA` and `PinsB` constructor do not expect an optional IOCONFIG argument anymore.
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- UART interrupt management is now handled by the main constructor instead of later stages to
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statically ensure one interrupt vector for the UART peripheral. `Uart::new` expects an
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optional `InterruptConfig` argument.
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- `enable_interrupt` and `disable_interrupt` renamed to `enable_nvic_interrupt` and
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`disable_nvic_interrupt` to distinguish them from peripheral interrupts more clearly.
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- `port_mux` renamed to `port_function_select`
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- Renamed `IrqUartErrors` to `UartErrors`.
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## Added
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- Add `downgrade` method for `Pin` and `upgrade` method for `DynPin` as explicit conversion
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methods.
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- Asynchronous GPIO support.
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- Asynchronous UART TX support.
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- Asynchronous UART RX support.
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- Add new `get_tim_raw` unsafe method to retrieve TIM peripheral blocks.
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- `Uart::with_with_interrupt` and `Uart::new_without_interrupt`
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## [v0.8.0] 2024-09-30
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## Changed
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- Improves `CascardSource` handling and general API when chosing cascade sources.
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- Replaced `utility::unmask_irq` by `enable_interrupt` and `disable_interrupt` API.
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- Improve and fix SPI abstractions. Add new low level interface. The primary SPI constructor now
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only expects a configuration structure and the transfer configuration needs to be applied in a
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separate step.
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- Removed complete `timer` module re-export in `pwm` module
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- `CountDownTimer` renamed to `CountdownTimer`
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## Fixes
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- Fixes for SPI peripheral: Flush implementation was incorrect and should now flush properly.
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## [v0.7.0] 2024-07-04
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- Replace `uarta` and `uartb` `Uart` constructors by `new` constructor
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- Replace SPI `spia`, `spib` and `spic` constructors by `new` constructor
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- Replace I2C `i2ca`, `i2cb` constructors by `new` constructor. Update constructor
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to fail on invalid fast I2C speed system clock values
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- Renamed `gpio::pins` to `gpio::pin` and `gpio::dynpins` to `gpio::dynpin`
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- Simplify UART clock divider calculations and remove `libm` dependency consequently
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## [v0.6.0] 2024-06-16
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- Updated `embedded-hal` to v1
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- Added optional `defmt` v0.3 feature and support.
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## v0.5.2 2024-06-16
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## Fixed
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- Replaced usage to `ptr::write_volatile` in UART module which is denied on more recent Rust
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compilers.
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## v0.5.1
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### Changes
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- Updated dependencies:
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- `cortex-m-rtic` (dev-depencency) to 1.1.2
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- `once_cell` to 1.12.0
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- Other dependencies: Only revision has changed
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## v0.5.0
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### Added
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- Reactored IRQ handling, so that `unmask` operations can be moved to HAL
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- Added UART IRQ handler. Right now, can only perform reception, TX still needs to be done in
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a blocking manner
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- Added RTIC template and RTIC UART IRQ application
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### Fixed
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- Bugfix in UART code where RX and TX could not be enabled or disabled independently
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## v0.4.3
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- Various smaller fixes for READMEs, update of links in documentation
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- Simplified CI for github, do not use `cross`
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- New `blinky-pac` example
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- Use HAL delay in `blinky` example
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## v0.4.2
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### Added
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- `port_mux` function to set pin function select manually
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### Changed
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- Clear TX and RX FIFO in SPI transfer function
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## v0.4.1
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### Fixed
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- Initial blockmode setting was not set in SPI constructor
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## v0.4.0
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### Changed
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- Replaced `Hertz` by `impl Into<Hertz>` completely and removed
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`+ Copy` where not necessary
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## v0.3.1
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- Updated all links to point to new repository
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## v0.3.0
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### Added
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- TIM Cascade example
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### Changed
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- `CountDownTimer` new function now expects an `impl Into<Hertz>` instead of `Hertz`
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- Primary repository now hosted on IRS external git: https://egit.irs.uni-stuttgart.de/rust/va108xx-hal
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- Relicensed as Apache-2.0
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## v0.2.3
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### Added
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- Basic API for EDAC functionality
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- PWM implementation and example
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- API to perform peripheral resets
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### Changed
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- Improved Timer API. It is now possible to simply use `new` on `CountDownTimer`
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## v0.2.2
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### Added
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- DelayUs and DelayMs trait implementations for timer
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- SPI implementation for blocking API, supports blockmode as well
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- Basic I2C implementation for blocking API
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### Changed
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- API which expects values in Hertz now uses `impl Into<Hertz>` as input parameter
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## v0.2.1
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### Added
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- Adds the IRQ interface to configure interrupts on output and input pins
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- Utility function to set up millisecond timer with `TIM0`
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- Function to set clock divisor registers in `clock` module
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### Changed
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- Minor optimizations and tweaks for GPIO module
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- Moved the `FilterClkSel` struct to the `clock` module, re-exporting in `gpio`
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- Clearing output state at initialization of Output pins
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## v0.2.0
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### Changed
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- New GPIO implementation which uses type-level programming. Implementation heavily based on the
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ATSAMD GPIO HAL: https://docs.rs/atsamd-hal/0.13.0/atsamd_hal/gpio/v2/index.html
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- Changes to API, therefore minor version bump
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### Added
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- UART implementation
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- UART example
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- Some bugfixes for GPIO implementation
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- Rust edition updated to 2021
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## v0.1.0
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### Added
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- First version of the HAL which adds the GPIO implementation and timer implementation.
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- Also adds some examples and helper files to set up new binary crates
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- RTT example application
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- Added basic test binary in form of an example
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- README with basic instructions how to set up own binary crate
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[unreleased]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...HEAD
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[v0.11.1]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.11.0...va108xx-hal-v0.11.1
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[v0.11.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.10.0...va108xx-hal-v0.11.0
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[v0.10.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.9.0...va108xx-hal-v0.10.0
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[v0.9.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.8.0...va108xx-hal-v0.9.0
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[v0.8.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.7.0...va108xx-hal-v0.8.0
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[v0.7.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/compare/va108xx-hal-v0.6.0...va108xx-hal-v0.7.0
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[v0.6.0]: https://egit.irs.uni-stuttgart.de/rust/va108xx-rs/src/tag/va108xx-hal-v0.6.0
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