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Important fix: Use bitmask everywhere now

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This PAC was generated using a patched version of svd2rust with
commit hash 43be074d21132c3a76780816010df592a3603874

It includes bugfix https://github.com/rust-embedded/svd2rust/pull/549
This commit is contained in:
Robin Müller
2021-11-09 18:11:56 +01:00
parent d37aad6b1c
commit 8c28367a33
62 changed files with 98 additions and 92 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/sysconfig/irq_clr.rs
View File

@ -37,7 +37,7 @@ impl<'a> RAMSBE_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = value as u32;
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}

4
src/sysconfig/irq_enb.rs
View File

@ -67,7 +67,7 @@ impl<'a> RAMSBE_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = value as u32;
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
@ -186,7 +186,7 @@ impl R {
#[doc = "Bit 0 - RAM Single Bit Interrupt"]
#[inline(always)]
pub fn ramsbe(&self) -> RAMSBE_R {
RAMSBE_R::new(self.bits != 0)
RAMSBE_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 1 - RAM Multi Bit Interrupt"]
#[inline(always)]

2
src/sysconfig/irq_end.rs
View File

@ -77,7 +77,7 @@ impl R {
#[doc = "Bit 0 - RAM Single Bit Interrupt"]
#[inline(always)]
pub fn ramsbe(&self) -> RAMSBE_R {
RAMSBE_R::new(self.bits != 0)
RAMSBE_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 1 - RAM Multi Bit Interrupt"]
#[inline(always)]

2
src/sysconfig/irq_raw.rs
View File

@ -77,7 +77,7 @@ impl R {
#[doc = "Bit 0 - RAM Single Bit Interrupt"]
#[inline(always)]
pub fn ramsbe(&self) -> RAMSBE_R {
RAMSBE_R::new(self.bits != 0)
RAMSBE_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 1 - RAM Multi Bit Interrupt"]
#[inline(always)]

4
src/sysconfig/lockup_reset.rs
View File

@ -67,7 +67,7 @@ impl<'a> LREN_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = value as u32;
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
@ -75,7 +75,7 @@ impl R {
#[doc = "Bit 0 - Lockup Reset Enable Bit"]
#[inline(always)]
pub fn lren(&self) -> LREN_R {
LREN_R::new(self.bits != 0)
LREN_R::new((self.bits & 0x01) != 0)
}
}
impl W {

4
src/sysconfig/peripheral_clk_enable.rs
View File

@ -67,7 +67,7 @@ impl<'a> PORTA_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = value as u32;
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
@ -533,7 +533,7 @@ impl R {
#[doc = "Bit 0 - Enable PORTA clock"]
#[inline(always)]
pub fn porta(&self) -> PORTA_R {
PORTA_R::new(self.bits != 0)
PORTA_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 1 - Enable PORTB clock"]
#[inline(always)]

4
src/sysconfig/ram_scrub.rs
View File

@ -57,7 +57,7 @@ impl<'a> VALUE_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
self.w.bits = value as u32;
self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
self.w
}
}
@ -87,7 +87,7 @@ impl R {
#[doc = "Bits 0:23 - Counter divide value"]
#[inline(always)]
pub fn value(&self) -> VALUE_R {
VALUE_R::new(self.bits as u32)
VALUE_R::new((self.bits & 0x00ff_ffff) as u32)
}
}
impl W {

4
src/sysconfig/ram_trap_synd.rs
View File

@ -57,7 +57,7 @@ impl<'a> SYND_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
self.w.bits = value as u32;
self.w.bits = (self.w.bits & !0x000f_ffff) | (value as u32 & 0x000f_ffff);
self.w
}
}
@ -65,7 +65,7 @@ impl R {
#[doc = "Bits 0:19 - Trap Syndrom Bits"]
#[inline(always)]
pub fn synd(&self) -> SYND_R {
SYND_R::new(self.bits as u32)
SYND_R::new((self.bits & 0x000f_ffff) as u32)
}
}
impl W {

4
src/sysconfig/rom_prot.rs
View File

@ -67,7 +67,7 @@ impl<'a> WREN_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = value as u32;
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
@ -75,7 +75,7 @@ impl R {
#[doc = "Bit 0 - ROM Write Enable Bit"]
#[inline(always)]
pub fn wren(&self) -> WREN_R {
WREN_R::new(self.bits != 0)
WREN_R::new((self.bits & 0x01) != 0)
}
}
impl W {

4
src/sysconfig/rom_scrub.rs
View File

@ -57,7 +57,7 @@ impl<'a> VALUE_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
self.w.bits = value as u32;
self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
self.w
}
}
@ -87,7 +87,7 @@ impl R {
#[doc = "Bits 0:23 - Counter divide value"]
#[inline(always)]
pub fn value(&self) -> VALUE_R {
VALUE_R::new(self.bits as u32)
VALUE_R::new((self.bits & 0x00ff_ffff) as u32)
}
}
impl W {

4
src/sysconfig/rom_trap_synd.rs
View File

@ -57,7 +57,7 @@ impl<'a> SYND_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u32) -> &'a mut W {
self.w.bits = value as u32;
self.w.bits = (self.w.bits & !0x000f_ffff) | (value as u32 & 0x000f_ffff);
self.w
}
}
@ -65,7 +65,7 @@ impl R {
#[doc = "Bits 0:19 - Trap Syndrom Bits"]
#[inline(always)]
pub fn synd(&self) -> SYND_R {
SYND_R::new(self.bits as u32)
SYND_R::new((self.bits & 0x000f_ffff) as u32)
}
}
impl W {

4
src/sysconfig/rst_cntl_ram.rs
View File

@ -67,7 +67,7 @@ impl<'a> POR_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = value as u32;
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
@ -260,7 +260,7 @@ impl R {
#[doc = "Bit 0 - Power On Reset Status"]
#[inline(always)]
pub fn por(&self) -> POR_R {
POR_R::new(self.bits != 0)
POR_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 1 - External Reset Status"]
#[inline(always)]

4
src/sysconfig/rst_cntl_rom.rs
View File

@ -67,7 +67,7 @@ impl<'a> POR_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = value as u32;
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
@ -260,7 +260,7 @@ impl R {
#[doc = "Bit 0 - Power On Reset Status"]
#[inline(always)]
pub fn por(&self) -> POR_R {
POR_R::new(self.bits != 0)
POR_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 1 - External Reset Status"]
#[inline(always)]

4
src/sysconfig/rst_stat.rs
View File

@ -67,7 +67,7 @@ impl<'a> POR_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = value as u32;
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
@ -260,7 +260,7 @@ impl R {
#[doc = "Bit 0 - Power On Reset Status"]
#[inline(always)]
pub fn por(&self) -> POR_R {
POR_R::new(self.bits != 0)
POR_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 1 - External Reset Status"]
#[inline(always)]