Important fix: Use bitmask everywhere now

This PAC was generated using a patched version of svd2rust with
commit hash 43be074d21132c3a76780816010df592a3603874

It includes bugfix https://github.com/rust-embedded/svd2rust/pull/549

src/tim0/cascade0.rs

@@ -57,7 +57,7 @@ impl<'a> CASSEL_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
         self.w
     }
 }
@@ -65,7 +65,7 @@ impl R {
     #[doc = "Bits 0:7 - Cascade Selection"]
     #[inline(always)]
     pub fn cassel(&self) -> CASSEL_R {
-        CASSEL_R::new(self.bits as u8)
+        CASSEL_R::new((self.bits & 0xff) as u8)
     }
 }
 impl W {

src/tim0/cascade1.rs

@@ -57,7 +57,7 @@ impl<'a> CASSEL_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
         self.w
     }
 }
@@ -65,7 +65,7 @@ impl R {
     #[doc = "Bits 0:7 - Cascade Selection"]
     #[inline(always)]
     pub fn cassel(&self) -> CASSEL_R {
-        CASSEL_R::new(self.bits as u8)
+        CASSEL_R::new((self.bits & 0xff) as u8)
     }
 }
 impl W {

src/tim0/cascade2.rs

@@ -57,7 +57,7 @@ impl<'a> CASSEL_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
         self.w
     }
 }
@@ -65,7 +65,7 @@ impl R {
     #[doc = "Bits 0:7 - Cascade Selection"]
     #[inline(always)]
     pub fn cassel(&self) -> CASSEL_R {
-        CASSEL_R::new(self.bits as u8)
+        CASSEL_R::new((self.bits & 0xff) as u8)
     }
 }
 impl W {

src/tim0/csd_ctrl.rs

@@ -67,7 +67,7 @@ impl<'a> CSDEN0_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -408,7 +408,7 @@ impl R {
     #[doc = "Bit 0 - Cascade 0 Enable"]
     #[inline(always)]
     pub fn csden0(&self) -> CSDEN0_R {
-        CSDEN0_R::new(self.bits != 0)
+        CSDEN0_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Cascade 0 Invert"]
     #[inline(always)]

src/tim0/ctrl.rs

@@ -67,7 +67,7 @@ impl<'a> ENABLE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -416,7 +416,7 @@ impl R {
     #[doc = "Bit 0 - Counter Enable"]
     #[inline(always)]
     pub fn enable(&self) -> ENABLE_R {
-        ENABLE_R::new(self.bits != 0)
+        ENABLE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Counter Active"]
     #[inline(always)]

src/tim0/enable.rs

@@ -67,7 +67,7 @@ impl<'a> ENABLE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -75,7 +75,7 @@ impl R {
     #[doc = "Bit 0 - Counter Enable"]
     #[inline(always)]
     pub fn enable(&self) -> ENABLE_R {
-        ENABLE_R::new(self.bits != 0)
+        ENABLE_R::new((self.bits & 0x01) != 0)
     }
 }
 impl W {