Important fix: Use bitmask everywhere now

This PAC was generated using a patched version of svd2rust with
commit hash 43be074d21132c3a76780816010df592a3603874

It includes bugfix https://github.com/rust-embedded/svd2rust/pull/549

CHANGELOG.md

@@ -12,6 +12,12 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Relicensed under dual Apache-2.0 / MIT license
 
+### Fixed
+
+- Generated with patched version of `svd2rust`: See 
+  https://github.com/rust-embedded/svd2rust/pull/549 for more details.
+  Some bitmasks were missing from register reader definitions.
+
 ### Changed
 
 - SVD file handling improved and new fields added for the peripheral

src/i2ca/clkscale.rs

@@ -57,7 +57,7 @@ impl<'a> VALUE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x7fff_ffff) | (value as u32 & 0x7fff_ffff);
         self.w
     }
 }
@@ -102,7 +102,7 @@ impl R {
     #[doc = "Bits 0:30 - Enable FastMode"]
     #[inline(always)]
     pub fn value(&self) -> VALUE_R {
-        VALUE_R::new(self.bits as u32)
+        VALUE_R::new((self.bits & 0x7fff_ffff) as u32)
     }
     #[doc = "Bit 31 - Enable FastMode"]
     #[inline(always)]

src/i2ca/ctrl.rs

@@ -67,7 +67,7 @@ impl<'a> CLKENABLED_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -371,7 +371,7 @@ impl R {
     #[doc = "Bit 0 - I2C CLK Enabled"]
     #[inline(always)]
     pub fn clkenabled(&self) -> CLKENABLED_R {
-        CLKENABLED_R::new(self.bits != 0)
+        CLKENABLED_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - I2C Activated"]
     #[inline(always)]

src/i2ca/fifo_clr.rs

@@ -37,7 +37,7 @@ impl<'a> RXFIFO_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }

src/i2ca/irq_clr.rs

@@ -37,7 +37,7 @@ impl<'a> I2CIDLE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }

src/i2ca/irq_enb.rs

@@ -67,7 +67,7 @@ impl<'a> I2CIDLE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -556,7 +556,7 @@ impl R {
     #[doc = "Bit 0 - I2C Bus is Idle"]
     #[inline(always)]
     pub fn i2cidle(&self) -> I2CIDLE_R {
-        I2CIDLE_R::new(self.bits != 0)
+        I2CIDLE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]

src/i2ca/irq_end.rs

@@ -227,7 +227,7 @@ impl R {
     #[doc = "Bit 0 - I2C Bus is Idle"]
     #[inline(always)]
     pub fn i2cidle(&self) -> I2CIDLE_R {
-        I2CIDLE_R::new(self.bits != 0)
+        I2CIDLE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]

src/i2ca/irq_raw.rs

@@ -227,7 +227,7 @@ impl R {
     #[doc = "Bit 0 - I2C Bus is Idle"]
     #[inline(always)]
     pub fn i2cidle(&self) -> I2CIDLE_R {
-        I2CIDLE_R::new(self.bits != 0)
+        I2CIDLE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]

src/i2ca/s0_ctrl.rs

@@ -67,7 +67,7 @@ impl<'a> CLKENABLED_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -223,7 +223,7 @@ impl R {
     #[doc = "Bit 0 - I2C Enabled"]
     #[inline(always)]
     pub fn clkenabled(&self) -> CLKENABLED_R {
-        CLKENABLED_R::new(self.bits != 0)
+        CLKENABLED_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - I2C Activated"]
     #[inline(always)]

src/i2ca/s0_fifo_clr.rs

@@ -37,7 +37,7 @@ impl<'a> RXFIFO_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }

src/i2ca/s0_irq_clr.rs

@@ -37,7 +37,7 @@ impl<'a> COMPLETED_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }

src/i2ca/s0_irq_enb.rs

@@ -67,7 +67,7 @@ impl<'a> COMPLETED_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -630,7 +630,7 @@ impl R {
     #[doc = "Bit 0 - Controller Complted a Transaction"]
     #[inline(always)]
     pub fn completed(&self) -> COMPLETED_R {
-        COMPLETED_R::new(self.bits != 0)
+        COMPLETED_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]

src/i2ca/s0_irq_end.rs

@@ -257,7 +257,7 @@ impl R {
     #[doc = "Bit 0 - Controller Complted a Transaction"]
     #[inline(always)]
     pub fn completed(&self) -> COMPLETED_R {
-        COMPLETED_R::new(self.bits != 0)
+        COMPLETED_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]

src/i2ca/s0_irq_raw.rs

@@ -257,7 +257,7 @@ impl R {
     #[doc = "Bit 0 - Controller Complted a Transaction"]
     #[inline(always)]
     pub fn completed(&self) -> COMPLETED_R {
-        COMPLETED_R::new(self.bits != 0)
+        COMPLETED_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]

src/i2ca/s0_status.rs

@@ -272,7 +272,7 @@ impl R {
     #[doc = "Bit 0 - Controller Complted a Transaction"]
     #[inline(always)]
     pub fn completed(&self) -> COMPLETED_R {
-        COMPLETED_R::new(self.bits != 0)
+        COMPLETED_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Controller is Idle"]
     #[inline(always)]

src/ioconfig/porta.rs

@@ -158,7 +158,7 @@ impl<'a> FLTTYPE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
         self.w
     }
 }
@@ -516,7 +516,7 @@ impl R {
     #[doc = "Bits 0:2 - Input Filter Selectoin"]
     #[inline(always)]
     pub fn flttype(&self) -> FLTTYPE_R {
-        FLTTYPE_R::new(self.bits as u8)
+        FLTTYPE_R::new((self.bits & 0x07) as u8)
     }
     #[doc = "Bits 3:5 - Input Filter Clock Selection"]
     #[inline(always)]

src/ioconfig/portb.rs

@@ -158,7 +158,7 @@ impl<'a> FLTTYPE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
         self.w
     }
 }
@@ -516,7 +516,7 @@ impl R {
     #[doc = "Bits 0:2 - Input Filter Selectoin"]
     #[inline(always)]
     pub fn flttype(&self) -> FLTTYPE_R {
-        FLTTYPE_R::new(self.bits as u8)
+        FLTTYPE_R::new((self.bits & 0x07) as u8)
     }
     #[doc = "Bits 3:5 - Input Filter Clock Selection"]
     #[inline(always)]

src/irqsel/edbgrq.rs

@@ -32,7 +32,7 @@ impl R {
     #[doc = "Bit 0 - Active"]
     #[inline(always)]
     pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
     }
 }
 #[doc = "EDBGRQ Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [edbgrq](index.html) module"]

src/irqsel/irqs.rs

@@ -32,7 +32,7 @@ impl R {
     #[doc = "Bit 0 - Active"]
     #[inline(always)]
     pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
     }
 }
 #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irqs](index.html) module"]

src/irqsel/mereset.rs

@@ -32,7 +32,7 @@ impl R {
     #[doc = "Bit 0 - Active"]
     #[inline(always)]
     pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
     }
 }
 #[doc = "MERESET Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mereset](index.html) module"]

src/irqsel/nmi.rs

@@ -32,7 +32,7 @@ impl R {
     #[doc = "Bit 0 - Active"]
     #[inline(always)]
     pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
     }
 }
 #[doc = "NMI Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmi](index.html) module"]

src/irqsel/rxev.rs

@@ -32,7 +32,7 @@ impl R {
     #[doc = "Bit 0 - Active"]
     #[inline(always)]
     pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
     }
 }
 #[doc = "RXEV Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxev](index.html) module"]

src/irqsel/watchdog.rs

@@ -32,7 +32,7 @@ impl R {
     #[doc = "Bit 0 - Active"]
     #[inline(always)]
     pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
     }
 }
 #[doc = "WATCHDOG Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [watchdog](index.html) module"]

src/lib.rs

@@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.19.0 (58c0bb6 2021-11-02))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
+#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.19.0 (43be074 2021-11-09))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
 svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![deny(const_err)]
 #![deny(dead_code)]

src/spia/ctrl0.rs

@@ -57,7 +57,7 @@ impl<'a> SIZE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f);
         self.w
     }
 }
@@ -166,7 +166,7 @@ impl R {
     #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
     #[inline(always)]
     pub fn size(&self) -> SIZE_R {
-        SIZE_R::new(self.bits as u8)
+        SIZE_R::new((self.bits & 0x0f) as u8)
     }
     #[doc = "Bit 6 - SPI Clock Polarity"]
     #[inline(always)]

src/spia/ctrl1.rs

@@ -67,7 +67,7 @@ impl<'a> LBM_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -398,7 +398,7 @@ impl R {
     #[doc = "Bit 0 - Loop Back"]
     #[inline(always)]
     pub fn lbm(&self) -> LBM_R {
-        LBM_R::new(self.bits != 0)
+        LBM_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Enable"]
     #[inline(always)]

src/spia/fifo_clr.rs

@@ -37,7 +37,7 @@ impl<'a> RXFIFO_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }

src/spia/irq_clr.rs

@@ -37,7 +37,7 @@ impl<'a> RORIM_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }

src/spia/irq_enb.rs

@@ -67,7 +67,7 @@ impl<'a> RORIM_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -186,7 +186,7 @@ impl R {
     #[doc = "Bit 0 - RX Overrun"]
     #[inline(always)]
     pub fn rorim(&self) -> RORIM_R {
-        RORIM_R::new(self.bits != 0)
+        RORIM_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RX Timeout"]
     #[inline(always)]

src/spia/irq_end.rs

@@ -77,7 +77,7 @@ impl R {
     #[doc = "Bit 0 - RX Overrun"]
     #[inline(always)]
     pub fn rorim(&self) -> RORIM_R {
-        RORIM_R::new(self.bits != 0)
+        RORIM_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RX Timeout"]
     #[inline(always)]

src/spia/irq_raw.rs

@@ -77,7 +77,7 @@ impl R {
     #[doc = "Bit 0 - RX Overrun"]
     #[inline(always)]
     pub fn rorim(&self) -> RORIM_R {
-        RORIM_R::new(self.bits != 0)
+        RORIM_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RX Timeout"]
     #[inline(always)]

src/spia/status.rs

@@ -137,7 +137,7 @@ impl R {
     #[doc = "Bit 0 - Transmit FIFO empty"]
     #[inline(always)]
     pub fn tfe(&self) -> TFE_R {
-        TFE_R::new(self.bits != 0)
+        TFE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Transmit FIFO not full"]
     #[inline(always)]

src/sysconfig/irq_clr.rs

@@ -37,7 +37,7 @@ impl<'a> RAMSBE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }

src/sysconfig/irq_enb.rs

@@ -67,7 +67,7 @@ impl<'a> RAMSBE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -186,7 +186,7 @@ impl R {
     #[doc = "Bit 0 - RAM Single Bit Interrupt"]
     #[inline(always)]
     pub fn ramsbe(&self) -> RAMSBE_R {
-        RAMSBE_R::new(self.bits != 0)
+        RAMSBE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RAM Multi Bit Interrupt"]
     #[inline(always)]

src/sysconfig/irq_end.rs

@@ -77,7 +77,7 @@ impl R {
     #[doc = "Bit 0 - RAM Single Bit Interrupt"]
     #[inline(always)]
     pub fn ramsbe(&self) -> RAMSBE_R {
-        RAMSBE_R::new(self.bits != 0)
+        RAMSBE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RAM Multi Bit Interrupt"]
     #[inline(always)]

src/sysconfig/irq_raw.rs

@@ -77,7 +77,7 @@ impl R {
     #[doc = "Bit 0 - RAM Single Bit Interrupt"]
     #[inline(always)]
     pub fn ramsbe(&self) -> RAMSBE_R {
-        RAMSBE_R::new(self.bits != 0)
+        RAMSBE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RAM Multi Bit Interrupt"]
     #[inline(always)]

src/sysconfig/lockup_reset.rs

@@ -67,7 +67,7 @@ impl<'a> LREN_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -75,7 +75,7 @@ impl R {
     #[doc = "Bit 0 - Lockup Reset Enable Bit"]
     #[inline(always)]
     pub fn lren(&self) -> LREN_R {
-        LREN_R::new(self.bits != 0)
+        LREN_R::new((self.bits & 0x01) != 0)
     }
 }
 impl W {

src/sysconfig/peripheral_clk_enable.rs

@@ -67,7 +67,7 @@ impl<'a> PORTA_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -533,7 +533,7 @@ impl R {
     #[doc = "Bit 0 - Enable PORTA clock"]
     #[inline(always)]
     pub fn porta(&self) -> PORTA_R {
-        PORTA_R::new(self.bits != 0)
+        PORTA_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Enable PORTB clock"]
     #[inline(always)]

src/sysconfig/ram_scrub.rs

@@ -57,7 +57,7 @@ impl<'a> VALUE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
         self.w
     }
 }
@@ -87,7 +87,7 @@ impl R {
     #[doc = "Bits 0:23 - Counter divide value"]
     #[inline(always)]
     pub fn value(&self) -> VALUE_R {
-        VALUE_R::new(self.bits as u32)
+        VALUE_R::new((self.bits & 0x00ff_ffff) as u32)
     }
 }
 impl W {

src/sysconfig/ram_trap_synd.rs

@@ -57,7 +57,7 @@ impl<'a> SYND_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x000f_ffff) | (value as u32 & 0x000f_ffff);
         self.w
     }
 }
@@ -65,7 +65,7 @@ impl R {
     #[doc = "Bits 0:19 - Trap Syndrom Bits"]
     #[inline(always)]
     pub fn synd(&self) -> SYND_R {
-        SYND_R::new(self.bits as u32)
+        SYND_R::new((self.bits & 0x000f_ffff) as u32)
     }
 }
 impl W {

src/sysconfig/rom_prot.rs

@@ -67,7 +67,7 @@ impl<'a> WREN_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -75,7 +75,7 @@ impl R {
     #[doc = "Bit 0 - ROM Write Enable Bit"]
     #[inline(always)]
     pub fn wren(&self) -> WREN_R {
-        WREN_R::new(self.bits != 0)
+        WREN_R::new((self.bits & 0x01) != 0)
     }
 }
 impl W {

src/sysconfig/rom_scrub.rs

@@ -57,7 +57,7 @@ impl<'a> VALUE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
         self.w
     }
 }
@@ -87,7 +87,7 @@ impl R {
     #[doc = "Bits 0:23 - Counter divide value"]
     #[inline(always)]
     pub fn value(&self) -> VALUE_R {
-        VALUE_R::new(self.bits as u32)
+        VALUE_R::new((self.bits & 0x00ff_ffff) as u32)
     }
 }
 impl W {

src/sysconfig/rom_trap_synd.rs

@@ -57,7 +57,7 @@ impl<'a> SYND_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x000f_ffff) | (value as u32 & 0x000f_ffff);
         self.w
     }
 }
@@ -65,7 +65,7 @@ impl R {
     #[doc = "Bits 0:19 - Trap Syndrom Bits"]
     #[inline(always)]
     pub fn synd(&self) -> SYND_R {
-        SYND_R::new(self.bits as u32)
+        SYND_R::new((self.bits & 0x000f_ffff) as u32)
     }
 }
 impl W {

src/sysconfig/rst_cntl_ram.rs

@@ -67,7 +67,7 @@ impl<'a> POR_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -260,7 +260,7 @@ impl R {
     #[doc = "Bit 0 - Power On Reset Status"]
     #[inline(always)]
     pub fn por(&self) -> POR_R {
-        POR_R::new(self.bits != 0)
+        POR_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - External Reset Status"]
     #[inline(always)]

src/sysconfig/rst_cntl_rom.rs

@@ -67,7 +67,7 @@ impl<'a> POR_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -260,7 +260,7 @@ impl R {
     #[doc = "Bit 0 - Power On Reset Status"]
     #[inline(always)]
     pub fn por(&self) -> POR_R {
-        POR_R::new(self.bits != 0)
+        POR_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - External Reset Status"]
     #[inline(always)]

src/sysconfig/rst_stat.rs

@@ -67,7 +67,7 @@ impl<'a> POR_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -260,7 +260,7 @@ impl R {
     #[doc = "Bit 0 - Power On Reset Status"]
     #[inline(always)]
     pub fn por(&self) -> POR_R {
-        POR_R::new(self.bits != 0)
+        POR_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - External Reset Status"]
     #[inline(always)]

src/tim0/cascade0.rs

@@ -57,7 +57,7 @@ impl<'a> CASSEL_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
         self.w
     }
 }
@@ -65,7 +65,7 @@ impl R {
     #[doc = "Bits 0:7 - Cascade Selection"]
     #[inline(always)]
     pub fn cassel(&self) -> CASSEL_R {
-        CASSEL_R::new(self.bits as u8)
+        CASSEL_R::new((self.bits & 0xff) as u8)
     }
 }
 impl W {

src/tim0/cascade1.rs

@@ -57,7 +57,7 @@ impl<'a> CASSEL_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
         self.w
     }
 }
@@ -65,7 +65,7 @@ impl R {
     #[doc = "Bits 0:7 - Cascade Selection"]
     #[inline(always)]
     pub fn cassel(&self) -> CASSEL_R {
-        CASSEL_R::new(self.bits as u8)
+        CASSEL_R::new((self.bits & 0xff) as u8)
     }
 }
 impl W {

src/tim0/cascade2.rs

@@ -57,7 +57,7 @@ impl<'a> CASSEL_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
         self.w
     }
 }
@@ -65,7 +65,7 @@ impl R {
     #[doc = "Bits 0:7 - Cascade Selection"]
     #[inline(always)]
     pub fn cassel(&self) -> CASSEL_R {
-        CASSEL_R::new(self.bits as u8)
+        CASSEL_R::new((self.bits & 0xff) as u8)
     }
 }
 impl W {

src/tim0/csd_ctrl.rs

@@ -67,7 +67,7 @@ impl<'a> CSDEN0_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -408,7 +408,7 @@ impl R {
     #[doc = "Bit 0 - Cascade 0 Enable"]
     #[inline(always)]
     pub fn csden0(&self) -> CSDEN0_R {
-        CSDEN0_R::new(self.bits != 0)
+        CSDEN0_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Cascade 0 Invert"]
     #[inline(always)]

src/tim0/ctrl.rs

@@ -67,7 +67,7 @@ impl<'a> ENABLE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -416,7 +416,7 @@ impl R {
     #[doc = "Bit 0 - Counter Enable"]
     #[inline(always)]
     pub fn enable(&self) -> ENABLE_R {
-        ENABLE_R::new(self.bits != 0)
+        ENABLE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Counter Active"]
     #[inline(always)]

src/tim0/enable.rs

@@ -67,7 +67,7 @@ impl<'a> ENABLE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -75,7 +75,7 @@ impl R {
     #[doc = "Bit 0 - Counter Enable"]
     #[inline(always)]
     pub fn enable(&self) -> ENABLE_R {
-        ENABLE_R::new(self.bits != 0)
+        ENABLE_R::new((self.bits & 0x01) != 0)
     }
 }
 impl W {

src/uarta/clkscale.rs

@@ -57,7 +57,7 @@ impl<'a> FRAC_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f);
         self.w
     }
 }
@@ -114,7 +114,7 @@ impl R {
     #[doc = "Bits 0:5 - Fractional Divide (64ths)"]
     #[inline(always)]
     pub fn frac(&self) -> FRAC_R {
-        FRAC_R::new(self.bits as u8)
+        FRAC_R::new((self.bits & 0x3f) as u8)
     }
     #[doc = "Bits 6:23 - Integer Divide"]
     #[inline(always)]

src/uarta/ctrl.rs

@@ -67,7 +67,7 @@ impl<'a> PAREN_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -435,7 +435,7 @@ impl R {
     #[doc = "Bit 0 - Parity Enable"]
     #[inline(always)]
     pub fn paren(&self) -> PAREN_R {
-        PAREN_R::new(self.bits != 0)
+        PAREN_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Parity Even/Odd(1/0)"]
     #[inline(always)]

src/uarta/enable.rs

@@ -67,7 +67,7 @@ impl<'a> RXENABLE_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -112,7 +112,7 @@ impl R {
     #[doc = "Bit 0 - Rx Enable"]
     #[inline(always)]
     pub fn rxenable(&self) -> RXENABLE_R {
-        RXENABLE_R::new(self.bits != 0)
+        RXENABLE_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Tx Enable"]
     #[inline(always)]

src/uarta/fifo_clr.rs

@@ -37,7 +37,7 @@ impl<'a> RXSTS_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }

src/uarta/irq_clr.rs

@@ -37,7 +37,7 @@ impl<'a> IRQ_RX_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }

src/uarta/irq_enb.rs

@@ -67,7 +67,7 @@ impl<'a> IRQ_RX_W<'a> {
     #[doc = r"Writes raw bits to the field"]
     #[inline(always)]
     pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
         self.w
     }
 }
@@ -297,7 +297,7 @@ impl R {
     #[doc = "Bit 0 - RX Interrupt"]
     #[inline(always)]
     pub fn irq_rx(&self) -> IRQ_RX_R {
-        IRQ_RX_R::new(self.bits != 0)
+        IRQ_RX_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RX Status Interrupt"]
     #[inline(always)]

src/uarta/irq_end.rs

@@ -122,7 +122,7 @@ impl R {
     #[doc = "Bit 0 - RX Interrupt"]
     #[inline(always)]
     pub fn irq_rx(&self) -> IRQ_RX_R {
-        IRQ_RX_R::new(self.bits != 0)
+        IRQ_RX_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RX Status Interrupt"]
     #[inline(always)]

src/uarta/irq_raw.rs

@@ -122,7 +122,7 @@ impl R {
     #[doc = "Bit 0 - RX Interrupt"]
     #[inline(always)]
     pub fn irq_rx(&self) -> IRQ_RX_R {
-        IRQ_RX_R::new(self.bits != 0)
+        IRQ_RX_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - RX Status Interrupt"]
     #[inline(always)]

src/uarta/rxstatus.rs

@@ -182,7 +182,7 @@ impl R {
     #[doc = "Bit 0 - Read Data Available"]
     #[inline(always)]
     pub fn rdavl(&self) -> RDAVL_R {
-        RDAVL_R::new(self.bits != 0)
+        RDAVL_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Read Fifo NOT Full"]
     #[inline(always)]

src/uarta/txstatus.rs

@@ -92,7 +92,7 @@ impl R {
     #[doc = "Bit 0 - Write Fifo NOT Full"]
     #[inline(always)]
     pub fn wrrdy(&self) -> WRRDY_R {
-        WRRDY_R::new(self.bits != 0)
+        WRRDY_R::new((self.bits & 0x01) != 0)
     }
     #[doc = "Bit 1 - Write Fifo Full"]
     #[inline(always)]