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main ... v0.2.0

10 changed files with 15 additions and 772 deletions

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@ -16,7 +16,9 @@ jobs:
override: true
- uses: actions-rs/cargo@v1
with:
use-cross: true
command: check
args: --target thumbv6m-none-eabi
fmt:
name: Rustfmt
@ -48,8 +50,9 @@ jobs:
- run: rustup component add clippy
- uses: actions-rs/cargo@v1
with:
use-cross: true
command: clippy
args: -- -D warnings
args: --target thumbv6m-none-eabi -- -D warnings
ci:
if: ${{ success() }}

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@ -8,22 +8,6 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
## [unreleased]
## [v0.2.4]
- Added missing bitfield `CSDTRG2` in `CSD_CTRL` register of `TIM0` peripheral
## [v0.2.3]
- Added peripheral reset fields for `PERIPHERAL_RESET` register
## [v0.2.2]
- README tweks
## [v0.2.1]
- Some README and Manifest weaks
## [v0.2.0]
- Authorative repository was transferred to https://egit.irs.uni-stuttgart.de/rust/va108xx-rs but

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@ -1,11 +1,11 @@
[package]
name = "va108xx"
version = "0.2.4"
version = "0.2.0"
authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
edition = "2021"
description = "PAC for the Vorago VA108xx family of microcontrollers"
homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx"
repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx"
homepage = "https://github.com/robamu-org/va108xx-rs"
repository = "https://github.com/robamu-org/va108xx-rs"
license = "Apache-2.0"
keywords = ["no-std", "arm", "cortex-m", "vorago", "va108xx"]
categories = ["embedded", "no-std", "hardware-support"]

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@ -1,5 +1,5 @@
[![Crates.io](https://img.shields.io/crates/v/va108xx)](https://crates.io/crates/va108xx)
[![build](https://github.com/us-irs/va108xx-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/us-irs/va108xx-rs/actions/workflows/ci.yml)
[![build](https://github.com/robamu-org/va108xx-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/robamu-org/va108xx-rs/actions/workflows/ci.yml)
[![docs.rs](https://img.shields.io/docsrs/va108xx)](https://docs.rs/va108xx)
# PAC for the Vorago VA108xx microcontroller family
@ -9,18 +9,13 @@ Voragos VA108xx series of Cortex-M0 based microcontrollers.
The crate was generated using [`svd2rust`](https://github.com/rust-embedded/svd2rust).
If you are interested in higher-level abstractions, it is recommended you visit
the [`va108xx-hal` HAL crate](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal) and
the [`vorago-reb1` BSP crate](https://github.com/robamu-org/vorago-reb1-rs) which build on top of
this PAC and provide application examples as well.
## Usage
To use this crate, add this to your `Cargo.toml`
```toml
[dependencies.va108xx]
version = "<Most Recent Version>"
version = "0.1"
features = ["rt"]
```
@ -33,8 +28,7 @@ For full details on the autgenerated API, please see the
The base file used by `svd2rust` is generated using the `svdtools` package and a
YAML patch file. You can create the patched file by running this command after installing
the Python [`svdtools` package](https://github.com/stm32-rs/svdtools) and the `form` tool
with `cargo install form`:
the Python [`svdtools` package](https://github.com/stm32-rs/svdtools):
```sh
cd svd

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@ -24,7 +24,7 @@ pipeline {
sh 'cargo fmt'
}
}
stage('Check') {
stage('Build') {
agent {
dockerfile {
dir 'automation'
@ -32,7 +32,7 @@ pipeline {
}
}
steps {
sh 'cargo check --target thumbv6m-none-eabi'
sh 'cargo build'
}
}
}

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@ -1,4 +1,4 @@
#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.19.0 (b45bdce 2021-12-04))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.19.0 (877196f 2021-11-14))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
#![deny(const_err)]
#![deny(dead_code)]

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@ -34,620 +34,7 @@ impl From<crate::W<PERIPHERAL_RESET_SPEC>> for W {
W(writer)
}
}
#[doc = "Field `PORTA` reader - Reset PORTA"]
pub struct PORTA_R(crate::FieldReader<bool, bool>);
impl PORTA_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
PORTA_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for PORTA_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `PORTA` writer - Reset PORTA"]
pub struct PORTA_W<'a> {
w: &'a mut W,
}
impl<'a> PORTA_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
self.w
}
}
#[doc = "Field `PORTB` reader - Reset PORTB"]
pub struct PORTB_R(crate::FieldReader<bool, bool>);
impl PORTB_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
PORTB_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for PORTB_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `PORTB` writer - Reset PORTB"]
pub struct PORTB_W<'a> {
w: &'a mut W,
}
impl<'a> PORTB_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
self.w
}
}
#[doc = "Field `SPI_0` reader - Reset SPI\\[0\\]"]
pub struct SPI_0_R(crate::FieldReader<bool, bool>);
impl SPI_0_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
SPI_0_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for SPI_0_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `SPI_0` writer - Reset SPI\\[0\\]"]
pub struct SPI_0_W<'a> {
w: &'a mut W,
}
impl<'a> SPI_0_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
self.w
}
}
#[doc = "Field `SPI_1` reader - Reset SPI\\[1\\]"]
pub struct SPI_1_R(crate::FieldReader<bool, bool>);
impl SPI_1_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
SPI_1_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for SPI_1_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `SPI_1` writer - Reset SPI\\[1\\]"]
pub struct SPI_1_W<'a> {
w: &'a mut W,
}
impl<'a> SPI_1_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
self.w
}
}
#[doc = "Field `SPI_2` reader - Reset SPI\\[2\\]"]
pub struct SPI_2_R(crate::FieldReader<bool, bool>);
impl SPI_2_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
SPI_2_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for SPI_2_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `SPI_2` writer - Reset SPI\\[2\\]"]
pub struct SPI_2_W<'a> {
w: &'a mut W,
}
impl<'a> SPI_2_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
self.w
}
}
#[doc = "Field `UART_0` reader - Reset UART\\[0\\]"]
pub struct UART_0_R(crate::FieldReader<bool, bool>);
impl UART_0_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
UART_0_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for UART_0_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `UART_0` writer - Reset UART\\[0\\]"]
pub struct UART_0_W<'a> {
w: &'a mut W,
}
impl<'a> UART_0_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
self.w
}
}
#[doc = "Field `UART_1` reader - Reset UART\\[1\\]"]
pub struct UART_1_R(crate::FieldReader<bool, bool>);
impl UART_1_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
UART_1_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for UART_1_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `UART_1` writer - Reset UART\\[1\\]"]
pub struct UART_1_W<'a> {
w: &'a mut W,
}
impl<'a> UART_1_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
self.w
}
}
#[doc = "Field `I2C_0` reader - Reset I2C\\[0\\]"]
pub struct I2C_0_R(crate::FieldReader<bool, bool>);
impl I2C_0_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
I2C_0_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for I2C_0_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `I2C_0` writer - Reset I2C\\[0\\]"]
pub struct I2C_0_W<'a> {
w: &'a mut W,
}
impl<'a> I2C_0_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
self.w
}
}
#[doc = "Field `I2C_1` reader - Reset I2C\\[1\\]"]
pub struct I2C_1_R(crate::FieldReader<bool, bool>);
impl I2C_1_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
I2C_1_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for I2C_1_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `I2C_1` writer - Reset I2C\\[1\\]"]
pub struct I2C_1_W<'a> {
w: &'a mut W,
}
impl<'a> I2C_1_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
self.w
}
}
#[doc = "Field `IRQSEL` reader - Reset IRQ selector"]
pub struct IRQSEL_R(crate::FieldReader<bool, bool>);
impl IRQSEL_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
IRQSEL_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for IRQSEL_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `IRQSEL` writer - Reset IRQ selector"]
pub struct IRQSEL_W<'a> {
w: &'a mut W,
}
impl<'a> IRQSEL_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21);
self.w
}
}
#[doc = "Field `IOCONFIG` reader - Reset IO Configuration block"]
pub struct IOCONFIG_R(crate::FieldReader<bool, bool>);
impl IOCONFIG_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
IOCONFIG_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for IOCONFIG_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `IOCONFIG` writer - Reset IO Configuration block"]
pub struct IOCONFIG_W<'a> {
w: &'a mut W,
}
impl<'a> IOCONFIG_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
self.w
}
}
#[doc = "Field `UTILITY` reader - Reset Utility Block"]
pub struct UTILITY_R(crate::FieldReader<bool, bool>);
impl UTILITY_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
UTILITY_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for UTILITY_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `UTILITY` writer - Reset Utility Block"]
pub struct UTILITY_W<'a> {
w: &'a mut W,
}
impl<'a> UTILITY_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
self.w
}
}
#[doc = "Field `GPIO` reader - Reset GPIO"]
pub struct GPIO_R(crate::FieldReader<bool, bool>);
impl GPIO_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
GPIO_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for GPIO_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `GPIO` writer - Reset GPIO"]
pub struct GPIO_W<'a> {
w: &'a mut W,
}
impl<'a> GPIO_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24);
self.w
}
}
impl R {
#[doc = "Bit 0 - Reset PORTA"]
#[inline(always)]
pub fn porta(&self) -> PORTA_R {
PORTA_R::new((self.bits & 0x01) != 0)
}
#[doc = "Bit 1 - Reset PORTB"]
#[inline(always)]
pub fn portb(&self) -> PORTB_R {
PORTB_R::new(((self.bits >> 1) & 0x01) != 0)
}
#[doc = "Bit 4 - Reset SPI\\[0\\]"]
#[inline(always)]
pub fn spi_0(&self) -> SPI_0_R {
SPI_0_R::new(((self.bits >> 4) & 0x01) != 0)
}
#[doc = "Bit 5 - Reset SPI\\[1\\]"]
#[inline(always)]
pub fn spi_1(&self) -> SPI_1_R {
SPI_1_R::new(((self.bits >> 5) & 0x01) != 0)
}
#[doc = "Bit 6 - Reset SPI\\[2\\]"]
#[inline(always)]
pub fn spi_2(&self) -> SPI_2_R {
SPI_2_R::new(((self.bits >> 6) & 0x01) != 0)
}
#[doc = "Bit 8 - Reset UART\\[0\\]"]
#[inline(always)]
pub fn uart_0(&self) -> UART_0_R {
UART_0_R::new(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 9 - Reset UART\\[1\\]"]
#[inline(always)]
pub fn uart_1(&self) -> UART_1_R {
UART_1_R::new(((self.bits >> 9) & 0x01) != 0)
}
#[doc = "Bit 16 - Reset I2C\\[0\\]"]
#[inline(always)]
pub fn i2c_0(&self) -> I2C_0_R {
I2C_0_R::new(((self.bits >> 16) & 0x01) != 0)
}
#[doc = "Bit 17 - Reset I2C\\[1\\]"]
#[inline(always)]
pub fn i2c_1(&self) -> I2C_1_R {
I2C_1_R::new(((self.bits >> 17) & 0x01) != 0)
}
#[doc = "Bit 21 - Reset IRQ selector"]
#[inline(always)]
pub fn irqsel(&self) -> IRQSEL_R {
IRQSEL_R::new(((self.bits >> 21) & 0x01) != 0)
}
#[doc = "Bit 22 - Reset IO Configuration block"]
#[inline(always)]
pub fn ioconfig(&self) -> IOCONFIG_R {
IOCONFIG_R::new(((self.bits >> 22) & 0x01) != 0)
}
#[doc = "Bit 23 - Reset Utility Block"]
#[inline(always)]
pub fn utility(&self) -> UTILITY_R {
UTILITY_R::new(((self.bits >> 23) & 0x01) != 0)
}
#[doc = "Bit 24 - Reset GPIO"]
#[inline(always)]
pub fn gpio(&self) -> GPIO_R {
GPIO_R::new(((self.bits >> 24) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 0 - Reset PORTA"]
#[inline(always)]
pub fn porta(&mut self) -> PORTA_W {
PORTA_W { w: self }
}
#[doc = "Bit 1 - Reset PORTB"]
#[inline(always)]
pub fn portb(&mut self) -> PORTB_W {
PORTB_W { w: self }
}
#[doc = "Bit 4 - Reset SPI\\[0\\]"]
#[inline(always)]
pub fn spi_0(&mut self) -> SPI_0_W {
SPI_0_W { w: self }
}
#[doc = "Bit 5 - Reset SPI\\[1\\]"]
#[inline(always)]
pub fn spi_1(&mut self) -> SPI_1_W {
SPI_1_W { w: self }
}
#[doc = "Bit 6 - Reset SPI\\[2\\]"]
#[inline(always)]
pub fn spi_2(&mut self) -> SPI_2_W {
SPI_2_W { w: self }
}
#[doc = "Bit 8 - Reset UART\\[0\\]"]
#[inline(always)]
pub fn uart_0(&mut self) -> UART_0_W {
UART_0_W { w: self }
}
#[doc = "Bit 9 - Reset UART\\[1\\]"]
#[inline(always)]
pub fn uart_1(&mut self) -> UART_1_W {
UART_1_W { w: self }
}
#[doc = "Bit 16 - Reset I2C\\[0\\]"]
#[inline(always)]
pub fn i2c_0(&mut self) -> I2C_0_W {
I2C_0_W { w: self }
}
#[doc = "Bit 17 - Reset I2C\\[1\\]"]
#[inline(always)]
pub fn i2c_1(&mut self) -> I2C_1_W {
I2C_1_W { w: self }
}
#[doc = "Bit 21 - Reset IRQ selector"]
#[inline(always)]
pub fn irqsel(&mut self) -> IRQSEL_W {
IRQSEL_W { w: self }
}
#[doc = "Bit 22 - Reset IO Configuration block"]
#[inline(always)]
pub fn ioconfig(&mut self) -> IOCONFIG_W {
IOCONFIG_W { w: self }
}
#[doc = "Bit 23 - Reset Utility Block"]
#[inline(always)]
pub fn utility(&mut self) -> UTILITY_W {
UTILITY_W { w: self }
}
#[doc = "Bit 24 - Reset GPIO"]
#[inline(always)]
pub fn gpio(&mut self) -> GPIO_W {
GPIO_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {

View File

@ -404,43 +404,6 @@ impl<'a> CSDXXX2_W<'a> {
self.w
}
}
#[doc = "Field `CSDTRG2` reader - Cascade 2 Enabled as Trigger"]
pub struct CSDTRG2_R(crate::FieldReader<bool, bool>);
impl CSDTRG2_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
CSDTRG2_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for CSDTRG2_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `CSDTRG2` writer - Cascade 2 Enabled as Trigger"]
pub struct CSDTRG2_W<'a> {
w: &'a mut W,
}
impl<'a> CSDTRG2_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
self.w
}
}
impl R {
#[doc = "Bit 0 - Cascade 0 Enable"]
#[inline(always)]
@ -492,11 +455,6 @@ impl R {
pub fn csdxxx2(&self) -> CSDXXX2_R {
CSDXXX2_R::new(((self.bits >> 11) & 0x01) != 0)
}
#[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
#[inline(always)]
pub fn csdtrg2(&self) -> CSDTRG2_R {
CSDTRG2_R::new(((self.bits >> 10) & 0x01) != 0)
}
}
impl W {
#[doc = "Bit 0 - Cascade 0 Enable"]
@ -549,11 +507,6 @@ impl W {
pub fn csdxxx2(&mut self) -> CSDXXX2_W {
CSDXXX2_W { w: self }
}
#[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
#[inline(always)]
pub fn csdtrg2(&mut self) -> CSDTRG2_W {
CSDTRG2_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {

View File

@ -293,20 +293,7 @@
<description>Peripheral Reset Control</description>
<addressOffset>0x078</addressOffset>
<resetValue>0xFFFFFFFF</resetValue>
<fields><field><name>PORTA</name><description>Reset PORTA</description><bitOffset>0</bitOffset><bitWidth>1</bitWidth></field>
<field><name>PORTB</name><description>Reset PORTB</description><bitOffset>1</bitOffset><bitWidth>1</bitWidth></field>
<field><name>SPI_0</name><description>Reset SPI[0]</description><bitOffset>4</bitOffset><bitWidth>1</bitWidth></field>
<field><name>SPI_1</name><description>Reset SPI[1]</description><bitOffset>5</bitOffset><bitWidth>1</bitWidth></field>
<field><name>SPI_2</name><description>Reset SPI[2]</description><bitOffset>6</bitOffset><bitWidth>1</bitWidth></field>
<field><name>UART_0</name><description>Reset UART[0]</description><bitOffset>8</bitOffset><bitWidth>1</bitWidth></field>
<field><name>UART_1</name><description>Reset UART[1]</description><bitOffset>9</bitOffset><bitWidth>1</bitWidth></field>
<field><name>I2C_0</name><description>Reset I2C[0]</description><bitOffset>16</bitOffset><bitWidth>1</bitWidth></field>
<field><name>I2C_1</name><description>Reset I2C[1]</description><bitOffset>17</bitOffset><bitWidth>1</bitWidth></field>
<field><name>IRQSEL</name><description>Reset IRQ selector</description><bitOffset>21</bitOffset><bitWidth>1</bitWidth></field>
<field><name>IOCONFIG</name><description>Reset IO Configuration block</description><bitOffset>22</bitOffset><bitWidth>1</bitWidth></field>
<field><name>UTILITY</name><description>Reset Utility Block</description><bitOffset>23</bitOffset><bitWidth>1</bitWidth></field>
<field><name>GPIO</name><description>Reset GPIO</description><bitOffset>24</bitOffset><bitWidth>1</bitWidth></field>
</fields></register>
</register>
<register>
<name>PERIPHERAL_CLK_ENABLE</name>
<description>Peripheral Enable Control</description>
@ -1296,8 +1283,7 @@
<description>Cascade 2 test mode</description>
<bitRange>[11:11]</bitRange>
</field>
<field><name>CSDTRG2</name><description>Cascade 2 Enabled as Trigger</description><bitOffset>10</bitOffset><bitWidth>1</bitWidth></field>
</fields>
</fields>
</register>
<register>
<name>CASCADE0</name>

View File

@ -56,61 +56,6 @@ SYSCONFIG:
bitOffset: 24
bitWidth: 1
PERIPHERAL_RESET:
_add:
PORTA:
description: Reset PORTA
bitOffset: 0
bitWidth: 1
PORTB:
description: Reset PORTB
bitOffset: 1
bitWidth: 1
SPI_0:
description: Reset SPI[0]
bitOffset: 4
bitWidth: 1
SPI_1:
description: Reset SPI[1]
bitOffset: 5
bitWidth: 1
SPI_2:
description: Reset SPI[2]
bitOffset: 6
bitWidth: 1
UART_0:
description: Reset UART[0]
bitOffset: 8
bitWidth: 1
UART_1:
description: Reset UART[1]
bitOffset: 9
bitWidth: 1
I2C_0:
description: Reset I2C[0]
bitOffset: 16
bitWidth: 1
I2C_1:
description: Reset I2C[1]
bitOffset: 17
bitWidth: 1
IRQSEL:
description: Reset IRQ selector
bitOffset: 21
bitWidth: 1
IOCONFIG:
description: Reset IO Configuration block
bitOffset: 22
bitWidth: 1
UTILITY:
description: Reset Utility Block
bitOffset: 23
bitWidth: 1
GPIO:
description: Reset GPIO
bitOffset: 24
bitWidth: 1
# I2CB is derived from I2CA
I2CA:
_modify:
@ -126,12 +71,3 @@ I2CA:
description: Controller is Idle
bitOffset: 1
bitWidth: 1
# All TIMs are derived from TIM0
TIM0:
CSD_CTRL:
_add:
CSDTRG2:
description: Cascade 2 Enabled as Trigger
bitOffset: 10
bitWidth: 1