simplify CI

update HAL link
only use check instead of build for CI/CD
2021-12-13 00:11:40 +01:00 · 2021-12-06 15:55:59 +01:00 · 2021-12-06 13:10:13 +01:00 · 2021-12-06 12:53:30 +01:00 · 2021-12-06 12:24:55 +01:00 · 2021-12-06 12:21:06 +01:00
78 changed files with 7413 additions and 482 deletions
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@ -12,6 +12,7 @@ jobs:
        with:
          profile: minimal
          toolchain: stable
+          target: thumbv6m-none-eabi
          override: true
      - uses: actions-rs/cargo@v1
        with:
@ -42,6 +43,7 @@ jobs:
        with:
          profile: minimal
          toolchain: stable
+          target: thumbv6m-none-eabi
          override: true
      - run: rustup component add clippy
      - uses: actions-rs/cargo@v1
--- a/.gitignore
+++ b/.gitignore
@ -0,0 +1,6 @@
+# Generated by Cargo
+# will have compiled files and executables
+/target/
+
+# These are backup files generated by rustfmt
+**/*.rs.bk
--- a/CHANGELOG.md
+++ b/CHANGELOG.md
@ -6,11 +6,64 @@ All notable changes to this project will be documented in this file.
 The format is based on [Keep a Changelog](http://keepachangelog.com/)
 and this project adheres to [Semantic Versioning](http://semver.org/).

-## [Unreleased]
+## [unreleased]
+
+## [v0.2.4]
+
+- Added missing bitfield `CSDTRG2` in `CSD_CTRL` register of `TIM0` peripheral
+
+## [v0.2.3]
+
+- Added peripheral reset fields for `PERIPHERAL_RESET` register
+
+## [v0.2.2]
+
+- README tweks
+
+## [v0.2.1]
+
+- Some README and Manifest weaks
+
+## [v0.2.0]
+
+- Authorative repository was transferred to https://egit.irs.uni-stuttgart.de/rust/va108xx-rs but
+  there still will be a GitHub mirror. Project relicensed as Apache-2.0 only
+
+## [v0.1.3]
+
+### Added
+
+- Added two missing bit fields for I2CA STATUS register: I2CIDLE and IDLE
+
+### Fixed
+
+- Made I2CA STATUS register read-only
+
+## [v0.1.2]
+
+### Fixed
+
+- Generated with patched version of `svd2rust`: See 
+  https://github.com/rust-embedded/svd2rust/pull/549 for more details.
+  Some bitmasks were missing from register reader definitions.
+
+## [v0.1.1]
+
+- Relicensed under dual Apache-2.0 / MIT license
+
+### Changed
+
+- SVD file handling improved and new fields added for the peripheral
+  clock enable register
+
+### Added
+
+- Helper script to automate all steps for PAC generation
+- Added badges for README

 ## [v0.1.0]

 ### Added

 - First version of the PAC which builds. Uses a patched version
-  of `svd2rust`: https://github.com/rust-embedded/svd2rust
+  of `svd2rust`: https://github.com/rust-embedded/svd2rust
--- a/Cargo.toml
+++ b/Cargo.toml
@ -1,13 +1,14 @@
 [package]
 name = "va108xx"
-version = "0.1.0"
-edition = "2018"
-description = "Peripheral access API for Vorago VA108XX microcontrollers"
-license = "0BSD"
-homepage = "https://github.com/robamu-org/va108xx-rs"
-repository = "https://github.com/robamu-org/va108xx-rs"
+version = "0.2.4"
+authors = ["Robin Mueller <muellerr@irs.uni-stuttgart.de>"]
+edition = "2021"
+description = "PAC for the Vorago VA108xx family of microcontrollers"
+homepage = "https://egit.irs.uni-stuttgart.de/rust/va108xx"
+repository = "https://egit.irs.uni-stuttgart.de/rust/va108xx"
+license = "Apache-2.0"
 keywords = ["no-std", "arm", "cortex-m", "vorago", "va108xx"]
-authors = ["Robin Mueller <robin.mueller.m@gmail.com>"]
+categories = ["embedded", "no-std", "hardware-support"]

 [dependencies]
 cortex-m = "0.7.3"
--- a/10
+++ b/10
@ -1,10 +0,0 @@
-Permission to use, copy, modify, and/or distribute this software for
-any purpose with or without fee is hereby granted.
-
-THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN
-AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT
-OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--- a/201
+++ b/201
@ -0,0 +1,201 @@
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--- a/3
+++ b/3
@ -0,0 +1,3 @@
+Peripheral access crate for the Vorago VA108xx family microcontrollers
+
+This software contains code developed at the University of Stuttgart.
--- a/README.md
+++ b/README.md
@ -1,6 +1,44 @@
+[![Crates.io](https://img.shields.io/crates/v/va108xx)](https://crates.io/crates/va108xx)
+[![build](https://github.com/us-irs/va108xx-rs/actions/workflows/ci.yml/badge.svg)](https://github.com/us-irs/va108xx-rs/actions/workflows/ci.yml)
+[![docs.rs](https://img.shields.io/docsrs/va108xx)](https://docs.rs/va108xx)
+
 # PAC for the Vorago VA108xx microcontroller family

 This repository contains the Peripheral Access Crate (PAC) for
 Voragos VA108xx series of Cortex-M0 based microcontrollers.

 The crate was generated using [`svd2rust`](https://github.com/rust-embedded/svd2rust).
+
+If you are interested in higher-level abstractions, it is recommended you visit
+the [`va108xx-hal` HAL crate](https://egit.irs.uni-stuttgart.de/rust/va108xx-hal) and
+the [`vorago-reb1` BSP crate](https://github.com/robamu-org/vorago-reb1-rs) which build on top of
+this PAC and provide application examples as well.
+
+## Usage
+
+To use this crate, add this to your `Cargo.toml`
+
+```toml
+[dependencies.va108xx]
+version = "<Most Recent Version>"
+features = ["rt"]
+```
+
+The `rt` feature is optional and recommended. It brings in support for `cortex-m-rt`.
+
+For full details on the autgenerated API, please see the
+[svd2rust documentation](https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api).
+
+## Regenerating the PAC
+
+The base file used by `svd2rust` is generated using the `svdtools` package and a
+YAML patch file. You can create the patched file by running this command after installing
+the Python [`svdtools` package](https://github.com/stm32-rs/svdtools) and the `form` tool
+with `cargo install form`:
+
+```sh
+cd svd
+svd patch va108xx-patch.yml
+```
+
+After that, you can regenerate the PAC by running the `gen-helper.sh` helper script.
--- a/automation/Dockerfile
+++ b/automation/Dockerfile
@ -0,0 +1,11 @@
+# Run the following commands from root directory to build and run locally
+# docker build -f automation/Dockerfile -t <NAME> .
+# docker run -it <NAME>
+FROM rust:latest
+RUN apt-get update
+RUN apt-get --yes upgrade
+# tzdata is a dependency, won't install otherwise
+ARG DEBIAN_FRONTEND=noninteractive
+
+RUN rustup target add thumbv6m-none-eabi && \
+	rustup component add rustfmt clippy
--- a/automation/Jenkinsfile
+++ b/automation/Jenkinsfile
@ -0,0 +1,39 @@
+pipeline {
+    agent any
+
+    stages {
+        stage('Clippy') {
+            agent {
+                dockerfile {
+                    dir 'automation'
+                    reuseNode true
+                }
+            }
+            steps {
+                sh 'cargo clippy'
+            }
+        }
+        stage('Rustfmt') {
+            agent {
+                dockerfile {
+                    dir 'automation'
+                    reuseNode true
+                }
+            }
+            steps {
+                sh 'cargo fmt'
+            }
+        }
+        stage('Check') {
+            agent {
+                dockerfile {
+                    dir 'automation'
+                    reuseNode true
+                }
+            }
+            steps {
+                sh 'cargo check --target thumbv6m-none-eabi'
+            }
+        }
+    }
+}
--- a/gen-helper.sh
+++ b/gen-helper.sh
@ -0,0 +1,21 @@
+#!/bin/sh
+
+# Use installed tool by default
+svd2rust_bin="svd2rust"
+# Automates the steps specified in https://docs.rs/svd2rust/0.19.0/svd2rust/
+if [ -f svd2rust ]; then
+	# If the local directory contains svd2rust, use that version instead
+	svd2rust_bin="./svd2rust"
+elif [ -f ../svd2rust ]; then
+	# Keeps the repository clean
+	svd2rust_bin="../svd2rust"
+fi
+if [ -x "$(${svd2rust_bin} --version)" ]; then
+	echo "No svd2rust found locally or installed." \
+		"Install it with cargo install svd2rust"
+	exit
+fi
+${svd2rust_bin} -i svd/va108xx-base.svd.patched
+rm -rf src
+form -i lib.rs -o src/ && rm lib.rs
+cargo fmt
--- a/src/i2ca/clkscale.rs
+++ b/src/i2ca/clkscale.rs
@ -57,7 +57,7 @@ impl<'a> VALUE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x7fff_ffff) | (value as u32 & 0x7fff_ffff);
        self.w
    }
 }
@ -102,7 +102,7 @@ impl R {
    #[doc = "Bits 0:30 - Enable FastMode"]
    #[inline(always)]
    pub fn value(&self) -> VALUE_R {
-        VALUE_R::new(self.bits as u32)
+        VALUE_R::new((self.bits & 0x7fff_ffff) as u32)
    }
    #[doc = "Bit 31 - Enable FastMode"]
    #[inline(always)]
--- a/src/i2ca/ctrl.rs
+++ b/src/i2ca/ctrl.rs
@ -67,7 +67,7 @@ impl<'a> CLKENABLED_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -371,7 +371,7 @@ impl R {
    #[doc = "Bit 0 - I2C CLK Enabled"]
    #[inline(always)]
    pub fn clkenabled(&self) -> CLKENABLED_R {
-        CLKENABLED_R::new(self.bits != 0)
+        CLKENABLED_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - I2C Activated"]
    #[inline(always)]
--- a/src/i2ca/fifo_clr.rs
+++ b/src/i2ca/fifo_clr.rs
@ -37,7 +37,7 @@ impl<'a> RXFIFO_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
--- a/src/i2ca/irq_clr.rs
+++ b/src/i2ca/irq_clr.rs
@ -37,7 +37,7 @@ impl<'a> I2CIDLE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
--- a/src/i2ca/irq_enb.rs
+++ b/src/i2ca/irq_enb.rs
@ -67,7 +67,7 @@ impl<'a> I2CIDLE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -556,7 +556,7 @@ impl R {
    #[doc = "Bit 0 - I2C Bus is Idle"]
    #[inline(always)]
    pub fn i2cidle(&self) -> I2CIDLE_R {
-        I2CIDLE_R::new(self.bits != 0)
+        I2CIDLE_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Controller is Idle"]
    #[inline(always)]
--- a/src/i2ca/irq_end.rs
+++ b/src/i2ca/irq_end.rs
@ -227,7 +227,7 @@ impl R {
    #[doc = "Bit 0 - I2C Bus is Idle"]
    #[inline(always)]
    pub fn i2cidle(&self) -> I2CIDLE_R {
-        I2CIDLE_R::new(self.bits != 0)
+        I2CIDLE_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Controller is Idle"]
    #[inline(always)]
--- a/src/i2ca/irq_raw.rs
+++ b/src/i2ca/irq_raw.rs
@ -227,7 +227,7 @@ impl R {
    #[doc = "Bit 0 - I2C Bus is Idle"]
    #[inline(always)]
    pub fn i2cidle(&self) -> I2CIDLE_R {
-        I2CIDLE_R::new(self.bits != 0)
+        I2CIDLE_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Controller is Idle"]
    #[inline(always)]
--- a/src/i2ca/s0_ctrl.rs
+++ b/src/i2ca/s0_ctrl.rs
@ -67,7 +67,7 @@ impl<'a> CLKENABLED_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -223,7 +223,7 @@ impl R {
    #[doc = "Bit 0 - I2C Enabled"]
    #[inline(always)]
    pub fn clkenabled(&self) -> CLKENABLED_R {
-        CLKENABLED_R::new(self.bits != 0)
+        CLKENABLED_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - I2C Activated"]
    #[inline(always)]
--- a/src/i2ca/s0_fifo_clr.rs
+++ b/src/i2ca/s0_fifo_clr.rs
@ -37,7 +37,7 @@ impl<'a> RXFIFO_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
--- a/src/i2ca/s0_irq_clr.rs
+++ b/src/i2ca/s0_irq_clr.rs
@ -37,7 +37,7 @@ impl<'a> COMPLETED_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
--- a/src/i2ca/s0_irq_enb.rs
+++ b/src/i2ca/s0_irq_enb.rs
@ -67,7 +67,7 @@ impl<'a> COMPLETED_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -630,7 +630,7 @@ impl R {
    #[doc = "Bit 0 - Controller Complted a Transaction"]
    #[inline(always)]
    pub fn completed(&self) -> COMPLETED_R {
-        COMPLETED_R::new(self.bits != 0)
+        COMPLETED_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Controller is Idle"]
    #[inline(always)]
--- a/src/i2ca/s0_irq_end.rs
+++ b/src/i2ca/s0_irq_end.rs
@ -257,7 +257,7 @@ impl R {
    #[doc = "Bit 0 - Controller Complted a Transaction"]
    #[inline(always)]
    pub fn completed(&self) -> COMPLETED_R {
-        COMPLETED_R::new(self.bits != 0)
+        COMPLETED_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Controller is Idle"]
    #[inline(always)]
--- a/src/i2ca/s0_irq_raw.rs
+++ b/src/i2ca/s0_irq_raw.rs
@ -257,7 +257,7 @@ impl R {
    #[doc = "Bit 0 - Controller Complted a Transaction"]
    #[inline(always)]
    pub fn completed(&self) -> COMPLETED_R {
-        COMPLETED_R::new(self.bits != 0)
+        COMPLETED_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Controller is Idle"]
    #[inline(always)]
--- a/src/i2ca/s0_status.rs
+++ b/src/i2ca/s0_status.rs
@ -272,7 +272,7 @@ impl R {
    #[doc = "Bit 0 - Controller Complted a Transaction"]
    #[inline(always)]
    pub fn completed(&self) -> COMPLETED_R {
-        COMPLETED_R::new(self.bits != 0)
+        COMPLETED_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Controller is Idle"]
    #[inline(always)]
--- a/src/i2ca/status.rs
+++ b/src/i2ca/status.rs
@ -13,27 +13,6 @@ impl From<crate::R<STATUS_SPEC>> for R {
        R(reader)
    }
 }
-#[doc = "Register `STATUS` writer"]
-pub struct W(crate::W<STATUS_SPEC>);
-impl core::ops::Deref for W {
-    type Target = crate::W<STATUS_SPEC>;
-    #[inline(always)]
-    fn deref(&self) -> &Self::Target {
-        &self.0
-    }
-}
-impl core::ops::DerefMut for W {
-    #[inline(always)]
-    fn deref_mut(&mut self) -> &mut Self::Target {
-        &mut self.0
-    }
-}
-impl From<crate::W<STATUS_SPEC>> for W {
-    #[inline(always)]
-    fn from(writer: crate::W<STATUS_SPEC>) -> Self {
-        W(writer)
-    }
-}
 #[doc = "Field `WAITING` reader - Controller is Waiting"]
 pub struct WAITING_R(crate::FieldReader<bool, bool>);
 impl WAITING_R {
@ -49,28 +28,6 @@ impl core::ops::Deref for WAITING_R {
        &self.0
    }
 }
-#[doc = "Field `WAITING` writer - Controller is Waiting"]
-pub struct WAITING_W<'a> {
-    w: &'a mut W,
-}
-impl<'a> WAITING_W<'a> {
-    #[doc = r"Sets the field bit"]
-    #[inline(always)]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r"Clears the field bit"]
-    #[inline(always)]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r"Writes raw bits to the field"]
-    #[inline(always)]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
-        self.w
-    }
-}
 #[doc = "Field `STALLED` reader - Controller is Stalled"]
 pub struct STALLED_R(crate::FieldReader<bool, bool>);
 impl STALLED_R {
@ -86,28 +43,6 @@ impl core::ops::Deref for STALLED_R {
        &self.0
    }
 }
-#[doc = "Field `STALLED` writer - Controller is Stalled"]
-pub struct STALLED_W<'a> {
-    w: &'a mut W,
-}
-impl<'a> STALLED_W<'a> {
-    #[doc = r"Sets the field bit"]
-    #[inline(always)]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r"Clears the field bit"]
-    #[inline(always)]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r"Writes raw bits to the field"]
-    #[inline(always)]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
-        self.w
-    }
-}
 #[doc = "Field `ARBLOST` reader - I2C Arbitration was lost"]
 pub struct ARBLOST_R(crate::FieldReader<bool, bool>);
 impl ARBLOST_R {
@ -123,28 +58,6 @@ impl core::ops::Deref for ARBLOST_R {
        &self.0
    }
 }
-#[doc = "Field `ARBLOST` writer - I2C Arbitration was lost"]
-pub struct ARBLOST_W<'a> {
-    w: &'a mut W,
-}
-impl<'a> ARBLOST_W<'a> {
-    #[doc = r"Sets the field bit"]
-    #[inline(always)]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r"Clears the field bit"]
-    #[inline(always)]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r"Writes raw bits to the field"]
-    #[inline(always)]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
-        self.w
-    }
-}
 #[doc = "Field `NACKADDR` reader - I2C Address was not Acknowledged"]
 pub struct NACKADDR_R(crate::FieldReader<bool, bool>);
 impl NACKADDR_R {
@ -160,28 +73,6 @@ impl core::ops::Deref for NACKADDR_R {
        &self.0
    }
 }
-#[doc = "Field `NACKADDR` writer - I2C Address was not Acknowledged"]
-pub struct NACKADDR_W<'a> {
-    w: &'a mut W,
-}
-impl<'a> NACKADDR_W<'a> {
-    #[doc = r"Sets the field bit"]
-    #[inline(always)]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r"Clears the field bit"]
-    #[inline(always)]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r"Writes raw bits to the field"]
-    #[inline(always)]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
-        self.w
-    }
-}
 #[doc = "Field `NACKDATA` reader - I2C Data was not Acknowledged"]
 pub struct NACKDATA_R(crate::FieldReader<bool, bool>);
 impl NACKDATA_R {
@ -197,28 +88,6 @@ impl core::ops::Deref for NACKDATA_R {
        &self.0
    }
 }
-#[doc = "Field `NACKDATA` writer - I2C Data was not Acknowledged"]
-pub struct NACKDATA_W<'a> {
-    w: &'a mut W,
-}
-impl<'a> NACKDATA_W<'a> {
-    #[doc = r"Sets the field bit"]
-    #[inline(always)]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r"Clears the field bit"]
-    #[inline(always)]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r"Writes raw bits to the field"]
-    #[inline(always)]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
-        self.w
-    }
-}
 #[doc = "Field `RXNEMPTY` reader - RX FIFO is Not Empty"]
 pub struct RXNEMPTY_R(crate::FieldReader<bool, bool>);
 impl RXNEMPTY_R {
@ -234,28 +103,6 @@ impl core::ops::Deref for RXNEMPTY_R {
        &self.0
    }
 }
-#[doc = "Field `RXNEMPTY` writer - RX FIFO is Not Empty"]
-pub struct RXNEMPTY_W<'a> {
-    w: &'a mut W,
-}
-impl<'a> RXNEMPTY_W<'a> {
-    #[doc = r"Sets the field bit"]
-    #[inline(always)]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r"Clears the field bit"]
-    #[inline(always)]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r"Writes raw bits to the field"]
-    #[inline(always)]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
-        self.w
-    }
-}
 #[doc = "Field `RXFULL` reader - RX FIFO is Full"]
 pub struct RXFULL_R(crate::FieldReader<bool, bool>);
 impl RXFULL_R {
@ -271,28 +118,6 @@ impl core::ops::Deref for RXFULL_R {
        &self.0
    }
 }
-#[doc = "Field `RXFULL` writer - RX FIFO is Full"]
-pub struct RXFULL_W<'a> {
-    w: &'a mut W,
-}
-impl<'a> RXFULL_W<'a> {
-    #[doc = r"Sets the field bit"]
-    #[inline(always)]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r"Clears the field bit"]
-    #[inline(always)]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r"Writes raw bits to the field"]
-    #[inline(always)]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
-        self.w
-    }
-}
 #[doc = "Field `RXTRIGGER` reader - RX FIFO Above Trigger Level"]
 pub struct RXTRIGGER_R(crate::FieldReader<bool, bool>);
 impl RXTRIGGER_R {
@ -308,28 +133,6 @@ impl core::ops::Deref for RXTRIGGER_R {
        &self.0
    }
 }
-#[doc = "Field `RXTRIGGER` writer - RX FIFO Above Trigger Level"]
-pub struct RXTRIGGER_W<'a> {
-    w: &'a mut W,
-}
-impl<'a> RXTRIGGER_W<'a> {
-    #[doc = r"Sets the field bit"]
-    #[inline(always)]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r"Clears the field bit"]
-    #[inline(always)]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r"Writes raw bits to the field"]
-    #[inline(always)]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 11)) | ((value as u32 & 0x01) << 11);
-        self.w
-    }
-}
 #[doc = "Field `TXEMPTY` reader - TX FIFO is Empty"]
 pub struct TXEMPTY_R(crate::FieldReader<bool, bool>);
 impl TXEMPTY_R {
@ -345,28 +148,6 @@ impl core::ops::Deref for TXEMPTY_R {
        &self.0
    }
 }
-#[doc = "Field `TXEMPTY` writer - TX FIFO is Empty"]
-pub struct TXEMPTY_W<'a> {
-    w: &'a mut W,
-}
-impl<'a> TXEMPTY_W<'a> {
-    #[doc = r"Sets the field bit"]
-    #[inline(always)]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r"Clears the field bit"]
-    #[inline(always)]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r"Writes raw bits to the field"]
-    #[inline(always)]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 12)) | ((value as u32 & 0x01) << 12);
-        self.w
-    }
-}
 #[doc = "Field `TXNFULL` reader - TX FIFO is Full"]
 pub struct TXNFULL_R(crate::FieldReader<bool, bool>);
 impl TXNFULL_R {
@ -382,28 +163,6 @@ impl core::ops::Deref for TXNFULL_R {
        &self.0
    }
 }
-#[doc = "Field `TXNFULL` writer - TX FIFO is Full"]
-pub struct TXNFULL_W<'a> {
-    w: &'a mut W,
-}
-impl<'a> TXNFULL_W<'a> {
-    #[doc = r"Sets the field bit"]
-    #[inline(always)]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r"Clears the field bit"]
-    #[inline(always)]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r"Writes raw bits to the field"]
-    #[inline(always)]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 13)) | ((value as u32 & 0x01) << 13);
-        self.w
-    }
-}
 #[doc = "Field `TXTRIGGER` reader - TX FIFO Below Trigger Level"]
 pub struct TXTRIGGER_R(crate::FieldReader<bool, bool>);
 impl TXTRIGGER_R {
@ -419,28 +178,6 @@ impl core::ops::Deref for TXTRIGGER_R {
        &self.0
    }
 }
-#[doc = "Field `TXTRIGGER` writer - TX FIFO Below Trigger Level"]
-pub struct TXTRIGGER_W<'a> {
-    w: &'a mut W,
-}
-impl<'a> TXTRIGGER_W<'a> {
-    #[doc = r"Sets the field bit"]
-    #[inline(always)]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r"Clears the field bit"]
-    #[inline(always)]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r"Writes raw bits to the field"]
-    #[inline(always)]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 15)) | ((value as u32 & 0x01) << 15);
-        self.w
-    }
-}
 #[doc = "Field `RAW_SDA` reader - I2C Raw SDA value"]
 pub struct RAW_SDA_R(crate::FieldReader<bool, bool>);
 impl RAW_SDA_R {
@ -456,28 +193,6 @@ impl core::ops::Deref for RAW_SDA_R {
        &self.0
    }
 }
-#[doc = "Field `RAW_SDA` writer - I2C Raw SDA value"]
-pub struct RAW_SDA_W<'a> {
-    w: &'a mut W,
-}
-impl<'a> RAW_SDA_W<'a> {
-    #[doc = r"Sets the field bit"]
-    #[inline(always)]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
-    }
-    #[doc = r"Clears the field bit"]
-    #[inline(always)]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
-    }
-    #[doc = r"Writes raw bits to the field"]
-    #[inline(always)]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 30)) | ((value as u32 & 0x01) << 30);
-        self.w
-    }
-}
 #[doc = "Field `RAW_SCL` reader - I2C Raw SCL value"]
 pub struct RAW_SCL_R(crate::FieldReader<bool, bool>);
 impl RAW_SCL_R {
@ -493,26 +208,34 @@ impl core::ops::Deref for RAW_SCL_R {
        &self.0
    }
 }
-#[doc = "Field `RAW_SCL` writer - I2C Raw SCL value"]
-pub struct RAW_SCL_W<'a> {
-    w: &'a mut W,
+#[doc = "Field `I2C_IDLE` reader - I2C bus is Idle"]
+pub struct I2C_IDLE_R(crate::FieldReader<bool, bool>);
+impl I2C_IDLE_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2C_IDLE_R(crate::FieldReader::new(bits))
+    }
 }
-impl<'a> RAW_SCL_W<'a> {
-    #[doc = r"Sets the field bit"]
+impl core::ops::Deref for I2C_IDLE_R {
+    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
-    pub fn set_bit(self) -> &'a mut W {
-        self.bit(true)
+    fn deref(&self) -> &Self::Target {
+        &self.0
    }
-    #[doc = r"Clears the field bit"]
+}
+#[doc = "Field `IDLE` reader - Controller is Idle"]
+pub struct IDLE_R(crate::FieldReader<bool, bool>);
+impl IDLE_R {
    #[inline(always)]
-    pub fn clear_bit(self) -> &'a mut W {
-        self.bit(false)
+    pub(crate) fn new(bits: bool) -> Self {
+        IDLE_R(crate::FieldReader::new(bits))
    }
-    #[doc = r"Writes raw bits to the field"]
+}
+impl core::ops::Deref for IDLE_R {
+    type Target = crate::FieldReader<bool, bool>;
    #[inline(always)]
-    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = (self.w.bits & !(0x01 << 31)) | ((value as u32 & 0x01) << 31);
-        self.w
+    fn deref(&self) -> &Self::Target {
+        &self.0
    }
 }
 impl R {
@ -581,81 +304,18 @@ impl R {
    pub fn raw_scl(&self) -> RAW_SCL_R {
        RAW_SCL_R::new(((self.bits >> 31) & 0x01) != 0)
    }
-}
-impl W {
-    #[doc = "Bit 2 - Controller is Waiting"]
+    #[doc = "Bit 0 - I2C bus is Idle"]
    #[inline(always)]
-    pub fn waiting(&mut self) -> WAITING_W {
-        WAITING_W { w: self }
+    pub fn i2c_idle(&self) -> I2C_IDLE_R {
+        I2C_IDLE_R::new((self.bits & 0x01) != 0)
    }
-    #[doc = "Bit 3 - Controller is Stalled"]
+    #[doc = "Bit 1 - Controller is Idle"]
    #[inline(always)]
-    pub fn stalled(&mut self) -> STALLED_W {
-        STALLED_W { w: self }
-    }
-    #[doc = "Bit 4 - I2C Arbitration was lost"]
-    #[inline(always)]
-    pub fn arblost(&mut self) -> ARBLOST_W {
-        ARBLOST_W { w: self }
-    }
-    #[doc = "Bit 5 - I2C Address was not Acknowledged"]
-    #[inline(always)]
-    pub fn nackaddr(&mut self) -> NACKADDR_W {
-        NACKADDR_W { w: self }
-    }
-    #[doc = "Bit 6 - I2C Data was not Acknowledged"]
-    #[inline(always)]
-    pub fn nackdata(&mut self) -> NACKDATA_W {
-        NACKDATA_W { w: self }
-    }
-    #[doc = "Bit 8 - RX FIFO is Not Empty"]
-    #[inline(always)]
-    pub fn rxnempty(&mut self) -> RXNEMPTY_W {
-        RXNEMPTY_W { w: self }
-    }
-    #[doc = "Bit 9 - RX FIFO is Full"]
-    #[inline(always)]
-    pub fn rxfull(&mut self) -> RXFULL_W {
-        RXFULL_W { w: self }
-    }
-    #[doc = "Bit 11 - RX FIFO Above Trigger Level"]
-    #[inline(always)]
-    pub fn rxtrigger(&mut self) -> RXTRIGGER_W {
-        RXTRIGGER_W { w: self }
-    }
-    #[doc = "Bit 12 - TX FIFO is Empty"]
-    #[inline(always)]
-    pub fn txempty(&mut self) -> TXEMPTY_W {
-        TXEMPTY_W { w: self }
-    }
-    #[doc = "Bit 13 - TX FIFO is Full"]
-    #[inline(always)]
-    pub fn txnfull(&mut self) -> TXNFULL_W {
-        TXNFULL_W { w: self }
-    }
-    #[doc = "Bit 15 - TX FIFO Below Trigger Level"]
-    #[inline(always)]
-    pub fn txtrigger(&mut self) -> TXTRIGGER_W {
-        TXTRIGGER_W { w: self }
-    }
-    #[doc = "Bit 30 - I2C Raw SDA value"]
-    #[inline(always)]
-    pub fn raw_sda(&mut self) -> RAW_SDA_W {
-        RAW_SDA_W { w: self }
-    }
-    #[doc = "Bit 31 - I2C Raw SCL value"]
-    #[inline(always)]
-    pub fn raw_scl(&mut self) -> RAW_SCL_W {
-        RAW_SCL_W { w: self }
-    }
-    #[doc = "Writes raw bits to the register."]
-    #[inline(always)]
-    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
-        self.0.bits(bits);
-        self
+    pub fn idle(&self) -> IDLE_R {
+        IDLE_R::new(((self.bits >> 1) & 0x01) != 0)
    }
 }
-#[doc = "I2C Controller Status Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
+#[doc = "I2C Controller Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [status](index.html) module"]
 pub struct STATUS_SPEC;
 impl crate::RegisterSpec for STATUS_SPEC {
    type Ux = u32;
@ -664,10 +324,6 @@ impl crate::RegisterSpec for STATUS_SPEC {
 impl crate::Readable for STATUS_SPEC {
    type Reader = R;
 }
-#[doc = "`write(|w| ..)` method takes [status::W](W) writer structure"]
-impl crate::Writable for STATUS_SPEC {
-    type Writer = W;
-}
 #[doc = "`reset()` method sets STATUS to value 0"]
 impl crate::Resettable for STATUS_SPEC {
    #[inline(always)]
--- a/src/ioconfig/porta.rs
+++ b/src/ioconfig/porta.rs
@ -158,7 +158,7 @@ impl<'a> FLTTYPE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
        self.w
    }
 }
@ -516,7 +516,7 @@ impl R {
    #[doc = "Bits 0:2 - Input Filter Selectoin"]
    #[inline(always)]
    pub fn flttype(&self) -> FLTTYPE_R {
-        FLTTYPE_R::new(self.bits as u8)
+        FLTTYPE_R::new((self.bits & 0x07) as u8)
    }
    #[doc = "Bits 3:5 - Input Filter Clock Selection"]
    #[inline(always)]
--- a/src/ioconfig/portb.rs
+++ b/src/ioconfig/portb.rs
@ -158,7 +158,7 @@ impl<'a> FLTTYPE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x07) | (value as u32 & 0x07);
        self.w
    }
 }
@ -516,7 +516,7 @@ impl R {
    #[doc = "Bits 0:2 - Input Filter Selectoin"]
    #[inline(always)]
    pub fn flttype(&self) -> FLTTYPE_R {
-        FLTTYPE_R::new(self.bits as u8)
+        FLTTYPE_R::new((self.bits & 0x07) as u8)
    }
    #[doc = "Bits 3:5 - Input Filter Clock Selection"]
    #[inline(always)]
--- a/src/irqsel/edbgrq.rs
+++ b/src/irqsel/edbgrq.rs
@ -32,7 +32,7 @@ impl R {
    #[doc = "Bit 0 - Active"]
    #[inline(always)]
    pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
    }
 }
 #[doc = "EDBGRQ Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [edbgrq](index.html) module"]
--- a/src/irqsel/irqs.rs
+++ b/src/irqsel/irqs.rs
@ -32,7 +32,7 @@ impl R {
    #[doc = "Bit 0 - Active"]
    #[inline(always)]
    pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
    }
 }
 #[doc = "Interrupt Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irqs](index.html) module"]
--- a/src/irqsel/mereset.rs
+++ b/src/irqsel/mereset.rs
@ -32,7 +32,7 @@ impl R {
    #[doc = "Bit 0 - Active"]
    #[inline(always)]
    pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
    }
 }
 #[doc = "MERESET Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [mereset](index.html) module"]
--- a/src/irqsel/nmi.rs
+++ b/src/irqsel/nmi.rs
@ -32,7 +32,7 @@ impl R {
    #[doc = "Bit 0 - Active"]
    #[inline(always)]
    pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
    }
 }
 #[doc = "NMI Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [nmi](index.html) module"]
--- a/src/irqsel/rxev.rs
+++ b/src/irqsel/rxev.rs
@ -32,7 +32,7 @@ impl R {
    #[doc = "Bit 0 - Active"]
    #[inline(always)]
    pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
    }
 }
 #[doc = "RXEV Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [rxev](index.html) module"]
--- a/src/irqsel/watchdog.rs
+++ b/src/irqsel/watchdog.rs
@ -32,7 +32,7 @@ impl R {
    #[doc = "Bit 0 - Active"]
    #[inline(always)]
    pub fn active(&self) -> ACTIVE_R {
-        ACTIVE_R::new(self.bits != 0)
+        ACTIVE_R::new((self.bits & 0x01) != 0)
    }
 }
 #[doc = "WATCHDOG Status Register\n\nThis register you can [`read`](crate::generic::Reg::read). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [watchdog](index.html) module"]
--- a/src/lib.rs
+++ b/src/lib.rs
@ -1,4 +1,4 @@
-#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.19.0 (af91938 2021-11-01))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
+#![doc = "Peripheral access API for VA108XX microcontrollers (generated using svd2rust v0.19.0 (b45bdce 2021-12-04))\n\nYou can find an overview of the generated API [here].\n\nAPI features to be included in the [next]
 svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.\n\n[here]: https://docs.rs/svd2rust/0.19.0/svd2rust/#peripheral-api\n[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased\n[repository]: https://github.com/rust-embedded/svd2rust"]
 #![deny(const_err)]
 #![deny(dead_code)]
--- a/src/spia/ctrl0.rs
+++ b/src/spia/ctrl0.rs
@ -57,7 +57,7 @@ impl<'a> SIZE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f);
        self.w
    }
 }
@ -166,7 +166,7 @@ impl R {
    #[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
    #[inline(always)]
    pub fn size(&self) -> SIZE_R {
-        SIZE_R::new(self.bits as u8)
+        SIZE_R::new((self.bits & 0x0f) as u8)
    }
    #[doc = "Bit 6 - SPI Clock Polarity"]
    #[inline(always)]
--- a/src/spia/ctrl1.rs
+++ b/src/spia/ctrl1.rs
@ -67,7 +67,7 @@ impl<'a> LBM_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -398,7 +398,7 @@ impl R {
    #[doc = "Bit 0 - Loop Back"]
    #[inline(always)]
    pub fn lbm(&self) -> LBM_R {
-        LBM_R::new(self.bits != 0)
+        LBM_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Enable"]
    #[inline(always)]
--- a/src/spia/fifo_clr.rs
+++ b/src/spia/fifo_clr.rs
@ -37,7 +37,7 @@ impl<'a> RXFIFO_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
--- a/src/spia/irq_clr.rs
+++ b/src/spia/irq_clr.rs
@ -37,7 +37,7 @@ impl<'a> RORIM_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
--- a/src/spia/irq_enb.rs
+++ b/src/spia/irq_enb.rs
@ -67,7 +67,7 @@ impl<'a> RORIM_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -186,7 +186,7 @@ impl R {
    #[doc = "Bit 0 - RX Overrun"]
    #[inline(always)]
    pub fn rorim(&self) -> RORIM_R {
-        RORIM_R::new(self.bits != 0)
+        RORIM_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - RX Timeout"]
    #[inline(always)]
--- a/src/spia/irq_end.rs
+++ b/src/spia/irq_end.rs
@ -77,7 +77,7 @@ impl R {
    #[doc = "Bit 0 - RX Overrun"]
    #[inline(always)]
    pub fn rorim(&self) -> RORIM_R {
-        RORIM_R::new(self.bits != 0)
+        RORIM_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - RX Timeout"]
    #[inline(always)]
--- a/src/spia/irq_raw.rs
+++ b/src/spia/irq_raw.rs
@ -77,7 +77,7 @@ impl R {
    #[doc = "Bit 0 - RX Overrun"]
    #[inline(always)]
    pub fn rorim(&self) -> RORIM_R {
-        RORIM_R::new(self.bits != 0)
+        RORIM_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - RX Timeout"]
    #[inline(always)]
--- a/src/spia/status.rs
+++ b/src/spia/status.rs
@ -137,7 +137,7 @@ impl R {
    #[doc = "Bit 0 - Transmit FIFO empty"]
    #[inline(always)]
    pub fn tfe(&self) -> TFE_R {
-        TFE_R::new(self.bits != 0)
+        TFE_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Transmit FIFO not full"]
    #[inline(always)]
--- a/src/sysconfig/irq_clr.rs
+++ b/src/sysconfig/irq_clr.rs
@ -37,7 +37,7 @@ impl<'a> RAMSBE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
--- a/src/sysconfig/irq_enb.rs
+++ b/src/sysconfig/irq_enb.rs
@ -67,7 +67,7 @@ impl<'a> RAMSBE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -186,7 +186,7 @@ impl R {
    #[doc = "Bit 0 - RAM Single Bit Interrupt"]
    #[inline(always)]
    pub fn ramsbe(&self) -> RAMSBE_R {
-        RAMSBE_R::new(self.bits != 0)
+        RAMSBE_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - RAM Multi Bit Interrupt"]
    #[inline(always)]
--- a/src/sysconfig/irq_end.rs
+++ b/src/sysconfig/irq_end.rs
@ -77,7 +77,7 @@ impl R {
    #[doc = "Bit 0 - RAM Single Bit Interrupt"]
    #[inline(always)]
    pub fn ramsbe(&self) -> RAMSBE_R {
-        RAMSBE_R::new(self.bits != 0)
+        RAMSBE_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - RAM Multi Bit Interrupt"]
    #[inline(always)]
--- a/src/sysconfig/irq_raw.rs
+++ b/src/sysconfig/irq_raw.rs
@ -77,7 +77,7 @@ impl R {
    #[doc = "Bit 0 - RAM Single Bit Interrupt"]
    #[inline(always)]
    pub fn ramsbe(&self) -> RAMSBE_R {
-        RAMSBE_R::new(self.bits != 0)
+        RAMSBE_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - RAM Multi Bit Interrupt"]
    #[inline(always)]
--- a/src/sysconfig/lockup_reset.rs
+++ b/src/sysconfig/lockup_reset.rs
@ -67,7 +67,7 @@ impl<'a> LREN_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -75,7 +75,7 @@ impl R {
    #[doc = "Bit 0 - Lockup Reset Enable Bit"]
    #[inline(always)]
    pub fn lren(&self) -> LREN_R {
-        LREN_R::new(self.bits != 0)
+        LREN_R::new((self.bits & 0x01) != 0)
    }
 }
 impl W {
--- a/src/sysconfig/peripheral_clk_enable.rs
+++ b/src/sysconfig/peripheral_clk_enable.rs
@ -34,7 +34,648 @@ impl From<crate::W<PERIPHERAL_CLK_ENABLE_SPEC>> for W {
        W(writer)
    }
 }
+#[doc = "Field `PORTA` reader - Enable PORTA clock"]
+pub struct PORTA_R(crate::FieldReader<bool, bool>);
+impl PORTA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        PORTA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PORTA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PORTA` writer - Enable PORTA clock"]
+pub struct PORTA_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> PORTA_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+        self.w
+    }
+}
+#[doc = "Field `PORTB` reader - Enable PORTB clock"]
+pub struct PORTB_R(crate::FieldReader<bool, bool>);
+impl PORTB_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        PORTB_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PORTB_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PORTB` writer - Enable PORTB clock"]
+pub struct PORTB_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> PORTB_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `SPI_0` reader - Enable SPI\\[0\\]
+clock"]
+pub struct SPI_0_R(crate::FieldReader<bool, bool>);
+impl SPI_0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SPI_0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SPI_0_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SPI_0` writer - Enable SPI\\[0\\]
+clock"]
+pub struct SPI_0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SPI_0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `SPI_1` reader - Enable SPI\\[1\\]
+clock"]
+pub struct SPI_1_R(crate::FieldReader<bool, bool>);
+impl SPI_1_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SPI_1_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SPI_1_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SPI_1` writer - Enable SPI\\[1\\]
+clock"]
+pub struct SPI_1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SPI_1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Field `SPI_2` reader - Enable SPI\\[2\\]
+clock"]
+pub struct SPI_2_R(crate::FieldReader<bool, bool>);
+impl SPI_2_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SPI_2_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SPI_2_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SPI_2` writer - Enable SPI\\[2\\]
+clock"]
+pub struct SPI_2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SPI_2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Field `UART_0` reader - Enable UART\\[0\\]
+clock"]
+pub struct UART_0_R(crate::FieldReader<bool, bool>);
+impl UART_0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        UART_0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for UART_0_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `UART_0` writer - Enable UART\\[0\\]
+clock"]
+pub struct UART_0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> UART_0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Field `UART_1` reader - Enable UART\\[1\\]
+clock"]
+pub struct UART_1_R(crate::FieldReader<bool, bool>);
+impl UART_1_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        UART_1_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for UART_1_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `UART_1` writer - Enable UART\\[1\\]
+clock"]
+pub struct UART_1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> UART_1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "Field `I2C_0` reader - Enable I2C\\[0\\]
+clock"]
+pub struct I2C_0_R(crate::FieldReader<bool, bool>);
+impl I2C_0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2C_0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2C_0_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `I2C_0` writer - Enable I2C\\[0\\]
+clock"]
+pub struct I2C_0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> I2C_0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
+        self.w
+    }
+}
+#[doc = "Field `I2C_1` reader - Enable I2C\\[1\\]
+clock"]
+pub struct I2C_1_R(crate::FieldReader<bool, bool>);
+impl I2C_1_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2C_1_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2C_1_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `I2C_1` writer - Enable I2C\\[1\\]
+clock"]
+pub struct I2C_1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> I2C_1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
+        self.w
+    }
+}
+#[doc = "Field `IRQSEL` reader - Enable IRQ selector clock"]
+pub struct IRQSEL_R(crate::FieldReader<bool, bool>);
+impl IRQSEL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IRQSEL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IRQSEL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IRQSEL` writer - Enable IRQ selector clock"]
+pub struct IRQSEL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IRQSEL_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21);
+        self.w
+    }
+}
+#[doc = "Field `IOCONFIG` reader - Enable IO Configuration block clock"]
+pub struct IOCONFIG_R(crate::FieldReader<bool, bool>);
+impl IOCONFIG_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IOCONFIG_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IOCONFIG_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IOCONFIG` writer - Enable IO Configuration block clock"]
+pub struct IOCONFIG_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IOCONFIG_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
+        self.w
+    }
+}
+#[doc = "Field `UTILITY` reader - Enable utility clock"]
+pub struct UTILITY_R(crate::FieldReader<bool, bool>);
+impl UTILITY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        UTILITY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for UTILITY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `UTILITY` writer - Enable utility clock"]
+pub struct UTILITY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> UTILITY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
+        self.w
+    }
+}
+#[doc = "Field `GPIO` reader - Enable GPIO clock"]
+pub struct GPIO_R(crate::FieldReader<bool, bool>);
+impl GPIO_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        GPIO_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for GPIO_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `GPIO` writer - Enable GPIO clock"]
+pub struct GPIO_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> GPIO_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Enable PORTA clock"]
+    #[inline(always)]
+    pub fn porta(&self) -> PORTA_R {
+        PORTA_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - Enable PORTB clock"]
+    #[inline(always)]
+    pub fn portb(&self) -> PORTB_R {
+        PORTB_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - Enable SPI\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_0(&self) -> SPI_0_R {
+        SPI_0_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - Enable SPI\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_1(&self) -> SPI_1_R {
+        SPI_1_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - Enable SPI\\[2\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_2(&self) -> SPI_2_R {
+        SPI_2_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - Enable UART\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn uart_0(&self) -> UART_0_R {
+        UART_0_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - Enable UART\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn uart_1(&self) -> UART_1_R {
+        UART_1_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 16 - Enable I2C\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn i2c_0(&self) -> I2C_0_R {
+        I2C_0_R::new(((self.bits >> 16) & 0x01) != 0)
+    }
+    #[doc = "Bit 17 - Enable I2C\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn i2c_1(&self) -> I2C_1_R {
+        I2C_1_R::new(((self.bits >> 17) & 0x01) != 0)
+    }
+    #[doc = "Bit 21 - Enable IRQ selector clock"]
+    #[inline(always)]
+    pub fn irqsel(&self) -> IRQSEL_R {
+        IRQSEL_R::new(((self.bits >> 21) & 0x01) != 0)
+    }
+    #[doc = "Bit 22 - Enable IO Configuration block clock"]
+    #[inline(always)]
+    pub fn ioconfig(&self) -> IOCONFIG_R {
+        IOCONFIG_R::new(((self.bits >> 22) & 0x01) != 0)
+    }
+    #[doc = "Bit 23 - Enable utility clock"]
+    #[inline(always)]
+    pub fn utility(&self) -> UTILITY_R {
+        UTILITY_R::new(((self.bits >> 23) & 0x01) != 0)
+    }
+    #[doc = "Bit 24 - Enable GPIO clock"]
+    #[inline(always)]
+    pub fn gpio(&self) -> GPIO_R {
+        GPIO_R::new(((self.bits >> 24) & 0x01) != 0)
+    }
+}
 impl W {
+    #[doc = "Bit 0 - Enable PORTA clock"]
+    #[inline(always)]
+    pub fn porta(&mut self) -> PORTA_W {
+        PORTA_W { w: self }
+    }
+    #[doc = "Bit 1 - Enable PORTB clock"]
+    #[inline(always)]
+    pub fn portb(&mut self) -> PORTB_W {
+        PORTB_W { w: self }
+    }
+    #[doc = "Bit 4 - Enable SPI\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_0(&mut self) -> SPI_0_W {
+        SPI_0_W { w: self }
+    }
+    #[doc = "Bit 5 - Enable SPI\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_1(&mut self) -> SPI_1_W {
+        SPI_1_W { w: self }
+    }
+    #[doc = "Bit 6 - Enable SPI\\[2\\]
+clock"]
+    #[inline(always)]
+    pub fn spi_2(&mut self) -> SPI_2_W {
+        SPI_2_W { w: self }
+    }
+    #[doc = "Bit 8 - Enable UART\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn uart_0(&mut self) -> UART_0_W {
+        UART_0_W { w: self }
+    }
+    #[doc = "Bit 9 - Enable UART\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn uart_1(&mut self) -> UART_1_W {
+        UART_1_W { w: self }
+    }
+    #[doc = "Bit 16 - Enable I2C\\[0\\]
+clock"]
+    #[inline(always)]
+    pub fn i2c_0(&mut self) -> I2C_0_W {
+        I2C_0_W { w: self }
+    }
+    #[doc = "Bit 17 - Enable I2C\\[1\\]
+clock"]
+    #[inline(always)]
+    pub fn i2c_1(&mut self) -> I2C_1_W {
+        I2C_1_W { w: self }
+    }
+    #[doc = "Bit 21 - Enable IRQ selector clock"]
+    #[inline(always)]
+    pub fn irqsel(&mut self) -> IRQSEL_W {
+        IRQSEL_W { w: self }
+    }
+    #[doc = "Bit 22 - Enable IO Configuration block clock"]
+    #[inline(always)]
+    pub fn ioconfig(&mut self) -> IOCONFIG_W {
+        IOCONFIG_W { w: self }
+    }
+    #[doc = "Bit 23 - Enable utility clock"]
+    #[inline(always)]
+    pub fn utility(&mut self) -> UTILITY_W {
+        UTILITY_W { w: self }
+    }
+    #[doc = "Bit 24 - Enable GPIO clock"]
+    #[inline(always)]
+    pub fn gpio(&mut self) -> GPIO_W {
+        GPIO_W { w: self }
+    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
--- a/src/sysconfig/peripheral_reset.rs
+++ b/src/sysconfig/peripheral_reset.rs
@ -34,7 +34,620 @@ impl From<crate::W<PERIPHERAL_RESET_SPEC>> for W {
        W(writer)
    }
 }
+#[doc = "Field `PORTA` reader - Reset PORTA"]
+pub struct PORTA_R(crate::FieldReader<bool, bool>);
+impl PORTA_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        PORTA_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PORTA_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PORTA` writer - Reset PORTA"]
+pub struct PORTA_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> PORTA_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
+        self.w
+    }
+}
+#[doc = "Field `PORTB` reader - Reset PORTB"]
+pub struct PORTB_R(crate::FieldReader<bool, bool>);
+impl PORTB_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        PORTB_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for PORTB_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `PORTB` writer - Reset PORTB"]
+pub struct PORTB_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> PORTB_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
+        self.w
+    }
+}
+#[doc = "Field `SPI_0` reader - Reset SPI\\[0\\]"]
+pub struct SPI_0_R(crate::FieldReader<bool, bool>);
+impl SPI_0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SPI_0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SPI_0_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SPI_0` writer - Reset SPI\\[0\\]"]
+pub struct SPI_0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SPI_0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 4)) | ((value as u32 & 0x01) << 4);
+        self.w
+    }
+}
+#[doc = "Field `SPI_1` reader - Reset SPI\\[1\\]"]
+pub struct SPI_1_R(crate::FieldReader<bool, bool>);
+impl SPI_1_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SPI_1_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SPI_1_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SPI_1` writer - Reset SPI\\[1\\]"]
+pub struct SPI_1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SPI_1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 5)) | ((value as u32 & 0x01) << 5);
+        self.w
+    }
+}
+#[doc = "Field `SPI_2` reader - Reset SPI\\[2\\]"]
+pub struct SPI_2_R(crate::FieldReader<bool, bool>);
+impl SPI_2_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        SPI_2_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for SPI_2_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `SPI_2` writer - Reset SPI\\[2\\]"]
+pub struct SPI_2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> SPI_2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
+        self.w
+    }
+}
+#[doc = "Field `UART_0` reader - Reset UART\\[0\\]"]
+pub struct UART_0_R(crate::FieldReader<bool, bool>);
+impl UART_0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        UART_0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for UART_0_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `UART_0` writer - Reset UART\\[0\\]"]
+pub struct UART_0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> UART_0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 8)) | ((value as u32 & 0x01) << 8);
+        self.w
+    }
+}
+#[doc = "Field `UART_1` reader - Reset UART\\[1\\]"]
+pub struct UART_1_R(crate::FieldReader<bool, bool>);
+impl UART_1_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        UART_1_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for UART_1_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `UART_1` writer - Reset UART\\[1\\]"]
+pub struct UART_1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> UART_1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 9)) | ((value as u32 & 0x01) << 9);
+        self.w
+    }
+}
+#[doc = "Field `I2C_0` reader - Reset I2C\\[0\\]"]
+pub struct I2C_0_R(crate::FieldReader<bool, bool>);
+impl I2C_0_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2C_0_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2C_0_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `I2C_0` writer - Reset I2C\\[0\\]"]
+pub struct I2C_0_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> I2C_0_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 16)) | ((value as u32 & 0x01) << 16);
+        self.w
+    }
+}
+#[doc = "Field `I2C_1` reader - Reset I2C\\[1\\]"]
+pub struct I2C_1_R(crate::FieldReader<bool, bool>);
+impl I2C_1_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        I2C_1_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for I2C_1_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `I2C_1` writer - Reset I2C\\[1\\]"]
+pub struct I2C_1_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> I2C_1_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 17)) | ((value as u32 & 0x01) << 17);
+        self.w
+    }
+}
+#[doc = "Field `IRQSEL` reader - Reset IRQ selector"]
+pub struct IRQSEL_R(crate::FieldReader<bool, bool>);
+impl IRQSEL_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IRQSEL_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IRQSEL_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IRQSEL` writer - Reset IRQ selector"]
+pub struct IRQSEL_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IRQSEL_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 21)) | ((value as u32 & 0x01) << 21);
+        self.w
+    }
+}
+#[doc = "Field `IOCONFIG` reader - Reset IO Configuration block"]
+pub struct IOCONFIG_R(crate::FieldReader<bool, bool>);
+impl IOCONFIG_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        IOCONFIG_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for IOCONFIG_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `IOCONFIG` writer - Reset IO Configuration block"]
+pub struct IOCONFIG_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> IOCONFIG_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 22)) | ((value as u32 & 0x01) << 22);
+        self.w
+    }
+}
+#[doc = "Field `UTILITY` reader - Reset Utility Block"]
+pub struct UTILITY_R(crate::FieldReader<bool, bool>);
+impl UTILITY_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        UTILITY_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for UTILITY_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `UTILITY` writer - Reset Utility Block"]
+pub struct UTILITY_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> UTILITY_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 23)) | ((value as u32 & 0x01) << 23);
+        self.w
+    }
+}
+#[doc = "Field `GPIO` reader - Reset GPIO"]
+pub struct GPIO_R(crate::FieldReader<bool, bool>);
+impl GPIO_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        GPIO_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for GPIO_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `GPIO` writer - Reset GPIO"]
+pub struct GPIO_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> GPIO_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 24)) | ((value as u32 & 0x01) << 24);
+        self.w
+    }
+}
+impl R {
+    #[doc = "Bit 0 - Reset PORTA"]
+    #[inline(always)]
+    pub fn porta(&self) -> PORTA_R {
+        PORTA_R::new((self.bits & 0x01) != 0)
+    }
+    #[doc = "Bit 1 - Reset PORTB"]
+    #[inline(always)]
+    pub fn portb(&self) -> PORTB_R {
+        PORTB_R::new(((self.bits >> 1) & 0x01) != 0)
+    }
+    #[doc = "Bit 4 - Reset SPI\\[0\\]"]
+    #[inline(always)]
+    pub fn spi_0(&self) -> SPI_0_R {
+        SPI_0_R::new(((self.bits >> 4) & 0x01) != 0)
+    }
+    #[doc = "Bit 5 - Reset SPI\\[1\\]"]
+    #[inline(always)]
+    pub fn spi_1(&self) -> SPI_1_R {
+        SPI_1_R::new(((self.bits >> 5) & 0x01) != 0)
+    }
+    #[doc = "Bit 6 - Reset SPI\\[2\\]"]
+    #[inline(always)]
+    pub fn spi_2(&self) -> SPI_2_R {
+        SPI_2_R::new(((self.bits >> 6) & 0x01) != 0)
+    }
+    #[doc = "Bit 8 - Reset UART\\[0\\]"]
+    #[inline(always)]
+    pub fn uart_0(&self) -> UART_0_R {
+        UART_0_R::new(((self.bits >> 8) & 0x01) != 0)
+    }
+    #[doc = "Bit 9 - Reset UART\\[1\\]"]
+    #[inline(always)]
+    pub fn uart_1(&self) -> UART_1_R {
+        UART_1_R::new(((self.bits >> 9) & 0x01) != 0)
+    }
+    #[doc = "Bit 16 - Reset I2C\\[0\\]"]
+    #[inline(always)]
+    pub fn i2c_0(&self) -> I2C_0_R {
+        I2C_0_R::new(((self.bits >> 16) & 0x01) != 0)
+    }
+    #[doc = "Bit 17 - Reset I2C\\[1\\]"]
+    #[inline(always)]
+    pub fn i2c_1(&self) -> I2C_1_R {
+        I2C_1_R::new(((self.bits >> 17) & 0x01) != 0)
+    }
+    #[doc = "Bit 21 - Reset IRQ selector"]
+    #[inline(always)]
+    pub fn irqsel(&self) -> IRQSEL_R {
+        IRQSEL_R::new(((self.bits >> 21) & 0x01) != 0)
+    }
+    #[doc = "Bit 22 - Reset IO Configuration block"]
+    #[inline(always)]
+    pub fn ioconfig(&self) -> IOCONFIG_R {
+        IOCONFIG_R::new(((self.bits >> 22) & 0x01) != 0)
+    }
+    #[doc = "Bit 23 - Reset Utility Block"]
+    #[inline(always)]
+    pub fn utility(&self) -> UTILITY_R {
+        UTILITY_R::new(((self.bits >> 23) & 0x01) != 0)
+    }
+    #[doc = "Bit 24 - Reset GPIO"]
+    #[inline(always)]
+    pub fn gpio(&self) -> GPIO_R {
+        GPIO_R::new(((self.bits >> 24) & 0x01) != 0)
+    }
+}
 impl W {
+    #[doc = "Bit 0 - Reset PORTA"]
+    #[inline(always)]
+    pub fn porta(&mut self) -> PORTA_W {
+        PORTA_W { w: self }
+    }
+    #[doc = "Bit 1 - Reset PORTB"]
+    #[inline(always)]
+    pub fn portb(&mut self) -> PORTB_W {
+        PORTB_W { w: self }
+    }
+    #[doc = "Bit 4 - Reset SPI\\[0\\]"]
+    #[inline(always)]
+    pub fn spi_0(&mut self) -> SPI_0_W {
+        SPI_0_W { w: self }
+    }
+    #[doc = "Bit 5 - Reset SPI\\[1\\]"]
+    #[inline(always)]
+    pub fn spi_1(&mut self) -> SPI_1_W {
+        SPI_1_W { w: self }
+    }
+    #[doc = "Bit 6 - Reset SPI\\[2\\]"]
+    #[inline(always)]
+    pub fn spi_2(&mut self) -> SPI_2_W {
+        SPI_2_W { w: self }
+    }
+    #[doc = "Bit 8 - Reset UART\\[0\\]"]
+    #[inline(always)]
+    pub fn uart_0(&mut self) -> UART_0_W {
+        UART_0_W { w: self }
+    }
+    #[doc = "Bit 9 - Reset UART\\[1\\]"]
+    #[inline(always)]
+    pub fn uart_1(&mut self) -> UART_1_W {
+        UART_1_W { w: self }
+    }
+    #[doc = "Bit 16 - Reset I2C\\[0\\]"]
+    #[inline(always)]
+    pub fn i2c_0(&mut self) -> I2C_0_W {
+        I2C_0_W { w: self }
+    }
+    #[doc = "Bit 17 - Reset I2C\\[1\\]"]
+    #[inline(always)]
+    pub fn i2c_1(&mut self) -> I2C_1_W {
+        I2C_1_W { w: self }
+    }
+    #[doc = "Bit 21 - Reset IRQ selector"]
+    #[inline(always)]
+    pub fn irqsel(&mut self) -> IRQSEL_W {
+        IRQSEL_W { w: self }
+    }
+    #[doc = "Bit 22 - Reset IO Configuration block"]
+    #[inline(always)]
+    pub fn ioconfig(&mut self) -> IOCONFIG_W {
+        IOCONFIG_W { w: self }
+    }
+    #[doc = "Bit 23 - Reset Utility Block"]
+    #[inline(always)]
+    pub fn utility(&mut self) -> UTILITY_W {
+        UTILITY_W { w: self }
+    }
+    #[doc = "Bit 24 - Reset GPIO"]
+    #[inline(always)]
+    pub fn gpio(&mut self) -> GPIO_W {
+        GPIO_W { w: self }
+    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
--- a/src/sysconfig/ram_scrub.rs
+++ b/src/sysconfig/ram_scrub.rs
@ -57,7 +57,7 @@ impl<'a> VALUE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
        self.w
    }
 }
@ -87,7 +87,7 @@ impl R {
    #[doc = "Bits 0:23 - Counter divide value"]
    #[inline(always)]
    pub fn value(&self) -> VALUE_R {
-        VALUE_R::new(self.bits as u32)
+        VALUE_R::new((self.bits & 0x00ff_ffff) as u32)
    }
 }
 impl W {
--- a/src/sysconfig/ram_trap_synd.rs
+++ b/src/sysconfig/ram_trap_synd.rs
@ -57,7 +57,7 @@ impl<'a> SYND_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x000f_ffff) | (value as u32 & 0x000f_ffff);
        self.w
    }
 }
@ -65,7 +65,7 @@ impl R {
    #[doc = "Bits 0:19 - Trap Syndrom Bits"]
    #[inline(always)]
    pub fn synd(&self) -> SYND_R {
-        SYND_R::new(self.bits as u32)
+        SYND_R::new((self.bits & 0x000f_ffff) as u32)
    }
 }
 impl W {
--- a/src/sysconfig/rom_prot.rs
+++ b/src/sysconfig/rom_prot.rs
@ -67,7 +67,7 @@ impl<'a> WREN_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -75,7 +75,7 @@ impl R {
    #[doc = "Bit 0 - ROM Write Enable Bit"]
    #[inline(always)]
    pub fn wren(&self) -> WREN_R {
-        WREN_R::new(self.bits != 0)
+        WREN_R::new((self.bits & 0x01) != 0)
    }
 }
 impl W {
--- a/src/sysconfig/rom_scrub.rs
+++ b/src/sysconfig/rom_scrub.rs
@ -57,7 +57,7 @@ impl<'a> VALUE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x00ff_ffff) | (value as u32 & 0x00ff_ffff);
        self.w
    }
 }
@ -87,7 +87,7 @@ impl R {
    #[doc = "Bits 0:23 - Counter divide value"]
    #[inline(always)]
    pub fn value(&self) -> VALUE_R {
-        VALUE_R::new(self.bits as u32)
+        VALUE_R::new((self.bits & 0x00ff_ffff) as u32)
    }
 }
 impl W {
--- a/src/sysconfig/rom_trap_synd.rs
+++ b/src/sysconfig/rom_trap_synd.rs
@ -57,7 +57,7 @@ impl<'a> SYND_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u32) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x000f_ffff) | (value as u32 & 0x000f_ffff);
        self.w
    }
 }
@ -65,7 +65,7 @@ impl R {
    #[doc = "Bits 0:19 - Trap Syndrom Bits"]
    #[inline(always)]
    pub fn synd(&self) -> SYND_R {
-        SYND_R::new(self.bits as u32)
+        SYND_R::new((self.bits & 0x000f_ffff) as u32)
    }
 }
 impl W {
--- a/src/sysconfig/rst_cntl_ram.rs
+++ b/src/sysconfig/rst_cntl_ram.rs
@ -67,7 +67,7 @@ impl<'a> POR_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -260,7 +260,7 @@ impl R {
    #[doc = "Bit 0 - Power On Reset Status"]
    #[inline(always)]
    pub fn por(&self) -> POR_R {
-        POR_R::new(self.bits != 0)
+        POR_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - External Reset Status"]
    #[inline(always)]
--- a/src/sysconfig/rst_cntl_rom.rs
+++ b/src/sysconfig/rst_cntl_rom.rs
@ -67,7 +67,7 @@ impl<'a> POR_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -260,7 +260,7 @@ impl R {
    #[doc = "Bit 0 - Power On Reset Status"]
    #[inline(always)]
    pub fn por(&self) -> POR_R {
-        POR_R::new(self.bits != 0)
+        POR_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - External Reset Status"]
    #[inline(always)]
--- a/src/sysconfig/rst_stat.rs
+++ b/src/sysconfig/rst_stat.rs
@ -67,7 +67,7 @@ impl<'a> POR_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -260,7 +260,7 @@ impl R {
    #[doc = "Bit 0 - Power On Reset Status"]
    #[inline(always)]
    pub fn por(&self) -> POR_R {
-        POR_R::new(self.bits != 0)
+        POR_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - External Reset Status"]
    #[inline(always)]
--- a/src/tim0/cascade0.rs
+++ b/src/tim0/cascade0.rs
@ -57,7 +57,7 @@ impl<'a> CASSEL_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
        self.w
    }
 }
@ -65,7 +65,7 @@ impl R {
    #[doc = "Bits 0:7 - Cascade Selection"]
    #[inline(always)]
    pub fn cassel(&self) -> CASSEL_R {
-        CASSEL_R::new(self.bits as u8)
+        CASSEL_R::new((self.bits & 0xff) as u8)
    }
 }
 impl W {
--- a/src/tim0/cascade1.rs
+++ b/src/tim0/cascade1.rs
@ -57,7 +57,7 @@ impl<'a> CASSEL_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
        self.w
    }
 }
@ -65,7 +65,7 @@ impl R {
    #[doc = "Bits 0:7 - Cascade Selection"]
    #[inline(always)]
    pub fn cassel(&self) -> CASSEL_R {
-        CASSEL_R::new(self.bits as u8)
+        CASSEL_R::new((self.bits & 0xff) as u8)
    }
 }
 impl W {
--- a/src/tim0/cascade2.rs
+++ b/src/tim0/cascade2.rs
@ -57,7 +57,7 @@ impl<'a> CASSEL_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0xff) | (value as u32 & 0xff);
        self.w
    }
 }
@ -65,7 +65,7 @@ impl R {
    #[doc = "Bits 0:7 - Cascade Selection"]
    #[inline(always)]
    pub fn cassel(&self) -> CASSEL_R {
-        CASSEL_R::new(self.bits as u8)
+        CASSEL_R::new((self.bits & 0xff) as u8)
    }
 }
 impl W {
--- a/src/tim0/csd_ctrl.rs
+++ b/src/tim0/csd_ctrl.rs
@ -67,7 +67,7 @@ impl<'a> CSDEN0_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -404,11 +404,48 @@ impl<'a> CSDXXX2_W<'a> {
        self.w
    }
 }
+#[doc = "Field `CSDTRG2` reader - Cascade 2 Enabled as Trigger"]
+pub struct CSDTRG2_R(crate::FieldReader<bool, bool>);
+impl CSDTRG2_R {
+    #[inline(always)]
+    pub(crate) fn new(bits: bool) -> Self {
+        CSDTRG2_R(crate::FieldReader::new(bits))
+    }
+}
+impl core::ops::Deref for CSDTRG2_R {
+    type Target = crate::FieldReader<bool, bool>;
+    #[inline(always)]
+    fn deref(&self) -> &Self::Target {
+        &self.0
+    }
+}
+#[doc = "Field `CSDTRG2` writer - Cascade 2 Enabled as Trigger"]
+pub struct CSDTRG2_W<'a> {
+    w: &'a mut W,
+}
+impl<'a> CSDTRG2_W<'a> {
+    #[doc = r"Sets the field bit"]
+    #[inline(always)]
+    pub fn set_bit(self) -> &'a mut W {
+        self.bit(true)
+    }
+    #[doc = r"Clears the field bit"]
+    #[inline(always)]
+    pub fn clear_bit(self) -> &'a mut W {
+        self.bit(false)
+    }
+    #[doc = r"Writes raw bits to the field"]
+    #[inline(always)]
+    pub fn bit(self, value: bool) -> &'a mut W {
+        self.w.bits = (self.w.bits & !(0x01 << 10)) | ((value as u32 & 0x01) << 10);
+        self.w
+    }
+}
 impl R {
    #[doc = "Bit 0 - Cascade 0 Enable"]
    #[inline(always)]
    pub fn csden0(&self) -> CSDEN0_R {
-        CSDEN0_R::new(self.bits != 0)
+        CSDEN0_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Cascade 0 Invert"]
    #[inline(always)]
@ -455,6 +492,11 @@ impl R {
    pub fn csdxxx2(&self) -> CSDXXX2_R {
        CSDXXX2_R::new(((self.bits >> 11) & 0x01) != 0)
    }
+    #[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
+    #[inline(always)]
+    pub fn csdtrg2(&self) -> CSDTRG2_R {
+        CSDTRG2_R::new(((self.bits >> 10) & 0x01) != 0)
+    }
 }
 impl W {
    #[doc = "Bit 0 - Cascade 0 Enable"]
@ -507,6 +549,11 @@ impl W {
    pub fn csdxxx2(&mut self) -> CSDXXX2_W {
        CSDXXX2_W { w: self }
    }
+    #[doc = "Bit 10 - Cascade 2 Enabled as Trigger"]
+    #[inline(always)]
+    pub fn csdtrg2(&mut self) -> CSDTRG2_W {
+        CSDTRG2_W { w: self }
+    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
--- a/src/tim0/ctrl.rs
+++ b/src/tim0/ctrl.rs
@ -67,7 +67,7 @@ impl<'a> ENABLE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -416,7 +416,7 @@ impl R {
    #[doc = "Bit 0 - Counter Enable"]
    #[inline(always)]
    pub fn enable(&self) -> ENABLE_R {
-        ENABLE_R::new(self.bits != 0)
+        ENABLE_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Counter Active"]
    #[inline(always)]
--- a/src/tim0/enable.rs
+++ b/src/tim0/enable.rs
@ -67,7 +67,7 @@ impl<'a> ENABLE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -75,7 +75,7 @@ impl R {
    #[doc = "Bit 0 - Counter Enable"]
    #[inline(always)]
    pub fn enable(&self) -> ENABLE_R {
-        ENABLE_R::new(self.bits != 0)
+        ENABLE_R::new((self.bits & 0x01) != 0)
    }
 }
 impl W {
--- a/src/uarta/clkscale.rs
+++ b/src/uarta/clkscale.rs
@ -57,7 +57,7 @@ impl<'a> FRAC_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub unsafe fn bits(self, value: u8) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x3f) | (value as u32 & 0x3f);
        self.w
    }
 }
@ -114,7 +114,7 @@ impl R {
    #[doc = "Bits 0:5 - Fractional Divide (64ths)"]
    #[inline(always)]
    pub fn frac(&self) -> FRAC_R {
-        FRAC_R::new(self.bits as u8)
+        FRAC_R::new((self.bits & 0x3f) as u8)
    }
    #[doc = "Bits 6:23 - Integer Divide"]
    #[inline(always)]
--- a/src/uarta/ctrl.rs
+++ b/src/uarta/ctrl.rs
@ -67,7 +67,7 @@ impl<'a> PAREN_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -435,7 +435,7 @@ impl R {
    #[doc = "Bit 0 - Parity Enable"]
    #[inline(always)]
    pub fn paren(&self) -> PAREN_R {
-        PAREN_R::new(self.bits != 0)
+        PAREN_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Parity Even/Odd(1/0)"]
    #[inline(always)]
--- a/src/uarta/enable.rs
+++ b/src/uarta/enable.rs
@ -67,7 +67,7 @@ impl<'a> RXENABLE_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -112,7 +112,7 @@ impl R {
    #[doc = "Bit 0 - Rx Enable"]
    #[inline(always)]
    pub fn rxenable(&self) -> RXENABLE_R {
-        RXENABLE_R::new(self.bits != 0)
+        RXENABLE_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Tx Enable"]
    #[inline(always)]
--- a/src/uarta/fifo_clr.rs
+++ b/src/uarta/fifo_clr.rs
@ -37,7 +37,7 @@ impl<'a> RXSTS_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
--- a/src/uarta/irq_clr.rs
+++ b/src/uarta/irq_clr.rs
@ -37,7 +37,7 @@ impl<'a> IRQ_RX_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
--- a/src/uarta/irq_enb.rs
+++ b/src/uarta/irq_enb.rs
@ -67,7 +67,7 @@ impl<'a> IRQ_RX_W<'a> {
    #[doc = r"Writes raw bits to the field"]
    #[inline(always)]
    pub fn bit(self, value: bool) -> &'a mut W {
-        self.w.bits = value as u32;
+        self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
        self.w
    }
 }
@ -297,7 +297,7 @@ impl R {
    #[doc = "Bit 0 - RX Interrupt"]
    #[inline(always)]
    pub fn irq_rx(&self) -> IRQ_RX_R {
-        IRQ_RX_R::new(self.bits != 0)
+        IRQ_RX_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - RX Status Interrupt"]
    #[inline(always)]
--- a/src/uarta/irq_end.rs
+++ b/src/uarta/irq_end.rs
@ -122,7 +122,7 @@ impl R {
    #[doc = "Bit 0 - RX Interrupt"]
    #[inline(always)]
    pub fn irq_rx(&self) -> IRQ_RX_R {
-        IRQ_RX_R::new(self.bits != 0)
+        IRQ_RX_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - RX Status Interrupt"]
    #[inline(always)]
--- a/src/uarta/irq_raw.rs
+++ b/src/uarta/irq_raw.rs
@ -122,7 +122,7 @@ impl R {
    #[doc = "Bit 0 - RX Interrupt"]
    #[inline(always)]
    pub fn irq_rx(&self) -> IRQ_RX_R {
-        IRQ_RX_R::new(self.bits != 0)
+        IRQ_RX_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - RX Status Interrupt"]
    #[inline(always)]
--- a/src/uarta/rxstatus.rs
+++ b/src/uarta/rxstatus.rs
@ -182,7 +182,7 @@ impl R {
    #[doc = "Bit 0 - Read Data Available"]
    #[inline(always)]
    pub fn rdavl(&self) -> RDAVL_R {
-        RDAVL_R::new(self.bits != 0)
+        RDAVL_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Read Fifo NOT Full"]
    #[inline(always)]
--- a/src/uarta/txstatus.rs
+++ b/src/uarta/txstatus.rs
@ -92,7 +92,7 @@ impl R {
    #[doc = "Bit 0 - Write Fifo NOT Full"]
    #[inline(always)]
    pub fn wrrdy(&self) -> WRRDY_R {
-        WRRDY_R::new(self.bits != 0)
+        WRRDY_R::new((self.bits & 0x01) != 0)
    }
    #[doc = "Bit 1 - Write Fifo Full"]
    #[inline(always)]
--- a/svd/va108xx-base.svd
+++ b/svd/va108xx-base.svd
--- a/svd/va108xx-base.svd.patched
+++ b/svd/va108xx-base.svd.patched
--- a/svd/va108xx-orig.svd
+++ b/svd/va108xx-orig.svd
--- a/svd/va108xx-patch.yml
+++ b/svd/va108xx-patch.yml
@ -0,0 +1,137 @@
+_svd: va108xx-base.svd
+
+SYSCONFIG:
+  PERIPHERAL_CLK_ENABLE:
+    _add:
+        PORTA:
+          description: Enable PORTA clock
+          bitOffset: 0
+          bitWidth: 1
+        PORTB:
+          description: Enable PORTB clock
+          bitOffset: 1
+          bitWidth: 1
+        SPI_0:
+          description: Enable SPI[0] clock
+          bitOffset: 4
+          bitWidth: 1
+        SPI_1:
+          description: Enable SPI[1] clock
+          bitOffset: 5
+          bitWidth: 1
+        SPI_2:
+          description: Enable SPI[2] clock
+          bitOffset: 6
+          bitWidth: 1
+        UART_0:
+          description: Enable UART[0] clock
+          bitOffset: 8
+          bitWidth: 1
+        UART_1:
+          description: Enable UART[1] clock
+          bitOffset: 9
+          bitWidth: 1
+        I2C_0:
+          description: Enable I2C[0] clock
+          bitOffset: 16
+          bitWidth: 1
+        I2C_1:
+          description: Enable I2C[1] clock
+          bitOffset: 17
+          bitWidth: 1
+        IRQSEL:
+          description: Enable IRQ selector clock
+          bitOffset: 21
+          bitWidth: 1
+        IOCONFIG:
+          description: Enable IO Configuration block clock
+          bitOffset: 22
+          bitWidth: 1
+        UTILITY:
+          description: Enable utility clock
+          bitOffset: 23
+          bitWidth: 1
+        GPIO:
+          description: Enable GPIO clock
+          bitOffset: 24
+          bitWidth: 1
+
+  PERIPHERAL_RESET:
+    _add:
+      PORTA:
+        description: Reset PORTA
+        bitOffset: 0
+        bitWidth: 1
+      PORTB:
+        description: Reset PORTB
+        bitOffset: 1
+        bitWidth: 1
+      SPI_0:
+        description: Reset SPI[0]
+        bitOffset: 4
+        bitWidth: 1
+      SPI_1:
+        description: Reset SPI[1]
+        bitOffset: 5
+        bitWidth: 1
+      SPI_2:
+        description: Reset SPI[2]
+        bitOffset: 6
+        bitWidth: 1
+      UART_0:
+        description: Reset UART[0]
+        bitOffset: 8
+        bitWidth: 1
+      UART_1:
+        description: Reset UART[1]
+        bitOffset: 9
+        bitWidth: 1
+      I2C_0:
+        description: Reset I2C[0]
+        bitOffset: 16
+        bitWidth: 1
+      I2C_1:
+        description: Reset I2C[1]
+        bitOffset: 17
+        bitWidth: 1
+      IRQSEL:
+        description: Reset IRQ selector
+        bitOffset: 21
+        bitWidth: 1
+      IOCONFIG:
+        description: Reset IO Configuration block
+        bitOffset: 22
+        bitWidth: 1
+      UTILITY:
+        description: Reset Utility Block
+        bitOffset: 23
+        bitWidth: 1
+      GPIO:
+        description: Reset GPIO
+        bitOffset: 24
+        bitWidth: 1
+
+# I2CB is derived from I2CA
+I2CA:
+  _modify:
+    STATUS:
+      access: read-only
+  STATUS:
+    _add:
+      I2C_IDLE:
+        description: I2C bus is Idle
+        bitOffset: 0
+        bitWidth: 1
+      IDLE:
+        description: Controller is Idle
+        bitOffset: 1
+        bitWidth: 1
+
+# All TIMs are derived from TIM0
+TIM0:
+  CSD_CTRL:
+    _add:
+      CSDTRG2:
+        description: Cascade 2 Enabled as Trigger
+        bitOffset: 10
+        bitWidth: 1
Author	SHA1	Message	Date
Robin Müller	f626e33e72	simplify CI	2021-12-13 00:11:40 +01:00
Robin Müller	4da8267c9c	update HAL link	2021-12-06 15:55:59 +01:00
Robin Müller	002b277ae2	only use check instead of build for CI/CD	2021-12-06 13:10:13 +01:00
Robin Müller	6a8c58bfce	update repo and homepage links in manifest	2021-12-06 12:53:30 +01:00
Robin Müller	a5e5f02f7c	bump version to 0.2.4 Rust/va108xx-rs/pipeline/head This commit looks good Details	2021-12-06 12:24:55 +01:00
Robin Müller	91a2db0f6f	Merge pull request 'added missing cascade field' (#5 ) from mueller/csd2-trg into main Rust/va108xx-rs/pipeline/head This commit looks good Details Reviewed-on: rust/va108xx-rs#5	2021-12-06 12:21:06 +01:00
Robin Müller	cba43bc221	added missing cascade field Rust/va108xx-rs/pipeline/head This commit looks good Details	2021-12-06 00:03:28 +01:00
Robin Müller	ed22f9a76f	update CHANGELOG Rust/va108xx-rs/pipeline/head This commit looks good Details	2021-12-05 21:57:13 +01:00
Robin Müller	c143d8186d	bump revision Rust/va108xx-rs/pipeline/head This commit looks good Details	2021-12-05 21:56:16 +01:00
Robin Müller	ba6c42df52	Merge pull request 'Add peripheral reset fields' (#4 ) from mueller/add-peripheral-reset into main Rust/va108xx-rs/pipeline/head This commit looks good Details Reviewed-on: rust/va108xx-rs#4	2021-12-05 21:55:14 +01:00
Robin Müller	64a023970a	Add peripheral reset fields Rust/va108xx-rs/pipeline/head This commit looks good Details - Also update CHANGELOG	2021-12-05 21:51:08 +01:00
Robin Müller	8c6537181f	cross-reference HAL and BSP Rust/va108xx-rs/pipeline/head This commit looks good Details	2021-12-05 17:42:58 +01:00
Robin Müller	914ec09376	replaced badge Rust/va108xx-rs/pipeline/head This commit looks good Details	2021-12-03 20:39:53 +01:00
Robin Müller	9e8dbb7c6d	hopefully the last small fix Rust/va108xx-rs/pipeline/head This commit looks good Details	2021-12-03 15:07:11 +01:00
Robin Müller	1a707aa861	small README fix	2021-12-03 15:06:49 +01:00
Robin Müller	02725c9aa2	v0.2.1: updated homepage and repostory Rust/va108xx-rs/pipeline/head This commit looks good Details	2021-12-03 15:04:20 +01:00
Robin Müller	b09e82a563	Merge pull request 'v0.2.0: Relicensed as Apache-2.0' (#3 ) from mueller/bump-to-v0.2.0 into main Rust/va108xx-rs/pipeline/head This commit looks good Details Reviewed-on: rust/va108xx-rs#3	2021-12-03 14:41:59 +01:00
Robin Müller	2c86b1420e	v0.2.0: Relicensed and republished Rust/va108xx-rs/pipeline/head This commit looks good Details - Now hosted on EGit	2021-12-03 14:28:37 +01:00
Robin Müller	74a4c44f71	Merge pull request 'NOTICE Draft' (#2 ) from mohr-NOTICE into main Rust/va108xx-rs/pipeline/head This commit looks good Details Reviewed-on: rust/va108xx-rs#2	2021-11-29 09:54:16 +01:00
Ulrich Mohr	b7ba49258c	NOTICE Draft Rust/va108xx-rs/pipeline/head This commit looks good Details	2021-11-26 18:00:10 +01:00
Robin Müller	acadf7cdc9	Merge pull request 'EGit integration' (#1 ) from mueller/egit-integration into main Rust/va108xx-rs/pipeline/head This commit looks good Details Reviewed-on: rust/va108xx-rs#1	2021-11-26 14:56:15 +01:00
Robin Müller	952ec3738b	EGit integration Rust/va108xx-rs/pipeline/head This commit looks good Details - Added automation files for CI/CD - Relicense as Apache 2.0	2021-11-23 10:34:25 +01:00
bors[bot]	e59ba9e860	Merge #12 12: I2C update r=robamu a=robamu - Added two missing bit fields for I2CA STATUS register: I2CIDLE and IDLE - Made STATUS register read-only Co-authored-by: Robin Mueller <robin.mueller.m@gmail.com>	2021-11-23 09:19:29 +00:00
Robin Müller	4c91a36568	I2C update - Added two missing bit fields for I2CA STATUS register: I2CIDLE and IDLE - Made STATUS register read-only	2021-11-23 01:42:22 +01:00
Robin Müller	1c08574e3e	update changelog	2021-11-09 18:49:01 +01:00
Robin Müller	6712a3fcb1	bumping to v0.1.2	2021-11-09 18:22:19 +01:00
Robin Müller	7720a22269	update README	2021-11-09 18:21:22 +01:00
bors[bot]	1f6b1333bc	Merge #11 11: Update to v0.1.1 with important bugfix r=robamu a=robamu This PAC was generated using a patched version of svd2rust with commit hash 43be074d21132c3a76780816010df592a3603874 It includes bugfix rust-embedded/svd2rust#549 Co-authored-by: Robin Mueller <robin.mueller.m@gmail.com>	2021-11-09 17:17:45 +00:00
Robin Müller	25d0ec677a	bumped revision for bugfix	2021-11-09 18:16:08 +01:00
Robin Müller	8c28367a33	Important fix: Use bitmask everywhere now This PAC was generated using a patched version of svd2rust with commit hash 43be074d21132c3a76780816010df592a3603874 It includes bugfix https://github.com/rust-embedded/svd2rust/pull/549	2021-11-09 18:15:08 +01:00
Robin Müller	d37aad6b1c	updated rust edition to 2021	2021-11-09 11:29:28 +01:00
Robin Müller	20ab6733d7	cross-compile now in CI	2021-11-08 23:52:41 +01:00
Robin Müller	d9784284a8	added crates IO badge	2021-11-06 01:37:29 +01:00
bors[bot]	e5ff466af3	Merge #10 10: v0.1.1 release r=robamu a=robamu Release for VA108xx HAL implementation Co-authored-by: Robin Mueller <robin.mueller.m@gmail.com>	2021-11-06 00:33:39 +00:00
Robin Müller	f2cb5d03c1	update CHANGELOG	2021-11-06 01:32:06 +01:00
Robin Müller	943d8aff75	release for HAL	2021-11-06 01:31:07 +01:00
bors[bot]	96df701b5f	Merge #9 9: Added PAC update for new fields r=robamu a=robamu - Adds the PAC changes for the updated SVD file. Peripheral clock enable register now has named fields Co-authored-by: Robin Mueller <robin.mueller.m@gmail.com>	2021-11-04 21:50:21 +00:00
Robin Müller	9d279c8788	Added PAC update for new fields	2021-11-04 22:48:42 +01:00
bors[bot]	07916573ed	Merge #8 8: Added gitignore file r=robamu a=robamu Co-authored-by: Robin Mueller <robin.mueller.m@gmail.com>	2021-11-04 21:45:12 +00:00
bors[bot]	22c561248b	Merge #7 7: Update Cargo.toml r=robamu a=robamu - Added categories and reordered Cargo.toml a bit Co-authored-by: Robin Mueller <robin.mueller.m@gmail.com>	2021-11-04 21:44:05 +00:00
Robin Müller	93a332438e	Merge remote-tracking branch 'origin/main' into mueller/categories	2021-11-04 22:43:02 +01:00
bors[bot]	6308acc0b5	Merge #6 6: Updated SVD file handling and README r=robamu a=robamu SVD base file is now created using the svdtools package and a YAML file. Update README with usage information as well. Adds new fields for the peripheral clock enable register as well Co-authored-by: Robin Mueller <robin.mueller.m@gmail.com>	2021-11-04 21:41:00 +00:00
Robin Müller	0dcc83720d	Updated SVD file handling and README SVD base file is now created using the svdtools package and a YAML file. Update README with usage information as well. This PR also adds new fields for the peripheral clock enable register in the SVD file	2021-11-04 22:39:53 +01:00
Robin Müller	0d65141d2e	Added gitignore file	2021-11-04 22:37:48 +01:00
Robin Müller	bf57ee4817	Update Cargo.toml - Added categories and reordered a bit	2021-11-04 22:36:50 +01:00
bors[bot]	81c21e3894	Merge #5 5: switched license to dual MIT or Apache 2.0 r=robamu a=robamu - Relicensing code under MIT / Apache 2.0 dual license Co-authored-by: Robin Mueller <robin.mueller.m@gmail.com>	2021-11-02 19:47:56 +00:00
Robin Müller	60b8a8ae62	switched license to dual MIT or Apache 2.0	2021-11-02 20:47:04 +01:00
bors[bot]	f1cda700d2	Merge #4 4: added helper script r=robamu a=robamu Script automates all steps to generate the PAC Co-authored-by: Robin Mueller <robin.mueller.m@gmail.com>	2021-11-02 10:01:19 +00:00
Robin Müller	9d6d3e8cc4	Merge remote-tracking branch 'origin/main' into mueller/added-helper-script	2021-11-02 11:00:34 +01:00
Robin Müller	40b36feb63	added helper script Script automates all steps to generate the PAC	2021-11-02 10:59:17 +01:00
bors[bot]	eb473f7c36	Merge #3 3: Added badges r=robamu a=robamu Badges for README Co-authored-by: Robin Mueller <robin.mueller.m@gmail.com>	2021-11-02 09:52:41 +00:00
Robin Müller	4865157c4b	added docs and build badge	2021-11-02 10:46:11 +01:00