138 lines
3.0 KiB
YAML
138 lines
3.0 KiB
YAML
_svd: va108xx-base.svd
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SYSCONFIG:
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PERIPHERAL_CLK_ENABLE:
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_add:
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PORTA:
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description: Enable PORTA clock
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bitOffset: 0
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bitWidth: 1
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PORTB:
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description: Enable PORTB clock
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bitOffset: 1
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bitWidth: 1
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SPI_0:
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description: Enable SPI[0] clock
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bitOffset: 4
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bitWidth: 1
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SPI_1:
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description: Enable SPI[1] clock
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bitOffset: 5
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bitWidth: 1
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SPI_2:
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description: Enable SPI[2] clock
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bitOffset: 6
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bitWidth: 1
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UART_0:
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description: Enable UART[0] clock
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bitOffset: 8
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bitWidth: 1
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UART_1:
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description: Enable UART[1] clock
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bitOffset: 9
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bitWidth: 1
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I2C_0:
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description: Enable I2C[0] clock
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bitOffset: 16
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bitWidth: 1
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I2C_1:
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description: Enable I2C[1] clock
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bitOffset: 17
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bitWidth: 1
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IRQSEL:
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description: Enable IRQ selector clock
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bitOffset: 21
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bitWidth: 1
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IOCONFIG:
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description: Enable IO Configuration block clock
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bitOffset: 22
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bitWidth: 1
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UTILITY:
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description: Enable utility clock
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bitOffset: 23
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bitWidth: 1
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GPIO:
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description: Enable GPIO clock
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bitOffset: 24
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bitWidth: 1
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PERIPHERAL_RESET:
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_add:
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PORTA:
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description: Reset PORTA
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bitOffset: 0
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bitWidth: 1
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PORTB:
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description: Reset PORTB
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bitOffset: 1
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bitWidth: 1
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SPI_0:
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description: Reset SPI[0]
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bitOffset: 4
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bitWidth: 1
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SPI_1:
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description: Reset SPI[1]
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bitOffset: 5
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bitWidth: 1
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SPI_2:
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description: Reset SPI[2]
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bitOffset: 6
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bitWidth: 1
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UART_0:
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description: Reset UART[0]
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bitOffset: 8
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bitWidth: 1
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UART_1:
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description: Reset UART[1]
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bitOffset: 9
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bitWidth: 1
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I2C_0:
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description: Reset I2C[0]
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bitOffset: 16
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bitWidth: 1
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I2C_1:
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description: Reset I2C[1]
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bitOffset: 17
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bitWidth: 1
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IRQSEL:
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description: Reset IRQ selector
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bitOffset: 21
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bitWidth: 1
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IOCONFIG:
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description: Reset IO Configuration block
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bitOffset: 22
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bitWidth: 1
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UTILITY:
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description: Reset Utility Block
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bitOffset: 23
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bitWidth: 1
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GPIO:
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description: Reset GPIO
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bitOffset: 24
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bitWidth: 1
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# I2CB is derived from I2CA
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I2CA:
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_modify:
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STATUS:
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access: read-only
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STATUS:
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_add:
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I2C_IDLE:
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description: I2C bus is Idle
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bitOffset: 0
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bitWidth: 1
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IDLE:
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description: Controller is Idle
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bitOffset: 1
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bitWidth: 1
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# All TIMs are derived from TIM0
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TIM0:
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CSD_CTRL:
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_add:
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CSDTRG2:
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description: Cascade 2 Enabled as Trigger
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bitOffset: 10
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bitWidth: 1
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