Robin Mueller
8c28367a33
This PAC was generated using a patched version of svd2rust with commit hash 43be074d21132c3a76780816010df592a3603874 It includes bugfix https://github.com/rust-embedded/svd2rust/pull/549
154 lines
4.3 KiB
Rust
154 lines
4.3 KiB
Rust
#[doc = "Register `IRQ_CLR` writer"]
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pub struct W(crate::W<IRQ_CLR_SPEC>);
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impl core::ops::Deref for W {
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type Target = crate::W<IRQ_CLR_SPEC>;
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#[inline(always)]
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fn deref(&self) -> &Self::Target {
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&self.0
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}
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}
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impl core::ops::DerefMut for W {
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#[inline(always)]
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fn deref_mut(&mut self) -> &mut Self::Target {
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&mut self.0
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}
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}
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impl From<crate::W<IRQ_CLR_SPEC>> for W {
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#[inline(always)]
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fn from(writer: crate::W<IRQ_CLR_SPEC>) -> Self {
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W(writer)
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}
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}
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#[doc = "Field `RORIM` writer - RX Overrun"]
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pub struct RORIM_W<'a> {
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w: &'a mut W,
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}
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impl<'a> RORIM_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !0x01) | (value as u32 & 0x01);
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self.w
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}
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}
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#[doc = "Field `RTIM` writer - RX Timeout"]
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pub struct RTIM_W<'a> {
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w: &'a mut W,
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}
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impl<'a> RTIM_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 1)) | ((value as u32 & 0x01) << 1);
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self.w
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}
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}
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#[doc = "Field `RXIM` writer - RX Fifo is at least half full"]
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pub struct RXIM_W<'a> {
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w: &'a mut W,
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}
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impl<'a> RXIM_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 2)) | ((value as u32 & 0x01) << 2);
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self.w
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}
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}
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#[doc = "Field `TXIM` writer - TX Fifo is at least half empty"]
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pub struct TXIM_W<'a> {
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w: &'a mut W,
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}
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impl<'a> TXIM_W<'a> {
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#[doc = r"Sets the field bit"]
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#[inline(always)]
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pub fn set_bit(self) -> &'a mut W {
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self.bit(true)
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}
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#[doc = r"Clears the field bit"]
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#[inline(always)]
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pub fn clear_bit(self) -> &'a mut W {
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self.bit(false)
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}
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#[doc = r"Writes raw bits to the field"]
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#[inline(always)]
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pub fn bit(self, value: bool) -> &'a mut W {
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self.w.bits = (self.w.bits & !(0x01 << 3)) | ((value as u32 & 0x01) << 3);
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self.w
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}
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}
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impl W {
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#[doc = "Bit 0 - RX Overrun"]
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#[inline(always)]
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pub fn rorim(&mut self) -> RORIM_W {
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RORIM_W { w: self }
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}
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#[doc = "Bit 1 - RX Timeout"]
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#[inline(always)]
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pub fn rtim(&mut self) -> RTIM_W {
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RTIM_W { w: self }
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}
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#[doc = "Bit 2 - RX Fifo is at least half full"]
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#[inline(always)]
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pub fn rxim(&mut self) -> RXIM_W {
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RXIM_W { w: self }
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}
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#[doc = "Bit 3 - TX Fifo is at least half empty"]
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#[inline(always)]
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pub fn txim(&mut self) -> TXIM_W {
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TXIM_W { w: self }
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}
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#[doc = "Writes raw bits to the register."]
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#[inline(always)]
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pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
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self.0.bits(bits);
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self
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}
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}
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#[doc = "Clear Interrupt Status Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [irq_clr](index.html) module"]
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pub struct IRQ_CLR_SPEC;
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impl crate::RegisterSpec for IRQ_CLR_SPEC {
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type Ux = u32;
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}
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#[doc = "`write(|w| ..)` method takes [irq_clr::W](W) writer structure"]
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impl crate::Writable for IRQ_CLR_SPEC {
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type Writer = W;
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}
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#[doc = "`reset()` method sets IRQ_CLR to value 0"]
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impl crate::Resettable for IRQ_CLR_SPEC {
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#[inline(always)]
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fn reset_value() -> Self::Ux {
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0
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}
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}
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