va108xx/src/spia/ctrl0.rs

235 lines
6.5 KiB
Rust

#[doc = "Register `CTRL0` reader"]
pub struct R(crate::R<CTRL0_SPEC>);
impl core::ops::Deref for R {
type Target = crate::R<CTRL0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl From<crate::R<CTRL0_SPEC>> for R {
#[inline(always)]
fn from(reader: crate::R<CTRL0_SPEC>) -> Self {
R(reader)
}
}
#[doc = "Register `CTRL0` writer"]
pub struct W(crate::W<CTRL0_SPEC>);
impl core::ops::Deref for W {
type Target = crate::W<CTRL0_SPEC>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
impl core::ops::DerefMut for W {
#[inline(always)]
fn deref_mut(&mut self) -> &mut Self::Target {
&mut self.0
}
}
impl From<crate::W<CTRL0_SPEC>> for W {
#[inline(always)]
fn from(writer: crate::W<CTRL0_SPEC>) -> Self {
W(writer)
}
}
#[doc = "Field `SIZE` reader - Data Size(0x3=>4, 0xf=>16)"]
pub struct SIZE_R(crate::FieldReader<u8, u8>);
impl SIZE_R {
#[inline(always)]
pub(crate) fn new(bits: u8) -> Self {
SIZE_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for SIZE_R {
type Target = crate::FieldReader<u8, u8>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `SIZE` writer - Data Size(0x3=>4, 0xf=>16)"]
pub struct SIZE_W<'a> {
w: &'a mut W,
}
impl<'a> SIZE_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !0x0f) | (value as u32 & 0x0f);
self.w
}
}
#[doc = "Field `SPO` reader - SPI Clock Polarity"]
pub struct SPO_R(crate::FieldReader<bool, bool>);
impl SPO_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
SPO_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for SPO_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `SPO` writer - SPI Clock Polarity"]
pub struct SPO_W<'a> {
w: &'a mut W,
}
impl<'a> SPO_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | ((value as u32 & 0x01) << 6);
self.w
}
}
#[doc = "Field `SPH` reader - SPI Clock Phase"]
pub struct SPH_R(crate::FieldReader<bool, bool>);
impl SPH_R {
#[inline(always)]
pub(crate) fn new(bits: bool) -> Self {
SPH_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for SPH_R {
type Target = crate::FieldReader<bool, bool>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `SPH` writer - SPI Clock Phase"]
pub struct SPH_W<'a> {
w: &'a mut W,
}
impl<'a> SPH_W<'a> {
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 7)) | ((value as u32 & 0x01) << 7);
self.w
}
}
#[doc = "Field `SCRDV` reader - Serial Clock Rate divide+1 value"]
pub struct SCRDV_R(crate::FieldReader<u8, u8>);
impl SCRDV_R {
#[inline(always)]
pub(crate) fn new(bits: u8) -> Self {
SCRDV_R(crate::FieldReader::new(bits))
}
}
impl core::ops::Deref for SCRDV_R {
type Target = crate::FieldReader<u8, u8>;
#[inline(always)]
fn deref(&self) -> &Self::Target {
&self.0
}
}
#[doc = "Field `SCRDV` writer - Serial Clock Rate divide+1 value"]
pub struct SCRDV_W<'a> {
w: &'a mut W,
}
impl<'a> SCRDV_W<'a> {
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub unsafe fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0xff << 8)) | ((value as u32 & 0xff) << 8);
self.w
}
}
impl R {
#[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
#[inline(always)]
pub fn size(&self) -> SIZE_R {
SIZE_R::new((self.bits & 0x0f) as u8)
}
#[doc = "Bit 6 - SPI Clock Polarity"]
#[inline(always)]
pub fn spo(&self) -> SPO_R {
SPO_R::new(((self.bits >> 6) & 0x01) != 0)
}
#[doc = "Bit 7 - SPI Clock Phase"]
#[inline(always)]
pub fn sph(&self) -> SPH_R {
SPH_R::new(((self.bits >> 7) & 0x01) != 0)
}
#[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
#[inline(always)]
pub fn scrdv(&self) -> SCRDV_R {
SCRDV_R::new(((self.bits >> 8) & 0xff) as u8)
}
}
impl W {
#[doc = "Bits 0:3 - Data Size(0x3=>4, 0xf=>16)"]
#[inline(always)]
pub fn size(&mut self) -> SIZE_W {
SIZE_W { w: self }
}
#[doc = "Bit 6 - SPI Clock Polarity"]
#[inline(always)]
pub fn spo(&mut self) -> SPO_W {
SPO_W { w: self }
}
#[doc = "Bit 7 - SPI Clock Phase"]
#[inline(always)]
pub fn sph(&mut self) -> SPH_W {
SPH_W { w: self }
}
#[doc = "Bits 8:15 - Serial Clock Rate divide+1 value"]
#[inline(always)]
pub fn scrdv(&mut self) -> SCRDV_W {
SCRDV_W { w: self }
}
#[doc = "Writes raw bits to the register."]
#[inline(always)]
pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
self.0.bits(bits);
self
}
}
#[doc = "Control Register 0\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ctrl0](index.html) module"]
pub struct CTRL0_SPEC;
impl crate::RegisterSpec for CTRL0_SPEC {
type Ux = u32;
}
#[doc = "`read()` method returns [ctrl0::R](R) reader structure"]
impl crate::Readable for CTRL0_SPEC {
type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [ctrl0::W](W) writer structure"]
impl crate::Writable for CTRL0_SPEC {
type Writer = W;
}
#[doc = "`reset()` method sets CTRL0 to value 0"]
impl crate::Resettable for CTRL0_SPEC {
#[inline(always)]
fn reset_value() -> Self::Ux {
0
}
}