rust/va416xx-rs
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regenerate PAC, va416xx v0.3.0

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This commit is contained in:
Robin Müller
2025-02-13 15:58:05 +01:00
parent 0c040515fe
commit 2c9ca004ce
517 changed files with 1376 additions and 2392 deletions
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8
va416xx/src/adc/ctrl.rs
View File

@ -61,42 +61,36 @@ impl R {
impl W {
#[doc = "Bits 0:15 - Enables the channel for data collection"]
#[inline(always)]
#[must_use]
pub fn chan_en(&mut self) -> ChanEnW<CtrlSpec> {
ChanEnW::new(self, 0)
}
#[doc = "Bit 16 - Enables the channel tag to be saved with the ADC data"]
#[inline(always)]
#[must_use]
pub fn chan_tag_en(&mut self) -> ChanTagEnW<CtrlSpec> {
ChanTagEnW::new(self, 16)
}
#[doc = "Bit 17 - ADC data acquisition for all enabled channel"]
#[inline(always)]
#[must_use]
pub fn sweep_en(&mut self) -> SweepEnW<CtrlSpec> {
SweepEnW::new(self, 17)
}
#[doc = "Bit 18 - Allows the external trigger to start analog acquisition"]
#[inline(always)]
#[must_use]
pub fn ext_trig_en(&mut self) -> ExtTrigEnW<CtrlSpec> {
ExtTrigEnW::new(self, 18)
}
#[doc = "Bit 19 - Starts analog acquisition"]
#[inline(always)]
#[must_use]
pub fn manual_trig(&mut self) -> ManualTrigW<CtrlSpec> {
ManualTrigW::new(self, 19)
}
#[doc = "Bits 20:23 - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"]
#[inline(always)]
#[must_use]
pub fn conv_cnt(&mut self) -> ConvCntW<CtrlSpec> {
ConvCntW::new(self, 20)
}
}
#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Control Register\n\nYou can [`read`](crate::Reg::read) this register and get [`ctrl::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct CtrlSpec;
impl crate::RegisterSpec for CtrlSpec {
type Ux = u32;

3
va416xx/src/adc/fifo_clr.rs
View File

@ -7,12 +7,11 @@ pub type FifoClrW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Clears the ADC FIFO. Always reads 0"]
#[inline(always)]
#[must_use]
pub fn fifo_clr(&mut self) -> FifoClrW<FifoClrSpec> {
FifoClrW::new(self, 0)
}
}
#[doc = "FIFO Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_clr::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "FIFO Clear\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_clr::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`fifo_clr::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoClrSpec;
impl crate::RegisterSpec for FifoClrSpec {
type Ux = u32;

2
va416xx/src/adc/fifo_data.rs
View File

@ -16,7 +16,7 @@ impl R {
ChanTagR::new(((self.bits >> 12) & 0x0f) as u8)
}
}
#[doc = "FIFO data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "FIFO data\n\nYou can [`read`](crate::Reg::read) this register and get [`fifo_data::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct FifoDataSpec;
impl crate::RegisterSpec for FifoDataSpec {
type Ux = u32;

6
va416xx/src/adc/irq_clr.rs
View File

@ -11,30 +11,26 @@ pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>;
impl W {
#[doc = "Bit 0 - Clears the FIFO overflow interrupt status. Always reads 0"]
#[inline(always)]
#[must_use]
pub fn fifo_oflow(&mut self) -> FifoOflowW<IrqClrSpec> {
FifoOflowW::new(self, 0)
}
#[doc = "Bit 1 - Clears the FIFO underflow interrupt status. Always reads 0"]
#[inline(always)]
#[must_use]
pub fn fifo_uflow(&mut self) -> FifoUflowW<IrqClrSpec> {
FifoUflowW::new(self, 1)
}
#[doc = "Bit 2 - Clears the ADC done interrupt status. Always reads 0"]
#[inline(always)]
#[must_use]
pub fn adc_done(&mut self) -> AdcDoneW<IrqClrSpec> {
AdcDoneW::new(self, 2)
}
#[doc = "Bit 3 - Clears the trigger error interrupt status. Always reads 0"]
#[inline(always)]
#[must_use]
pub fn trig_error(&mut self) -> TrigErrorW<IrqClrSpec> {
TrigErrorW::new(self, 3)
}
}
#[doc = "Clear Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Clear Interrupt\n\nYou can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqClrSpec;
impl crate::RegisterSpec for IrqClrSpec {
type Ux = u32;

9
va416xx/src/adc/irq_enb.rs
View File

@ -70,48 +70,41 @@ impl R {
impl W {
#[doc = "Bit 0 - Enables the interrupt for FIFO empty"]
#[inline(always)]
#[must_use]
pub fn fifo_empty(&mut self) -> FifoEmptyW<IrqEnbSpec> {
FifoEmptyW::new(self, 0)
}
#[doc = "Bit 1 - Enables the interrupt for FIFO full"]
#[inline(always)]
#[must_use]
pub fn fifo_full(&mut self) -> FifoFullW<IrqEnbSpec> {
FifoFullW::new(self, 1)
}
#[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"]
#[inline(always)]
#[must_use]
pub fn fifo_oflow(&mut self) -> FifoOflowW<IrqEnbSpec> {
FifoOflowW::new(self, 2)
}
#[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"]
#[inline(always)]
#[must_use]
pub fn fifo_uflow(&mut self) -> FifoUflowW<IrqEnbSpec> {
FifoUflowW::new(self, 3)
}
#[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"]
#[inline(always)]
#[must_use]
pub fn adc_done(&mut self) -> AdcDoneW<IrqEnbSpec> {
AdcDoneW::new(self, 4)
}
#[doc = "Bit 5 - Enables the interrupt for a trigger error"]
#[inline(always)]
#[must_use]
pub fn trig_error(&mut self) -> TrigErrorW<IrqEnbSpec> {
TrigErrorW::new(self, 5)
}
#[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
#[inline(always)]
#[must_use]
pub fn fifo_depth_trig(&mut self) -> FifoDepthTrigW<IrqEnbSpec> {
FifoDepthTrigW::new(self, 6)
}
}
#[doc = "Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEnbSpec;
impl crate::RegisterSpec for IrqEnbSpec {
type Ux = u32;

2
va416xx/src/adc/irq_end.rs
View File

@ -51,7 +51,7 @@ impl R {
FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0)
}
}
#[doc = "Enabled Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Enabled Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_end::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqEndSpec;
impl crate::RegisterSpec for IrqEndSpec {
type Ux = u32;

2
va416xx/src/adc/irq_raw.rs
View File

@ -51,7 +51,7 @@ impl R {
FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0)
}
}
#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_raw::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct IrqRawSpec;
impl crate::RegisterSpec for IrqRawSpec {
type Ux = u32;

2
va416xx/src/adc/perid.rs
View File

@ -5,7 +5,7 @@ impl core::fmt::Debug for R {
write!(f, "{}", self.bits())
}
}
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct PeridSpec;
impl crate::RegisterSpec for PeridSpec {
type Ux = u32;

3
va416xx/src/adc/rxfifoirqtrg.rs
View File

@ -16,12 +16,11 @@ impl R {
impl W {
#[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"]
#[inline(always)]
#[must_use]
pub fn level(&mut self) -> LevelW<RxfifoirqtrgSpec> {
LevelW::new(self, 0)
}
}
#[doc = "Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::Reg::read) this register and get [`rxfifoirqtrg::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct RxfifoirqtrgSpec;
impl crate::RegisterSpec for RxfifoirqtrgSpec {
type Ux = u32;

2
va416xx/src/adc/status.rs
View File

@ -16,7 +16,7 @@ impl R {
AdcBusyR::new(((self.bits >> 7) & 1) != 0)
}
}
#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
#[doc = "Status\n\nYou can [`read`](crate::Reg::read) this register and get [`status::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
pub struct StatusSpec;
impl crate::RegisterSpec for StatusSpec {
type Ux = u32;