124 lines
5.6 KiB
Rust
124 lines
5.6 KiB
Rust
#[doc = "Register `IRQ_ENB` reader"]
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pub type R = crate::R<IrqEnbSpec>;
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#[doc = "Register `IRQ_ENB` writer"]
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pub type W = crate::W<IrqEnbSpec>;
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#[doc = "Field `FIFO_EMPTY` reader - Enables the interrupt for FIFO empty"]
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pub type FifoEmptyR = crate::BitReader;
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#[doc = "Field `FIFO_EMPTY` writer - Enables the interrupt for FIFO empty"]
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pub type FifoEmptyW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `FIFO_FULL` reader - Enables the interrupt for FIFO full"]
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pub type FifoFullR = crate::BitReader;
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#[doc = "Field `FIFO_FULL` writer - Enables the interrupt for FIFO full"]
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pub type FifoFullW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `FIFO_OFLOW` reader - Enables the interrupt for a FIFO overflow"]
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pub type FifoOflowR = crate::BitReader;
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#[doc = "Field `FIFO_OFLOW` writer - Enables the interrupt for a FIFO overflow"]
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pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `FIFO_UFLOW` reader - Enables the interrupt for a FIFO underflow"]
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pub type FifoUflowR = crate::BitReader;
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#[doc = "Field `FIFO_UFLOW` writer - Enables the interrupt for a FIFO underflow"]
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pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `ADC_DONE` reader - Enables the interrupt for an ADC data acquisition completion"]
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pub type AdcDoneR = crate::BitReader;
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#[doc = "Field `ADC_DONE` writer - Enables the interrupt for an ADC data acquisition completion"]
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pub type AdcDoneW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `TRIG_ERROR` reader - Enables the interrupt for a trigger error"]
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pub type TrigErrorR = crate::BitReader;
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#[doc = "Field `TRIG_ERROR` writer - Enables the interrupt for a trigger error"]
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pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>;
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#[doc = "Field `FIFO_DEPTH_TRIG` reader - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
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pub type FifoDepthTrigR = crate::BitReader;
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#[doc = "Field `FIFO_DEPTH_TRIG` writer - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
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pub type FifoDepthTrigW<'a, REG> = crate::BitWriter<'a, REG>;
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impl R {
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#[doc = "Bit 0 - Enables the interrupt for FIFO empty"]
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#[inline(always)]
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pub fn fifo_empty(&self) -> FifoEmptyR {
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FifoEmptyR::new((self.bits & 1) != 0)
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}
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#[doc = "Bit 1 - Enables the interrupt for FIFO full"]
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#[inline(always)]
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pub fn fifo_full(&self) -> FifoFullR {
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FifoFullR::new(((self.bits >> 1) & 1) != 0)
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}
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#[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"]
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#[inline(always)]
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pub fn fifo_oflow(&self) -> FifoOflowR {
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FifoOflowR::new(((self.bits >> 2) & 1) != 0)
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}
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#[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"]
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#[inline(always)]
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pub fn fifo_uflow(&self) -> FifoUflowR {
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FifoUflowR::new(((self.bits >> 3) & 1) != 0)
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}
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#[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"]
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#[inline(always)]
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pub fn adc_done(&self) -> AdcDoneR {
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AdcDoneR::new(((self.bits >> 4) & 1) != 0)
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}
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#[doc = "Bit 5 - Enables the interrupt for a trigger error"]
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#[inline(always)]
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pub fn trig_error(&self) -> TrigErrorR {
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TrigErrorR::new(((self.bits >> 5) & 1) != 0)
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}
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#[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
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#[inline(always)]
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pub fn fifo_depth_trig(&self) -> FifoDepthTrigR {
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FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0)
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}
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}
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impl W {
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#[doc = "Bit 0 - Enables the interrupt for FIFO empty"]
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#[inline(always)]
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pub fn fifo_empty(&mut self) -> FifoEmptyW<IrqEnbSpec> {
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FifoEmptyW::new(self, 0)
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}
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#[doc = "Bit 1 - Enables the interrupt for FIFO full"]
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#[inline(always)]
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pub fn fifo_full(&mut self) -> FifoFullW<IrqEnbSpec> {
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FifoFullW::new(self, 1)
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}
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#[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"]
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#[inline(always)]
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pub fn fifo_oflow(&mut self) -> FifoOflowW<IrqEnbSpec> {
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FifoOflowW::new(self, 2)
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}
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#[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"]
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#[inline(always)]
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pub fn fifo_uflow(&mut self) -> FifoUflowW<IrqEnbSpec> {
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FifoUflowW::new(self, 3)
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}
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#[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"]
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#[inline(always)]
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pub fn adc_done(&mut self) -> AdcDoneW<IrqEnbSpec> {
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AdcDoneW::new(self, 4)
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}
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#[doc = "Bit 5 - Enables the interrupt for a trigger error"]
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#[inline(always)]
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pub fn trig_error(&mut self) -> TrigErrorW<IrqEnbSpec> {
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TrigErrorW::new(self, 5)
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}
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#[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
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#[inline(always)]
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pub fn fifo_depth_trig(&mut self) -> FifoDepthTrigW<IrqEnbSpec> {
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FifoDepthTrigW::new(self, 6)
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}
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}
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#[doc = "Interrupt Enable\n\nYou can [`read`](crate::Reg::read) this register and get [`irq_enb::R`](R). You can [`reset`](crate::Reg::reset), [`write`](crate::Reg::write), [`write_with_zero`](crate::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct IrqEnbSpec;
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impl crate::RegisterSpec for IrqEnbSpec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"]
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impl crate::Readable for IrqEnbSpec {}
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#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
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impl crate::Writable for IrqEnbSpec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets IRQ_ENB to value 0"]
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impl crate::Resettable for IrqEnbSpec {
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const RESET_VALUE: u32 = 0;
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}
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