Init Commit

Monorepo for Rust support of VA416XX family of radiation hardened MCUs

va416xx/src/adc/ctrl.rs

@@ -0,0 +1,115 @@
+#[doc = "Register `CTRL` reader"]
+pub type R = crate::R<CtrlSpec>;
+#[doc = "Register `CTRL` writer"]
+pub type W = crate::W<CtrlSpec>;
+#[doc = "Field `CHAN_EN` reader - Enables the channel for data collection"]
+pub type ChanEnR = crate::FieldReader<u16>;
+#[doc = "Field `CHAN_EN` writer - Enables the channel for data collection"]
+pub type ChanEnW<'a, REG> = crate::FieldWriter<'a, REG, 16, u16>;
+#[doc = "Field `CHAN_TAG_EN` reader - Enables the channel tag to be saved with the ADC data"]
+pub type ChanTagEnR = crate::BitReader;
+#[doc = "Field `CHAN_TAG_EN` writer - Enables the channel tag to be saved with the ADC data"]
+pub type ChanTagEnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `SWEEP_EN` reader - ADC data acquisition for all enabled channel"]
+pub type SweepEnR = crate::BitReader;
+#[doc = "Field `SWEEP_EN` writer - ADC data acquisition for all enabled channel"]
+pub type SweepEnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `EXT_TRIG_EN` reader - Allows the external trigger to start analog acquisition"]
+pub type ExtTrigEnR = crate::BitReader;
+#[doc = "Field `EXT_TRIG_EN` writer - Allows the external trigger to start analog acquisition"]
+pub type ExtTrigEnW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `MANUAL_TRIG` reader - Starts analog acquisition"]
+pub type ManualTrigR = crate::BitReader;
+#[doc = "Field `MANUAL_TRIG` writer - Starts analog acquisition"]
+pub type ManualTrigW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CONV_CNT` reader - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"]
+pub type ConvCntR = crate::FieldReader;
+#[doc = "Field `CONV_CNT` writer - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"]
+pub type ConvCntW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:15 - Enables the channel for data collection"]
+    #[inline(always)]
+    pub fn chan_en(&self) -> ChanEnR {
+        ChanEnR::new((self.bits & 0xffff) as u16)
+    }
+    #[doc = "Bit 16 - Enables the channel tag to be saved with the ADC data"]
+    #[inline(always)]
+    pub fn chan_tag_en(&self) -> ChanTagEnR {
+        ChanTagEnR::new(((self.bits >> 16) & 1) != 0)
+    }
+    #[doc = "Bit 17 - ADC data acquisition for all enabled channel"]
+    #[inline(always)]
+    pub fn sweep_en(&self) -> SweepEnR {
+        SweepEnR::new(((self.bits >> 17) & 1) != 0)
+    }
+    #[doc = "Bit 18 - Allows the external trigger to start analog acquisition"]
+    #[inline(always)]
+    pub fn ext_trig_en(&self) -> ExtTrigEnR {
+        ExtTrigEnR::new(((self.bits >> 18) & 1) != 0)
+    }
+    #[doc = "Bit 19 - Starts analog acquisition"]
+    #[inline(always)]
+    pub fn manual_trig(&self) -> ManualTrigR {
+        ManualTrigR::new(((self.bits >> 19) & 1) != 0)
+    }
+    #[doc = "Bits 20:23 - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"]
+    #[inline(always)]
+    pub fn conv_cnt(&self) -> ConvCntR {
+        ConvCntR::new(((self.bits >> 20) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:15 - Enables the channel for data collection"]
+    #[inline(always)]
+    #[must_use]
+    pub fn chan_en(&mut self) -> ChanEnW<CtrlSpec> {
+        ChanEnW::new(self, 0)
+    }
+    #[doc = "Bit 16 - Enables the channel tag to be saved with the ADC data"]
+    #[inline(always)]
+    #[must_use]
+    pub fn chan_tag_en(&mut self) -> ChanTagEnW<CtrlSpec> {
+        ChanTagEnW::new(self, 16)
+    }
+    #[doc = "Bit 17 - ADC data acquisition for all enabled channel"]
+    #[inline(always)]
+    #[must_use]
+    pub fn sweep_en(&mut self) -> SweepEnW<CtrlSpec> {
+        SweepEnW::new(self, 17)
+    }
+    #[doc = "Bit 18 - Allows the external trigger to start analog acquisition"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ext_trig_en(&mut self) -> ExtTrigEnW<CtrlSpec> {
+        ExtTrigEnW::new(self, 18)
+    }
+    #[doc = "Bit 19 - Starts analog acquisition"]
+    #[inline(always)]
+    #[must_use]
+    pub fn manual_trig(&mut self) -> ManualTrigW<CtrlSpec> {
+        ManualTrigW::new(self, 19)
+    }
+    #[doc = "Bits 20:23 - Conversion count describes the number of conversions to be applied for triggers/sweeps. (N+1 conversions)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn conv_cnt(&mut self) -> ConvCntW<CtrlSpec> {
+        ConvCntW::new(self, 20)
+    }
+}
+#[doc = "Control Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CtrlSpec;
+impl crate::RegisterSpec for CtrlSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl::R`](R) reader structure"]
+impl crate::Readable for CtrlSpec {}
+#[doc = "`write(|w| ..)` method takes [`ctrl::W`](W) writer structure"]
+impl crate::Writable for CtrlSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL to value 0"]
+impl crate::Resettable for CtrlSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/adc/fifo_clr.rs

@@ -0,0 +1,31 @@
+#[doc = "Register `FIFO_CLR` reader"]
+pub type R = crate::R<FifoClrSpec>;
+#[doc = "Register `FIFO_CLR` writer"]
+pub type W = crate::W<FifoClrSpec>;
+#[doc = "Field `FIFO_CLR` writer - Clears the ADC FIFO. Always reads 0"]
+pub type FifoClrW<'a, REG> = crate::BitWriter<'a, REG>;
+impl W {
+    #[doc = "Bit 0 - Clears the ADC FIFO. Always reads 0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_clr(&mut self) -> FifoClrW<FifoClrSpec> {
+        FifoClrW::new(self, 0)
+    }
+}
+#[doc = "FIFO Clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`fifo_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct FifoClrSpec;
+impl crate::RegisterSpec for FifoClrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`fifo_clr::R`](R) reader structure"]
+impl crate::Readable for FifoClrSpec {}
+#[doc = "`write(|w| ..)` method takes [`fifo_clr::W`](W) writer structure"]
+impl crate::Writable for FifoClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets FIFO_CLR to value 0"]
+impl crate::Resettable for FifoClrSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/adc/fifo_data.rs

@@ -0,0 +1,29 @@
+#[doc = "Register `FIFO_DATA` reader"]
+pub type R = crate::R<FifoDataSpec>;
+#[doc = "Field `ADC_DATA` reader - ADC acquisition data from the FIFO"]
+pub type AdcDataR = crate::FieldReader<u16>;
+#[doc = "Field `CHAN_TAG` reader - If enabled, this will include the number of the channel corresponding to the measurement"]
+pub type ChanTagR = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:11 - ADC acquisition data from the FIFO"]
+    #[inline(always)]
+    pub fn adc_data(&self) -> AdcDataR {
+        AdcDataR::new((self.bits & 0x0fff) as u16)
+    }
+    #[doc = "Bits 12:15 - If enabled, this will include the number of the channel corresponding to the measurement"]
+    #[inline(always)]
+    pub fn chan_tag(&self) -> ChanTagR {
+        ChanTagR::new(((self.bits >> 12) & 0x0f) as u8)
+    }
+}
+#[doc = "FIFO data\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`fifo_data::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct FifoDataSpec;
+impl crate::RegisterSpec for FifoDataSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`fifo_data::R`](R) reader structure"]
+impl crate::Readable for FifoDataSpec {}
+#[doc = "`reset()` method sets FIFO_DATA to value 0"]
+impl crate::Resettable for FifoDataSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/adc/irq_clr.rs

@@ -0,0 +1,51 @@
+#[doc = "Register `IRQ_CLR` writer"]
+pub type W = crate::W<IrqClrSpec>;
+#[doc = "Field `FIFO_OFLOW` writer - Clears the FIFO overflow interrupt status. Always reads 0"]
+pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FIFO_UFLOW` writer - Clears the FIFO underflow interrupt status. Always reads 0"]
+pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ADC_DONE` writer - Clears the ADC done interrupt status. Always reads 0"]
+pub type AdcDoneW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TRIG_ERROR` writer - Clears the trigger error interrupt status. Always reads 0"]
+pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>;
+impl W {
+    #[doc = "Bit 0 - Clears the FIFO overflow interrupt status. Always reads 0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_oflow(&mut self) -> FifoOflowW<IrqClrSpec> {
+        FifoOflowW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Clears the FIFO underflow interrupt status. Always reads 0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_uflow(&mut self) -> FifoUflowW<IrqClrSpec> {
+        FifoUflowW::new(self, 1)
+    }
+    #[doc = "Bit 2 - Clears the ADC done interrupt status. Always reads 0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn adc_done(&mut self) -> AdcDoneW<IrqClrSpec> {
+        AdcDoneW::new(self, 2)
+    }
+    #[doc = "Bit 3 - Clears the trigger error interrupt status. Always reads 0"]
+    #[inline(always)]
+    #[must_use]
+    pub fn trig_error(&mut self) -> TrigErrorW<IrqClrSpec> {
+        TrigErrorW::new(self, 3)
+    }
+}
+#[doc = "Clear Interrupt\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqClrSpec;
+impl crate::RegisterSpec for IrqClrSpec {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`irq_clr::W`](W) writer structure"]
+impl crate::Writable for IrqClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_CLR to value 0"]
+impl crate::Resettable for IrqClrSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/adc/irq_enb.rs

@@ -0,0 +1,130 @@
+#[doc = "Register `IRQ_ENB` reader"]
+pub type R = crate::R<IrqEnbSpec>;
+#[doc = "Register `IRQ_ENB` writer"]
+pub type W = crate::W<IrqEnbSpec>;
+#[doc = "Field `FIFO_EMPTY` reader - Enables the interrupt for FIFO empty"]
+pub type FifoEmptyR = crate::BitReader;
+#[doc = "Field `FIFO_EMPTY` writer - Enables the interrupt for FIFO empty"]
+pub type FifoEmptyW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FIFO_FULL` reader - Enables the interrupt for FIFO full"]
+pub type FifoFullR = crate::BitReader;
+#[doc = "Field `FIFO_FULL` writer - Enables the interrupt for FIFO full"]
+pub type FifoFullW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FIFO_OFLOW` reader - Enables the interrupt for a FIFO overflow"]
+pub type FifoOflowR = crate::BitReader;
+#[doc = "Field `FIFO_OFLOW` writer - Enables the interrupt for a FIFO overflow"]
+pub type FifoOflowW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FIFO_UFLOW` reader - Enables the interrupt for a FIFO underflow"]
+pub type FifoUflowR = crate::BitReader;
+#[doc = "Field `FIFO_UFLOW` writer - Enables the interrupt for a FIFO underflow"]
+pub type FifoUflowW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `ADC_DONE` reader - Enables the interrupt for an ADC data acquisition completion"]
+pub type AdcDoneR = crate::BitReader;
+#[doc = "Field `ADC_DONE` writer - Enables the interrupt for an ADC data acquisition completion"]
+pub type AdcDoneW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `TRIG_ERROR` reader - Enables the interrupt for a trigger error"]
+pub type TrigErrorR = crate::BitReader;
+#[doc = "Field `TRIG_ERROR` writer - Enables the interrupt for a trigger error"]
+pub type TrigErrorW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `FIFO_DEPTH_TRIG` reader - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+pub type FifoDepthTrigR = crate::BitReader;
+#[doc = "Field `FIFO_DEPTH_TRIG` writer - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+pub type FifoDepthTrigW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Enables the interrupt for FIFO empty"]
+    #[inline(always)]
+    pub fn fifo_empty(&self) -> FifoEmptyR {
+        FifoEmptyR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Enables the interrupt for FIFO full"]
+    #[inline(always)]
+    pub fn fifo_full(&self) -> FifoFullR {
+        FifoFullR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"]
+    #[inline(always)]
+    pub fn fifo_oflow(&self) -> FifoOflowR {
+        FifoOflowR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"]
+    #[inline(always)]
+    pub fn fifo_uflow(&self) -> FifoUflowR {
+        FifoUflowR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"]
+    #[inline(always)]
+    pub fn adc_done(&self) -> AdcDoneR {
+        AdcDoneR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Enables the interrupt for a trigger error"]
+    #[inline(always)]
+    pub fn trig_error(&self) -> TrigErrorR {
+        TrigErrorR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+    #[inline(always)]
+    pub fn fifo_depth_trig(&self) -> FifoDepthTrigR {
+        FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Enables the interrupt for FIFO empty"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_empty(&mut self) -> FifoEmptyW<IrqEnbSpec> {
+        FifoEmptyW::new(self, 0)
+    }
+    #[doc = "Bit 1 - Enables the interrupt for FIFO full"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_full(&mut self) -> FifoFullW<IrqEnbSpec> {
+        FifoFullW::new(self, 1)
+    }
+    #[doc = "Bit 2 - Enables the interrupt for a FIFO overflow"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_oflow(&mut self) -> FifoOflowW<IrqEnbSpec> {
+        FifoOflowW::new(self, 2)
+    }
+    #[doc = "Bit 3 - Enables the interrupt for a FIFO underflow"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_uflow(&mut self) -> FifoUflowW<IrqEnbSpec> {
+        FifoUflowW::new(self, 3)
+    }
+    #[doc = "Bit 4 - Enables the interrupt for an ADC data acquisition completion"]
+    #[inline(always)]
+    #[must_use]
+    pub fn adc_done(&mut self) -> AdcDoneW<IrqEnbSpec> {
+        AdcDoneW::new(self, 4)
+    }
+    #[doc = "Bit 5 - Enables the interrupt for a trigger error"]
+    #[inline(always)]
+    #[must_use]
+    pub fn trig_error(&mut self) -> TrigErrorW<IrqEnbSpec> {
+        TrigErrorW::new(self, 5)
+    }
+    #[doc = "Bit 6 - Enables the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+    #[inline(always)]
+    #[must_use]
+    pub fn fifo_depth_trig(&mut self) -> FifoDepthTrigW<IrqEnbSpec> {
+        FifoDepthTrigW::new(self, 6)
+    }
+}
+#[doc = "Interrupt Enable\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_enb::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`irq_enb::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEnbSpec;
+impl crate::RegisterSpec for IrqEnbSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_enb::R`](R) reader structure"]
+impl crate::Readable for IrqEnbSpec {}
+#[doc = "`write(|w| ..)` method takes [`irq_enb::W`](W) writer structure"]
+impl crate::Writable for IrqEnbSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets IRQ_ENB to value 0"]
+impl crate::Resettable for IrqEnbSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/adc/irq_end.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `IRQ_END` reader"]
+pub type R = crate::R<IrqEndSpec>;
+#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty and the interrupt is enabled"]
+pub type FifoEmptyR = crate::BitReader;
+#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full and the interrupt is enabled"]
+pub type FifoFullR = crate::BitReader;
+#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred and the interrupt is enabled"]
+pub type FifoOflowR = crate::BitReader;
+#[doc = "Field `FIFO_UFLOW` reader - Indicates a FIFO underflow occurred and the interrupt is enabled"]
+pub type FifoUflowR = crate::BitReader;
+#[doc = "Field `ADC_DONE` reader - Indicates that a ADC conversion is done and the interrupt is enabled"]
+pub type AdcDoneR = crate::BitReader;
+#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled"]
+pub type TrigErrorR = crate::BitReader;
+#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+pub type FifoDepthTrigR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Indicates the FIFO is empty and the interrupt is enabled"]
+    #[inline(always)]
+    pub fn fifo_empty(&self) -> FifoEmptyR {
+        FifoEmptyR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Indicates the FIFO is full and the interrupt is enabled"]
+    #[inline(always)]
+    pub fn fifo_full(&self) -> FifoFullR {
+        FifoFullR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Indicates a FIFO overflow occurred and the interrupt is enabled"]
+    #[inline(always)]
+    pub fn fifo_oflow(&self) -> FifoOflowR {
+        FifoOflowR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Indicates a FIFO underflow occurred and the interrupt is enabled"]
+    #[inline(always)]
+    pub fn fifo_uflow(&self) -> FifoUflowR {
+        FifoUflowR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Indicates that a ADC conversion is done and the interrupt is enabled"]
+    #[inline(always)]
+    pub fn adc_done(&self) -> AdcDoneR {
+        AdcDoneR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion and the interrupt is enabled"]
+    #[inline(always)]
+    pub fn trig_error(&self) -> TrigErrorR {
+        TrigErrorR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+    #[inline(always)]
+    pub fn fifo_depth_trig(&self) -> FifoDepthTrigR {
+        FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[doc = "Enabled Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_end::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqEndSpec;
+impl crate::RegisterSpec for IrqEndSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_end::R`](R) reader structure"]
+impl crate::Readable for IrqEndSpec {}
+#[doc = "`reset()` method sets IRQ_END to value 0"]
+impl crate::Resettable for IrqEndSpec {
+    const RESET_VALUE: u32 = 0;
+}

va416xx/src/adc/irq_raw.rs

@@ -0,0 +1,64 @@
+#[doc = "Register `IRQ_RAW` reader"]
+pub type R = crate::R<IrqRawSpec>;
+#[doc = "Field `FIFO_EMPTY` reader - Indicates the FIFO is empty"]
+pub type FifoEmptyR = crate::BitReader;
+#[doc = "Field `FIFO_FULL` reader - Indicates the FIFO is full"]
+pub type FifoFullR = crate::BitReader;
+#[doc = "Field `FIFO_OFLOW` reader - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"]
+pub type FifoOflowR = crate::BitReader;
+#[doc = "Field `FIFO_UFLOW` reader - Indicates data was unavailable when a new trigger for ADC update is received"]
+pub type FifoUflowR = crate::BitReader;
+#[doc = "Field `ADC_DONE` reader - Indicates that a ADC conversion is done"]
+pub type AdcDoneR = crate::BitReader;
+#[doc = "Field `TRIG_ERROR` reader - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion"]
+pub type TrigErrorR = crate::BitReader;
+#[doc = "Field `FIFO_DEPTH_TRIG` reader - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+pub type FifoDepthTrigR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Indicates the FIFO is empty"]
+    #[inline(always)]
+    pub fn fifo_empty(&self) -> FifoEmptyR {
+        FifoEmptyR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Indicates the FIFO is full"]
+    #[inline(always)]
+    pub fn fifo_full(&self) -> FifoFullR {
+        FifoFullR::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Indicates a FIFO overflow occurred (FIFO was full when new data was written)"]
+    #[inline(always)]
+    pub fn fifo_oflow(&self) -> FifoOflowR {
+        FifoOflowR::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Indicates data was unavailable when a new trigger for ADC update is received"]
+    #[inline(always)]
+    pub fn fifo_uflow(&self) -> FifoUflowR {
+        FifoUflowR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bit 4 - Indicates that a ADC conversion is done"]
+    #[inline(always)]
+    pub fn adc_done(&self) -> AdcDoneR {
+        AdcDoneR::new(((self.bits >> 4) & 1) != 0)
+    }
+    #[doc = "Bit 5 - Indicates a manual or external trigger occurred when the ADC was BUSY doing a conversion"]
+    #[inline(always)]
+    pub fn trig_error(&self) -> TrigErrorR {
+        TrigErrorR::new(((self.bits >> 5) & 1) != 0)
+    }
+    #[doc = "Bit 6 - Indicates the interrupt for the FIFO entry count meets or exceeds the trigger level"]
+    #[inline(always)]
+    pub fn fifo_depth_trig(&self) -> FifoDepthTrigR {
+        FifoDepthTrigR::new(((self.bits >> 6) & 1) != 0)
+    }
+}
+#[doc = "Raw Interrupt Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`irq_raw::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IrqRawSpec;
+impl crate::RegisterSpec for IrqRawSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`irq_raw::R`](R) reader structure"]
+impl crate::Readable for IrqRawSpec {}
+#[doc = "`reset()` method sets IRQ_RAW to value 0x01"]
+impl crate::Resettable for IrqRawSpec {
+    const RESET_VALUE: u32 = 0x01;
+}

va416xx/src/adc/perid.rs

@@ -0,0 +1,18 @@
+#[doc = "Register `PERID` reader"]
+pub type R = crate::R<PeridSpec>;
+impl core::fmt::Debug for R {
+    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
+        write!(f, "{}", self.bits())
+    }
+}
+#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeridSpec;
+impl crate::RegisterSpec for PeridSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
+impl crate::Readable for PeridSpec {}
+#[doc = "`reset()` method sets PERID to value 0x0019_07e9"]
+impl crate::Resettable for PeridSpec {
+    const RESET_VALUE: u32 = 0x0019_07e9;
+}

va416xx/src/adc/rxfifoirqtrg.rs

@@ -0,0 +1,40 @@
+#[doc = "Register `RXFIFOIRQTRG` reader"]
+pub type R = crate::R<RxfifoirqtrgSpec>;
+#[doc = "Register `RXFIFOIRQTRG` writer"]
+pub type W = crate::W<RxfifoirqtrgSpec>;
+#[doc = "Field `LEVEL` reader - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"]
+pub type LevelR = crate::FieldReader;
+#[doc = "Field `LEVEL` writer - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"]
+pub type LevelW<'a, REG> = crate::FieldWriter<'a, REG, 5>;
+impl R {
+    #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"]
+    #[inline(always)]
+    pub fn level(&self) -> LevelR {
+        LevelR::new((self.bits & 0x1f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:4 - Sets the FIFO_ENTRY_CNT value that asserts the FIFO_DEPTH_TRIG interrupt"]
+    #[inline(always)]
+    #[must_use]
+    pub fn level(&mut self) -> LevelW<RxfifoirqtrgSpec> {
+        LevelW::new(self, 0)
+    }
+}
+#[doc = "Receive FIFO Interrupt Trigger Value\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`rxfifoirqtrg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`rxfifoirqtrg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct RxfifoirqtrgSpec;
+impl crate::RegisterSpec for RxfifoirqtrgSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`rxfifoirqtrg::R`](R) reader structure"]
+impl crate::Readable for RxfifoirqtrgSpec {}
+#[doc = "`write(|w| ..)` method takes [`rxfifoirqtrg::W`](W) writer structure"]
+impl crate::Writable for RxfifoirqtrgSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets RXFIFOIRQTRG to value 0x10"]
+impl crate::Resettable for RxfifoirqtrgSpec {
+    const RESET_VALUE: u32 = 0x10;
+}

va416xx/src/adc/status.rs

@@ -0,0 +1,29 @@
+#[doc = "Register `STATUS` reader"]
+pub type R = crate::R<StatusSpec>;
+#[doc = "Field `FIFO_ENTRY_CNT` reader - Indicates the number of entries in the FIFO"]
+pub type FifoEntryCntR = crate::FieldReader;
+#[doc = "Field `ADC_BUSY` reader - Indicates an ADC data acquisition is in process"]
+pub type AdcBusyR = crate::BitReader;
+impl R {
+    #[doc = "Bits 0:5 - Indicates the number of entries in the FIFO"]
+    #[inline(always)]
+    pub fn fifo_entry_cnt(&self) -> FifoEntryCntR {
+        FifoEntryCntR::new((self.bits & 0x3f) as u8)
+    }
+    #[doc = "Bit 7 - Indicates an ADC data acquisition is in process"]
+    #[inline(always)]
+    pub fn adc_busy(&self) -> AdcBusyR {
+        AdcBusyR::new(((self.bits >> 7) & 1) != 0)
+    }
+}
+#[doc = "Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct StatusSpec;
+impl crate::RegisterSpec for StatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`status::R`](R) reader structure"]
+impl crate::Readable for StatusSpec {}
+#[doc = "`reset()` method sets STATUS to value 0"]
+impl crate::Resettable for StatusSpec {
+    const RESET_VALUE: u32 = 0;
+}