Init Commit

Monorepo for Rust support of VA416XX family of radiation hardened MCUs
2021-12-07 00:31:51 +01:00
commit 5d1740efea
606 changed files with 74678 additions and 0 deletions
--- a/va416xx/src/dma/alt_ctrl_base_ptr.rs
+++ b/va416xx/src/dma/alt_ctrl_base_ptr.rs
@ -0,0 +1,40 @@
+#[doc = "Register `ALT_CTRL_BASE_PTR` reader"]
+pub type R = crate::R<AltCtrlBasePtrSpec>;
+#[doc = "Register `ALT_CTRL_BASE_PTR` writer"]
+pub type W = crate::W<AltCtrlBasePtrSpec>;
+#[doc = "Field `ALT_CTRL_BASE_PTR` reader - Base Pointer for Alternate DMA Control Register"]
+pub type AltCtrlBasePtrR = crate::FieldReader<u32>;
+#[doc = "Field `ALT_CTRL_BASE_PTR` writer - Base Pointer for Alternate DMA Control Register"]
+pub type AltCtrlBasePtrW<'a, REG> = crate::FieldWriter<'a, REG, 32, u32>;
+impl R {
+    #[doc = "Bits 0:31 - Base Pointer for Alternate DMA Control Register"]
+    #[inline(always)]
+    pub fn alt_ctrl_base_ptr(&self) -> AltCtrlBasePtrR {
+        AltCtrlBasePtrR::new(self.bits)
+    }
+}
+impl W {
+    #[doc = "Bits 0:31 - Base Pointer for Alternate DMA Control Register"]
+    #[inline(always)]
+    #[must_use]
+    pub fn alt_ctrl_base_ptr(&mut self) -> AltCtrlBasePtrW<AltCtrlBasePtrSpec> {
+        AltCtrlBasePtrW::new(self, 0)
+    }
+}
+#[doc = "DMA Channel alternate control data base pointer\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`alt_ctrl_base_ptr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`alt_ctrl_base_ptr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct AltCtrlBasePtrSpec;
+impl crate::RegisterSpec for AltCtrlBasePtrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`alt_ctrl_base_ptr::R`](R) reader structure"]
+impl crate::Readable for AltCtrlBasePtrSpec {}
+#[doc = "`write(|w| ..)` method takes [`alt_ctrl_base_ptr::W`](W) writer structure"]
+impl crate::Writable for AltCtrlBasePtrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ALT_CTRL_BASE_PTR to value 0"]
+impl crate::Resettable for AltCtrlBasePtrSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/cfg.rs
+++ b/va416xx/src/dma/cfg.rs
@ -0,0 +1,35 @@
+#[doc = "Register `CFG` writer"]
+pub type W = crate::W<CfgSpec>;
+#[doc = "Field `MASTER_ENABLE` writer - PLL Symbol; Feedback cycle slip output (CLKOUT frequency low)"]
+pub type MasterEnableW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CHNL_PROT_CTRL` writer - HPROT\\[3:0\\]"]
+pub type ChnlProtCtrlW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+impl W {
+    #[doc = "Bit 0 - PLL Symbol; Feedback cycle slip output (CLKOUT frequency low)"]
+    #[inline(always)]
+    #[must_use]
+    pub fn master_enable(&mut self) -> MasterEnableW<CfgSpec> {
+        MasterEnableW::new(self, 0)
+    }
+    #[doc = "Bits 5:7 - HPROT\\[3:0\\]"]
+    #[inline(always)]
+    #[must_use]
+    pub fn chnl_prot_ctrl(&mut self) -> ChnlProtCtrlW<CfgSpec> {
+        ChnlProtCtrlW::new(self, 5)
+    }
+}
+#[doc = "DMA Configuration\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`cfg::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CfgSpec;
+impl crate::RegisterSpec for CfgSpec {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`cfg::W`](W) writer structure"]
+impl crate::Writable for CfgSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CFG to value 0"]
+impl crate::Resettable for CfgSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/chnl_enable_clr.rs
+++ b/va416xx/src/dma/chnl_enable_clr.rs
@ -0,0 +1,85 @@
+#[doc = "Register `CHNL_ENABLE_CLR` reader"]
+pub type R = crate::R<ChnlEnableClrSpec>;
+#[doc = "Register `CHNL_ENABLE_CLR` writer"]
+pub type W = crate::W<ChnlEnableClrSpec>;
+#[doc = "Field `CH0` reader - Channel Enable clear"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - Channel Enable clear"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - Channel Enable clear"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - Channel Enable clear"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - Channel Enable clear"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - Channel Enable clear"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - Channel Enable clear"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - Channel Enable clear"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Channel Enable clear"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Channel Enable clear"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Channel Enable clear"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Channel Enable clear"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Channel Enable clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<ChnlEnableClrSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Channel Enable clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<ChnlEnableClrSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Channel Enable clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<ChnlEnableClrSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Channel Enable clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<ChnlEnableClrSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA channel enable clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_enable_clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_enable_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ChnlEnableClrSpec;
+impl crate::RegisterSpec for ChnlEnableClrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`chnl_enable_clr::R`](R) reader structure"]
+impl crate::Readable for ChnlEnableClrSpec {}
+#[doc = "`write(|w| ..)` method takes [`chnl_enable_clr::W`](W) writer structure"]
+impl crate::Writable for ChnlEnableClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CHNL_ENABLE_CLR to value 0"]
+impl crate::Resettable for ChnlEnableClrSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/chnl_enable_set.rs
+++ b/va416xx/src/dma/chnl_enable_set.rs
@ -0,0 +1,85 @@
+#[doc = "Register `CHNL_ENABLE_SET` reader"]
+pub type R = crate::R<ChnlEnableSetSpec>;
+#[doc = "Register `CHNL_ENABLE_SET` writer"]
+pub type W = crate::W<ChnlEnableSetSpec>;
+#[doc = "Field `CH0` reader - Channel Enable set"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - Channel Enable set"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - Channel Enable set"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - Channel Enable set"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - Channel Enable set"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - Channel Enable set"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - Channel Enable set"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - Channel Enable set"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Channel Enable set"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Channel Enable set"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Channel Enable set"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Channel Enable set"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Channel Enable set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<ChnlEnableSetSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Channel Enable set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<ChnlEnableSetSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Channel Enable set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<ChnlEnableSetSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Channel Enable set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<ChnlEnableSetSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA channel enable set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_enable_set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_enable_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ChnlEnableSetSpec;
+impl crate::RegisterSpec for ChnlEnableSetSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`chnl_enable_set::R`](R) reader structure"]
+impl crate::Readable for ChnlEnableSetSpec {}
+#[doc = "`write(|w| ..)` method takes [`chnl_enable_set::W`](W) writer structure"]
+impl crate::Writable for ChnlEnableSetSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CHNL_ENABLE_SET to value 0"]
+impl crate::Resettable for ChnlEnableSetSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/chnl_pri_alt_clr.rs
+++ b/va416xx/src/dma/chnl_pri_alt_clr.rs
@ -0,0 +1,85 @@
+#[doc = "Register `CHNL_PRI_ALT_CLR` reader"]
+pub type R = crate::R<ChnlPriAltClrSpec>;
+#[doc = "Register `CHNL_PRI_ALT_CLR` writer"]
+pub type W = crate::W<ChnlPriAltClrSpec>;
+#[doc = "Field `CH0` reader - Channel PRI_ALT clear"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - Channel PRI_ALT clear"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - Channel PRI_ALT clear"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - Channel PRI_ALT clear"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - Channel PRI_ALT clear"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - Channel PRI_ALT clear"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - Channel PRI_ALT clear"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - Channel PRI_ALT clear"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Channel PRI_ALT clear"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Channel PRI_ALT clear"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Channel PRI_ALT clear"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Channel PRI_ALT clear"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Channel PRI_ALT clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<ChnlPriAltClrSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Channel PRI_ALT clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<ChnlPriAltClrSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Channel PRI_ALT clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<ChnlPriAltClrSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Channel PRI_ALT clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<ChnlPriAltClrSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA channel primary alternate clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_pri_alt_clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_pri_alt_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ChnlPriAltClrSpec;
+impl crate::RegisterSpec for ChnlPriAltClrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`chnl_pri_alt_clr::R`](R) reader structure"]
+impl crate::Readable for ChnlPriAltClrSpec {}
+#[doc = "`write(|w| ..)` method takes [`chnl_pri_alt_clr::W`](W) writer structure"]
+impl crate::Writable for ChnlPriAltClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CHNL_PRI_ALT_CLR to value 0"]
+impl crate::Resettable for ChnlPriAltClrSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/chnl_pri_alt_set.rs
+++ b/va416xx/src/dma/chnl_pri_alt_set.rs
@ -0,0 +1,85 @@
+#[doc = "Register `CHNL_PRI_ALT_SET` reader"]
+pub type R = crate::R<ChnlPriAltSetSpec>;
+#[doc = "Register `CHNL_PRI_ALT_SET` writer"]
+pub type W = crate::W<ChnlPriAltSetSpec>;
+#[doc = "Field `CH0` reader - Channel PRI_ALT set"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - Channel PRI_ALT set"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - Channel PRI_ALT set"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - Channel PRI_ALT set"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - Channel PRI_ALT set"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - Channel PRI_ALT set"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - Channel PRI_ALT set"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - Channel PRI_ALT set"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Channel PRI_ALT set"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Channel PRI_ALT set"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Channel PRI_ALT set"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Channel PRI_ALT set"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Channel PRI_ALT set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<ChnlPriAltSetSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Channel PRI_ALT set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<ChnlPriAltSetSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Channel PRI_ALT set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<ChnlPriAltSetSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Channel PRI_ALT set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<ChnlPriAltSetSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA channel primary alternate set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_pri_alt_set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_pri_alt_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ChnlPriAltSetSpec;
+impl crate::RegisterSpec for ChnlPriAltSetSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`chnl_pri_alt_set::R`](R) reader structure"]
+impl crate::Readable for ChnlPriAltSetSpec {}
+#[doc = "`write(|w| ..)` method takes [`chnl_pri_alt_set::W`](W) writer structure"]
+impl crate::Writable for ChnlPriAltSetSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CHNL_PRI_ALT_SET to value 0"]
+impl crate::Resettable for ChnlPriAltSetSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/chnl_priority_clr.rs
+++ b/va416xx/src/dma/chnl_priority_clr.rs
@ -0,0 +1,51 @@
+#[doc = "Register `CHNL_PRIORITY_CLR` writer"]
+pub type W = crate::W<ChnlPriorityClrSpec>;
+#[doc = "Field `CH0` writer - Channel PRIORITY clear"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` writer - Channel PRIORITY clear"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` writer - Channel PRIORITY clear"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` writer - Channel PRIORITY clear"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl W {
+    #[doc = "Bit 0 - Channel PRIORITY clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<ChnlPriorityClrSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Channel PRIORITY clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<ChnlPriorityClrSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Channel PRIORITY clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<ChnlPriorityClrSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Channel PRIORITY clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<ChnlPriorityClrSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA channel priority clear\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_priority_clr::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ChnlPriorityClrSpec;
+impl crate::RegisterSpec for ChnlPriorityClrSpec {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`chnl_priority_clr::W`](W) writer structure"]
+impl crate::Writable for ChnlPriorityClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CHNL_PRIORITY_CLR to value 0"]
+impl crate::Resettable for ChnlPriorityClrSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/chnl_priority_set.rs
+++ b/va416xx/src/dma/chnl_priority_set.rs
@ -0,0 +1,85 @@
+#[doc = "Register `CHNL_PRIORITY_SET` reader"]
+pub type R = crate::R<ChnlPrioritySetSpec>;
+#[doc = "Register `CHNL_PRIORITY_SET` writer"]
+pub type W = crate::W<ChnlPrioritySetSpec>;
+#[doc = "Field `CH0` reader - Channel PRIORITY set"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - Channel PRIORITY set"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - Channel PRIORITY set"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - Channel PRIORITY set"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - Channel PRIORITY set"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - Channel PRIORITY set"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - Channel PRIORITY set"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - Channel PRIORITY set"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Channel PRIORITY set"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Channel PRIORITY set"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Channel PRIORITY set"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Channel PRIORITY set"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Channel PRIORITY set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<ChnlPrioritySetSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Channel PRIORITY set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<ChnlPrioritySetSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Channel PRIORITY set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<ChnlPrioritySetSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Channel PRIORITY set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<ChnlPrioritySetSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA channel priority set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_priority_set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_priority_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ChnlPrioritySetSpec;
+impl crate::RegisterSpec for ChnlPrioritySetSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`chnl_priority_set::R`](R) reader structure"]
+impl crate::Readable for ChnlPrioritySetSpec {}
+#[doc = "`write(|w| ..)` method takes [`chnl_priority_set::W`](W) writer structure"]
+impl crate::Writable for ChnlPrioritySetSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CHNL_PRIORITY_SET to value 0"]
+impl crate::Resettable for ChnlPrioritySetSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/chnl_req_mask_clr.rs
+++ b/va416xx/src/dma/chnl_req_mask_clr.rs
@ -0,0 +1,85 @@
+#[doc = "Register `CHNL_REQ_MASK_CLR` reader"]
+pub type R = crate::R<ChnlReqMaskClrSpec>;
+#[doc = "Register `CHNL_REQ_MASK_CLR` writer"]
+pub type W = crate::W<ChnlReqMaskClrSpec>;
+#[doc = "Field `CH0` reader - Channel Request Mask clear"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - Channel Request Mask clear"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - Channel Request Mask clear"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - Channel Request Mask clear"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - Channel Request Mask clear"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - Channel Request Mask clear"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - Channel Request Mask clear"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - Channel Request Mask clear"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Channel Request Mask clear"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Channel Request Mask clear"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Channel Request Mask clear"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Channel Request Mask clear"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Channel Request Mask clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<ChnlReqMaskClrSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Channel Request Mask clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<ChnlReqMaskClrSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Channel Request Mask clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<ChnlReqMaskClrSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Channel Request Mask clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<ChnlReqMaskClrSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA channel request mask clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_req_mask_clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_req_mask_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ChnlReqMaskClrSpec;
+impl crate::RegisterSpec for ChnlReqMaskClrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`chnl_req_mask_clr::R`](R) reader structure"]
+impl crate::Readable for ChnlReqMaskClrSpec {}
+#[doc = "`write(|w| ..)` method takes [`chnl_req_mask_clr::W`](W) writer structure"]
+impl crate::Writable for ChnlReqMaskClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CHNL_REQ_MASK_CLR to value 0"]
+impl crate::Resettable for ChnlReqMaskClrSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/chnl_req_mask_set.rs
+++ b/va416xx/src/dma/chnl_req_mask_set.rs
@ -0,0 +1,85 @@
+#[doc = "Register `CHNL_REQ_MASK_SET` reader"]
+pub type R = crate::R<ChnlReqMaskSetSpec>;
+#[doc = "Register `CHNL_REQ_MASK_SET` writer"]
+pub type W = crate::W<ChnlReqMaskSetSpec>;
+#[doc = "Field `CH0` reader - Channel Request Mask set"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - Channel Request Mask set"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - Channel Request Mask set"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - Channel Request Mask set"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - Channel Request Mask set"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - Channel Request Mask set"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - Channel Request Mask set"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - Channel Request Mask set"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Channel Request Mask set"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Channel Request Mask set"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Channel Request Mask set"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Channel Request Mask set"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Channel Request Mask set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<ChnlReqMaskSetSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Channel Request Mask set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<ChnlReqMaskSetSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Channel Request Mask set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<ChnlReqMaskSetSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Channel Request Mask set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<ChnlReqMaskSetSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA channel request mask set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_req_mask_set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_req_mask_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ChnlReqMaskSetSpec;
+impl crate::RegisterSpec for ChnlReqMaskSetSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`chnl_req_mask_set::R`](R) reader structure"]
+impl crate::Readable for ChnlReqMaskSetSpec {}
+#[doc = "`write(|w| ..)` method takes [`chnl_req_mask_set::W`](W) writer structure"]
+impl crate::Writable for ChnlReqMaskSetSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CHNL_REQ_MASK_SET to value 0"]
+impl crate::Resettable for ChnlReqMaskSetSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/chnl_sw_request.rs
+++ b/va416xx/src/dma/chnl_sw_request.rs
@ -0,0 +1,51 @@
+#[doc = "Register `CHNL_SW_REQUEST` writer"]
+pub type W = crate::W<ChnlSwRequestSpec>;
+#[doc = "Field `CH0` writer - Channel SW request"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` writer - Channel SW request"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` writer - Channel SW request"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` writer - Channel SW request"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl W {
+    #[doc = "Bit 0 - Channel SW request"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<ChnlSwRequestSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Channel SW request"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<ChnlSwRequestSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Channel SW request"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<ChnlSwRequestSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Channel SW request"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<ChnlSwRequestSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA channel software request\n\nYou can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_sw_request::W`](W). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ChnlSwRequestSpec;
+impl crate::RegisterSpec for ChnlSwRequestSpec {
+    type Ux = u32;
+}
+#[doc = "`write(|w| ..)` method takes [`chnl_sw_request::W`](W) writer structure"]
+impl crate::Writable for ChnlSwRequestSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CHNL_SW_REQUEST to value 0"]
+impl crate::Resettable for ChnlSwRequestSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/chnl_useburst_clr.rs
+++ b/va416xx/src/dma/chnl_useburst_clr.rs
@ -0,0 +1,85 @@
+#[doc = "Register `CHNL_USEBURST_CLR` reader"]
+pub type R = crate::R<ChnlUseburstClrSpec>;
+#[doc = "Register `CHNL_USEBURST_CLR` writer"]
+pub type W = crate::W<ChnlUseburstClrSpec>;
+#[doc = "Field `CH0` reader - Channel use burst clear"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - Channel use burst clear"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - Channel use burst clear"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - Channel use burst clear"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - Channel use burst clear"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - Channel use burst clear"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - Channel use burst clear"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - Channel use burst clear"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Channel use burst clear"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Channel use burst clear"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Channel use burst clear"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Channel use burst clear"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Channel use burst clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<ChnlUseburstClrSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Channel use burst clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<ChnlUseburstClrSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Channel use burst clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<ChnlUseburstClrSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Channel use burst clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<ChnlUseburstClrSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA channel useburst clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_useburst_clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_useburst_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ChnlUseburstClrSpec;
+impl crate::RegisterSpec for ChnlUseburstClrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`chnl_useburst_clr::R`](R) reader structure"]
+impl crate::Readable for ChnlUseburstClrSpec {}
+#[doc = "`write(|w| ..)` method takes [`chnl_useburst_clr::W`](W) writer structure"]
+impl crate::Writable for ChnlUseburstClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CHNL_USEBURST_CLR to value 0"]
+impl crate::Resettable for ChnlUseburstClrSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/chnl_useburst_set.rs
+++ b/va416xx/src/dma/chnl_useburst_set.rs
@ -0,0 +1,85 @@
+#[doc = "Register `CHNL_USEBURST_SET` reader"]
+pub type R = crate::R<ChnlUseburstSetSpec>;
+#[doc = "Register `CHNL_USEBURST_SET` writer"]
+pub type W = crate::W<ChnlUseburstSetSpec>;
+#[doc = "Field `CH0` reader - Channel use burst set"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - Channel use burst set"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - Channel use burst set"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - Channel use burst set"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - Channel use burst set"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - Channel use burst set"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - Channel use burst set"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - Channel use burst set"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Channel use burst set"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - Channel use burst set"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - Channel use burst set"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - Channel use burst set"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Channel use burst set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<ChnlUseburstSetSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - Channel use burst set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<ChnlUseburstSetSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - Channel use burst set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<ChnlUseburstSetSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - Channel use burst set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<ChnlUseburstSetSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA channel useburst set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`chnl_useburst_set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`chnl_useburst_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ChnlUseburstSetSpec;
+impl crate::RegisterSpec for ChnlUseburstSetSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`chnl_useburst_set::R`](R) reader structure"]
+impl crate::Readable for ChnlUseburstSetSpec {}
+#[doc = "`write(|w| ..)` method takes [`chnl_useburst_set::W`](W) writer structure"]
+impl crate::Writable for ChnlUseburstSetSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CHNL_USEBURST_SET to value 0"]
+impl crate::Resettable for ChnlUseburstSetSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/ctrl_base_ptr.rs
+++ b/va416xx/src/dma/ctrl_base_ptr.rs
@ -0,0 +1,40 @@
+#[doc = "Register `CTRL_BASE_PTR` reader"]
+pub type R = crate::R<CtrlBasePtrSpec>;
+#[doc = "Register `CTRL_BASE_PTR` writer"]
+pub type W = crate::W<CtrlBasePtrSpec>;
+#[doc = "Field `CTRL_BASE_PTR` reader - Base Pointer for DMA Control Registers"]
+pub type CtrlBasePtrR = crate::FieldReader<u32>;
+#[doc = "Field `CTRL_BASE_PTR` writer - Base Pointer for DMA Control Registers"]
+pub type CtrlBasePtrW<'a, REG> = crate::FieldWriter<'a, REG, 25, u32>;
+impl R {
+    #[doc = "Bits 7:31 - Base Pointer for DMA Control Registers"]
+    #[inline(always)]
+    pub fn ctrl_base_ptr(&self) -> CtrlBasePtrR {
+        CtrlBasePtrR::new((self.bits >> 7) & 0x01ff_ffff)
+    }
+}
+impl W {
+    #[doc = "Bits 7:31 - Base Pointer for DMA Control Registers"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ctrl_base_ptr(&mut self) -> CtrlBasePtrW<CtrlBasePtrSpec> {
+        CtrlBasePtrW::new(self, 7)
+    }
+}
+#[doc = "Base Pointer for DMA Control Registers\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`ctrl_base_ptr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`ctrl_base_ptr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct CtrlBasePtrSpec;
+impl crate::RegisterSpec for CtrlBasePtrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`ctrl_base_ptr::R`](R) reader structure"]
+impl crate::Readable for CtrlBasePtrSpec {}
+#[doc = "`write(|w| ..)` method takes [`ctrl_base_ptr::W`](W) writer structure"]
+impl crate::Writable for CtrlBasePtrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets CTRL_BASE_PTR to value 0"]
+impl crate::Resettable for CtrlBasePtrSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/dma_active_clr.rs
+++ b/va416xx/src/dma/dma_active_clr.rs
@ -0,0 +1,85 @@
+#[doc = "Register `DMA_ACTIVE_CLR` reader"]
+pub type R = crate::R<DmaActiveClrSpec>;
+#[doc = "Register `DMA_ACTIVE_CLR` writer"]
+pub type W = crate::W<DmaActiveClrSpec>;
+#[doc = "Field `CH0` reader - DMA Active clear"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - DMA Active clear"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - DMA Active clear"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - DMA Active clear"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - DMA Active clear"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - DMA Active clear"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - DMA Active clear"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - DMA Active clear"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - DMA Active clear"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - DMA Active clear"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - DMA Active clear"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - DMA Active clear"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - DMA Active clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<DmaActiveClrSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - DMA Active clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<DmaActiveClrSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - DMA Active clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<DmaActiveClrSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - DMA Active clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<DmaActiveClrSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA active clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_active_clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_active_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DmaActiveClrSpec;
+impl crate::RegisterSpec for DmaActiveClrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dma_active_clr::R`](R) reader structure"]
+impl crate::Readable for DmaActiveClrSpec {}
+#[doc = "`write(|w| ..)` method takes [`dma_active_clr::W`](W) writer structure"]
+impl crate::Writable for DmaActiveClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMA_ACTIVE_CLR to value 0"]
+impl crate::Resettable for DmaActiveClrSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/dma_active_set.rs
+++ b/va416xx/src/dma/dma_active_set.rs
@ -0,0 +1,85 @@
+#[doc = "Register `DMA_ACTIVE_SET` reader"]
+pub type R = crate::R<DmaActiveSetSpec>;
+#[doc = "Register `DMA_ACTIVE_SET` writer"]
+pub type W = crate::W<DmaActiveSetSpec>;
+#[doc = "Field `CH0` reader - DMA Active Set"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - DMA Active Set"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - DMA Active Set"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - DMA Active Set"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - DMA Active Set"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - DMA Active Set"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - DMA Active Set"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - DMA Active Set"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - DMA Active Set"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - DMA Active Set"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - DMA Active Set"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - DMA Active Set"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - DMA Active Set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<DmaActiveSetSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - DMA Active Set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<DmaActiveSetSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - DMA Active Set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<DmaActiveSetSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - DMA Active Set"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<DmaActiveSetSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA active set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_active_set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_active_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DmaActiveSetSpec;
+impl crate::RegisterSpec for DmaActiveSetSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dma_active_set::R`](R) reader structure"]
+impl crate::Readable for DmaActiveSetSpec {}
+#[doc = "`write(|w| ..)` method takes [`dma_active_set::W`](W) writer structure"]
+impl crate::Writable for DmaActiveSetSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMA_ACTIVE_SET to value 0"]
+impl crate::Resettable for DmaActiveSetSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/dma_done_clr.rs
+++ b/va416xx/src/dma/dma_done_clr.rs
@ -0,0 +1,85 @@
+#[doc = "Register `DMA_DONE_CLR` reader"]
+pub type R = crate::R<DmaDoneClrSpec>;
+#[doc = "Register `DMA_DONE_CLR` writer"]
+pub type W = crate::W<DmaDoneClrSpec>;
+#[doc = "Field `CH0` reader - DMA Done clear for this CH"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - DMA Done clear for this CH"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - DMA Done clear for this CH"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - DMA Done clear for this CH"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - DMA Done clear for this CH"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - DMA Done clear for this CH"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - DMA Done clear for this CH"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - DMA Done clear for this CH"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - DMA Done clear for this CH"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - DMA Done clear for this CH"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - DMA Done clear for this CH"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - DMA Done clear for this CH"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - DMA Done clear for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<DmaDoneClrSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - DMA Done clear for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<DmaDoneClrSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - DMA Done clear for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<DmaDoneClrSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - DMA Done clear for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<DmaDoneClrSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA done clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_done_clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_done_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DmaDoneClrSpec;
+impl crate::RegisterSpec for DmaDoneClrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dma_done_clr::R`](R) reader structure"]
+impl crate::Readable for DmaDoneClrSpec {}
+#[doc = "`write(|w| ..)` method takes [`dma_done_clr::W`](W) writer structure"]
+impl crate::Writable for DmaDoneClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMA_DONE_CLR to value 0"]
+impl crate::Resettable for DmaDoneClrSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/dma_done_set.rs
+++ b/va416xx/src/dma/dma_done_set.rs
@ -0,0 +1,85 @@
+#[doc = "Register `DMA_DONE_SET` reader"]
+pub type R = crate::R<DmaDoneSetSpec>;
+#[doc = "Register `DMA_DONE_SET` writer"]
+pub type W = crate::W<DmaDoneSetSpec>;
+#[doc = "Field `CH0` reader - DMA Done Set for this CH"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - DMA Done Set for this CH"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - DMA Done Set for this CH"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - DMA Done Set for this CH"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - DMA Done Set for this CH"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - DMA Done Set for this CH"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - DMA Done Set for this CH"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - DMA Done Set for this CH"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - DMA Done Set for this CH"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - DMA Done Set for this CH"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - DMA Done Set for this CH"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - DMA Done Set for this CH"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - DMA Done Set for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<DmaDoneSetSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - DMA Done Set for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<DmaDoneSetSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - DMA Done Set for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<DmaDoneSetSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - DMA Done Set for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<DmaDoneSetSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA done set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_done_set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_done_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DmaDoneSetSpec;
+impl crate::RegisterSpec for DmaDoneSetSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dma_done_set::R`](R) reader structure"]
+impl crate::Readable for DmaDoneSetSpec {}
+#[doc = "`write(|w| ..)` method takes [`dma_done_set::W`](W) writer structure"]
+impl crate::Writable for DmaDoneSetSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMA_DONE_SET to value 0"]
+impl crate::Resettable for DmaDoneSetSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/dma_req_status.rs
+++ b/va416xx/src/dma/dma_req_status.rs
@ -0,0 +1,85 @@
+#[doc = "Register `DMA_REQ_STATUS` reader"]
+pub type R = crate::R<DmaReqStatusSpec>;
+#[doc = "Register `DMA_REQ_STATUS` writer"]
+pub type W = crate::W<DmaReqStatusSpec>;
+#[doc = "Field `CH0` reader - DMA Request Status for this CH"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - DMA Request Status for this CH"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - DMA Request Status for this CH"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - DMA Request Status for this CH"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - DMA Request Status for this CH"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - DMA Request Status for this CH"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - DMA Request Status for this CH"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - DMA Request Status for this CH"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - DMA Request Status for this CH"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - DMA Request Status for this CH"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - DMA Request Status for this CH"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - DMA Request Status for this CH"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - DMA Request Status for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<DmaReqStatusSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - DMA Request Status for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<DmaReqStatusSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - DMA Request Status for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<DmaReqStatusSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - DMA Request Status for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<DmaReqStatusSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA Configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_req_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_req_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DmaReqStatusSpec;
+impl crate::RegisterSpec for DmaReqStatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dma_req_status::R`](R) reader structure"]
+impl crate::Readable for DmaReqStatusSpec {}
+#[doc = "`write(|w| ..)` method takes [`dma_req_status::W`](W) writer structure"]
+impl crate::Writable for DmaReqStatusSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMA_REQ_STATUS to value 0"]
+impl crate::Resettable for DmaReqStatusSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/dma_sreq_status.rs
+++ b/va416xx/src/dma/dma_sreq_status.rs
@ -0,0 +1,85 @@
+#[doc = "Register `DMA_SREQ_STATUS` reader"]
+pub type R = crate::R<DmaSreqStatusSpec>;
+#[doc = "Register `DMA_SREQ_STATUS` writer"]
+pub type W = crate::W<DmaSreqStatusSpec>;
+#[doc = "Field `CH0` reader - DMA SRequest Status for this CH"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH0` writer - DMA SRequest Status for this CH"]
+pub type Ch0W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH1` reader - DMA SRequest Status for this CH"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH1` writer - DMA SRequest Status for this CH"]
+pub type Ch1W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH2` reader - DMA SRequest Status for this CH"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH2` writer - DMA SRequest Status for this CH"]
+pub type Ch2W<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `CH3` reader - DMA SRequest Status for this CH"]
+pub type Ch3R = crate::BitReader;
+#[doc = "Field `CH3` writer - DMA SRequest Status for this CH"]
+pub type Ch3W<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - DMA SRequest Status for this CH"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - DMA SRequest Status for this CH"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - DMA SRequest Status for this CH"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - DMA SRequest Status for this CH"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - DMA SRequest Status for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch0(&mut self) -> Ch0W<DmaSreqStatusSpec> {
+        Ch0W::new(self, 0)
+    }
+    #[doc = "Bit 1 - DMA SRequest Status for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch1(&mut self) -> Ch1W<DmaSreqStatusSpec> {
+        Ch1W::new(self, 1)
+    }
+    #[doc = "Bit 2 - DMA SRequest Status for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch2(&mut self) -> Ch2W<DmaSreqStatusSpec> {
+        Ch2W::new(self, 2)
+    }
+    #[doc = "Bit 3 - DMA SRequest Status for this CH"]
+    #[inline(always)]
+    #[must_use]
+    pub fn ch3(&mut self) -> Ch3W<DmaSreqStatusSpec> {
+        Ch3W::new(self, 3)
+    }
+}
+#[doc = "DMA single request status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`dma_sreq_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`dma_sreq_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct DmaSreqStatusSpec;
+impl crate::RegisterSpec for DmaSreqStatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`dma_sreq_status::R`](R) reader structure"]
+impl crate::Readable for DmaSreqStatusSpec {}
+#[doc = "`write(|w| ..)` method takes [`dma_sreq_status::W`](W) writer structure"]
+impl crate::Writable for DmaSreqStatusSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets DMA_SREQ_STATUS to value 0"]
+impl crate::Resettable for DmaSreqStatusSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/err_clr.rs
+++ b/va416xx/src/dma/err_clr.rs
@ -0,0 +1,40 @@
+#[doc = "Register `ERR_CLR` reader"]
+pub type R = crate::R<ErrClrSpec>;
+#[doc = "Register `ERR_CLR` writer"]
+pub type W = crate::W<ErrClrSpec>;
+#[doc = "Field `ERR_CLR` reader - Error Clear"]
+pub type ErrClrR = crate::BitReader;
+#[doc = "Field `ERR_CLR` writer - Error Clear"]
+pub type ErrClrW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Error Clear"]
+    #[inline(always)]
+    pub fn err_clr(&self) -> ErrClrR {
+        ErrClrR::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Error Clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn err_clr(&mut self) -> ErrClrW<ErrClrSpec> {
+        ErrClrW::new(self, 0)
+    }
+}
+#[doc = "DMA bus error clear\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_clr::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`err_clr::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ErrClrSpec;
+impl crate::RegisterSpec for ErrClrSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`err_clr::R`](R) reader structure"]
+impl crate::Readable for ErrClrSpec {}
+#[doc = "`write(|w| ..)` method takes [`err_clr::W`](W) writer structure"]
+impl crate::Writable for ErrClrSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ERR_CLR to value 0"]
+impl crate::Resettable for ErrClrSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/err_set.rs
+++ b/va416xx/src/dma/err_set.rs
@ -0,0 +1,31 @@
+#[doc = "Register `ERR_SET` reader"]
+pub type R = crate::R<ErrSetSpec>;
+#[doc = "Register `ERR_SET` writer"]
+pub type W = crate::W<ErrSetSpec>;
+#[doc = "Field `ERR_SET` reader - Set Error"]
+pub type ErrSetR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - Set Error"]
+    #[inline(always)]
+    pub fn err_set(&self) -> ErrSetR {
+        ErrSetR::new((self.bits & 1) != 0)
+    }
+}
+impl W {}
+#[doc = "DMA bus error set\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`err_set::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`err_set::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct ErrSetSpec;
+impl crate::RegisterSpec for ErrSetSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`err_set::R`](R) reader structure"]
+impl crate::Readable for ErrSetSpec {}
+#[doc = "`write(|w| ..)` method takes [`err_set::W`](W) writer structure"]
+impl crate::Writable for ErrSetSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets ERR_SET to value 0"]
+impl crate::Resettable for ErrSetSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/integration_cfg.rs
+++ b/va416xx/src/dma/integration_cfg.rs
@ -0,0 +1,40 @@
+#[doc = "Register `INTEGRATION_CFG` reader"]
+pub type R = crate::R<IntegrationCfgSpec>;
+#[doc = "Register `INTEGRATION_CFG` writer"]
+pub type W = crate::W<IntegrationCfgSpec>;
+#[doc = "Field `INT_TEST_EN` reader - Error Clear"]
+pub type IntTestEnR = crate::BitReader;
+#[doc = "Field `INT_TEST_EN` writer - Error Clear"]
+pub type IntTestEnW<'a, REG> = crate::BitWriter<'a, REG>;
+impl R {
+    #[doc = "Bit 0 - Error Clear"]
+    #[inline(always)]
+    pub fn int_test_en(&self) -> IntTestEnR {
+        IntTestEnR::new((self.bits & 1) != 0)
+    }
+}
+impl W {
+    #[doc = "Bit 0 - Error Clear"]
+    #[inline(always)]
+    #[must_use]
+    pub fn int_test_en(&mut self) -> IntTestEnW<IntegrationCfgSpec> {
+        IntTestEnW::new(self, 0)
+    }
+}
+#[doc = "DMA integration configuration\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`integration_cfg::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`integration_cfg::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct IntegrationCfgSpec;
+impl crate::RegisterSpec for IntegrationCfgSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`integration_cfg::R`](R) reader structure"]
+impl crate::Readable for IntegrationCfgSpec {}
+#[doc = "`write(|w| ..)` method takes [`integration_cfg::W`](W) writer structure"]
+impl crate::Writable for IntegrationCfgSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets INTEGRATION_CFG to value 0"]
+impl crate::Resettable for IntegrationCfgSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/periph_id_0.rs
+++ b/va416xx/src/dma/periph_id_0.rs
@ -0,0 +1,40 @@
+#[doc = "Register `PERIPH_ID_0` reader"]
+pub type R = crate::R<PeriphId0Spec>;
+#[doc = "Register `PERIPH_ID_0` writer"]
+pub type W = crate::W<PeriphId0Spec>;
+#[doc = "Field `PART_NUMBER_0` reader - Part Number"]
+pub type PartNumber0R = crate::FieldReader;
+#[doc = "Field `PART_NUMBER_0` writer - Part Number"]
+pub type PartNumber0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - Part Number"]
+    #[inline(always)]
+    pub fn part_number_0(&self) -> PartNumber0R {
+        PartNumber0R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - Part Number"]
+    #[inline(always)]
+    #[must_use]
+    pub fn part_number_0(&mut self) -> PartNumber0W<PeriphId0Spec> {
+        PartNumber0W::new(self, 0)
+    }
+}
+#[doc = "DMA Peripheral ID 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periph_id_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeriphId0Spec;
+impl crate::RegisterSpec for PeriphId0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`periph_id_0::R`](R) reader structure"]
+impl crate::Readable for PeriphId0Spec {}
+#[doc = "`write(|w| ..)` method takes [`periph_id_0::W`](W) writer structure"]
+impl crate::Writable for PeriphId0Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PERIPH_ID_0 to value 0x30"]
+impl crate::Resettable for PeriphId0Spec {
+    const RESET_VALUE: u32 = 0x30;
+}
--- a/va416xx/src/dma/periph_id_1.rs
+++ b/va416xx/src/dma/periph_id_1.rs
@ -0,0 +1,29 @@
+#[doc = "Register `PERIPH_ID_1` reader"]
+pub type R = crate::R<PeriphId1Spec>;
+#[doc = "Field `PART_NUMBER_1` reader - Part Number 1"]
+pub type PartNumber1R = crate::FieldReader;
+#[doc = "Field `JEP106_ID_3_0` reader - Indentity Code"]
+pub type Jep106Id3_0R = crate::FieldReader;
+impl R {
+    #[doc = "Bits 0:3 - Part Number 1"]
+    #[inline(always)]
+    pub fn part_number_1(&self) -> PartNumber1R {
+        PartNumber1R::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - Indentity Code"]
+    #[inline(always)]
+    pub fn jep106_id_3_0(&self) -> Jep106Id3_0R {
+        Jep106Id3_0R::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+}
+#[doc = "DMA Peripheral ID 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_1::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeriphId1Spec;
+impl crate::RegisterSpec for PeriphId1Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`periph_id_1::R`](R) reader structure"]
+impl crate::Readable for PeriphId1Spec {}
+#[doc = "`reset()` method sets PERIPH_ID_1 to value 0xb2"]
+impl crate::Resettable for PeriphId1Spec {
+    const RESET_VALUE: u32 = 0xb2;
+}
--- a/va416xx/src/dma/periph_id_2.rs
+++ b/va416xx/src/dma/periph_id_2.rs
@ -0,0 +1,70 @@
+#[doc = "Register `PERIPH_ID_2` reader"]
+pub type R = crate::R<PeriphId2Spec>;
+#[doc = "Register `PERIPH_ID_2` writer"]
+pub type W = crate::W<PeriphId2Spec>;
+#[doc = "Field `JEP106_ID_6_4` reader - JEP106"]
+pub type Jep106Id6_4R = crate::FieldReader;
+#[doc = "Field `JEP106_ID_6_4` writer - JEP106"]
+pub type Jep106Id6_4W<'a, REG> = crate::FieldWriter<'a, REG, 3>;
+#[doc = "Field `JEDEC_USED` reader - JEDEC"]
+pub type JedecUsedR = crate::BitReader;
+#[doc = "Field `JEDEC_USED` writer - JEDEC"]
+pub type JedecUsedW<'a, REG> = crate::BitWriter<'a, REG>;
+#[doc = "Field `REVISION` reader - Revision"]
+pub type RevisionR = crate::FieldReader;
+#[doc = "Field `REVISION` writer - Revision"]
+pub type RevisionW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:2 - JEP106"]
+    #[inline(always)]
+    pub fn jep106_id_6_4(&self) -> Jep106Id6_4R {
+        Jep106Id6_4R::new((self.bits & 7) as u8)
+    }
+    #[doc = "Bit 3 - JEDEC"]
+    #[inline(always)]
+    pub fn jedec_used(&self) -> JedecUsedR {
+        JedecUsedR::new(((self.bits >> 3) & 1) != 0)
+    }
+    #[doc = "Bits 4:7 - Revision"]
+    #[inline(always)]
+    pub fn revision(&self) -> RevisionR {
+        RevisionR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:2 - JEP106"]
+    #[inline(always)]
+    #[must_use]
+    pub fn jep106_id_6_4(&mut self) -> Jep106Id6_4W<PeriphId2Spec> {
+        Jep106Id6_4W::new(self, 0)
+    }
+    #[doc = "Bit 3 - JEDEC"]
+    #[inline(always)]
+    #[must_use]
+    pub fn jedec_used(&mut self) -> JedecUsedW<PeriphId2Spec> {
+        JedecUsedW::new(self, 3)
+    }
+    #[doc = "Bits 4:7 - Revision"]
+    #[inline(always)]
+    #[must_use]
+    pub fn revision(&mut self) -> RevisionW<PeriphId2Spec> {
+        RevisionW::new(self, 4)
+    }
+}
+#[doc = "DMA Peripheral ID 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periph_id_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeriphId2Spec;
+impl crate::RegisterSpec for PeriphId2Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`periph_id_2::R`](R) reader structure"]
+impl crate::Readable for PeriphId2Spec {}
+#[doc = "`write(|w| ..)` method takes [`periph_id_2::W`](W) writer structure"]
+impl crate::Writable for PeriphId2Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PERIPH_ID_2 to value 0xbc"]
+impl crate::Resettable for PeriphId2Spec {
+    const RESET_VALUE: u32 = 0xbc;
+}
--- a/va416xx/src/dma/periph_id_3.rs
+++ b/va416xx/src/dma/periph_id_3.rs
@ -0,0 +1,40 @@
+#[doc = "Register `PERIPH_ID_3` reader"]
+pub type R = crate::R<PeriphId3Spec>;
+#[doc = "Register `PERIPH_ID_3` writer"]
+pub type W = crate::W<PeriphId3Spec>;
+#[doc = "Field `MOD_NUMBER` reader - Controller Modifications"]
+pub type ModNumberR = crate::FieldReader;
+#[doc = "Field `MOD_NUMBER` writer - Controller Modifications"]
+pub type ModNumberW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - Controller Modifications"]
+    #[inline(always)]
+    pub fn mod_number(&self) -> ModNumberR {
+        ModNumberR::new((self.bits & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - Controller Modifications"]
+    #[inline(always)]
+    #[must_use]
+    pub fn mod_number(&mut self) -> ModNumberW<PeriphId3Spec> {
+        ModNumberW::new(self, 0)
+    }
+}
+#[doc = "DMA Peripheral ID 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periph_id_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeriphId3Spec;
+impl crate::RegisterSpec for PeriphId3Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`periph_id_3::R`](R) reader structure"]
+impl crate::Readable for PeriphId3Spec {}
+#[doc = "`write(|w| ..)` method takes [`periph_id_3::W`](W) writer structure"]
+impl crate::Writable for PeriphId3Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PERIPH_ID_3 to value 0"]
+impl crate::Resettable for PeriphId3Spec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/periph_id_4.rs
+++ b/va416xx/src/dma/periph_id_4.rs
@ -0,0 +1,55 @@
+#[doc = "Register `PERIPH_ID_4` reader"]
+pub type R = crate::R<PeriphId4Spec>;
+#[doc = "Register `PERIPH_ID_4` writer"]
+pub type W = crate::W<PeriphId4Spec>;
+#[doc = "Field `JEP106_C_CODE` reader - JEP106"]
+pub type Jep106CCodeR = crate::FieldReader;
+#[doc = "Field `JEP106_C_CODE` writer - JEP106"]
+pub type Jep106CCodeW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+#[doc = "Field `BLOCK_COUNT` reader - The Number of 4k Address Blocks Required"]
+pub type BlockCountR = crate::FieldReader;
+#[doc = "Field `BLOCK_COUNT` writer - The Number of 4k Address Blocks Required"]
+pub type BlockCountW<'a, REG> = crate::FieldWriter<'a, REG, 4>;
+impl R {
+    #[doc = "Bits 0:3 - JEP106"]
+    #[inline(always)]
+    pub fn jep106_c_code(&self) -> Jep106CCodeR {
+        Jep106CCodeR::new((self.bits & 0x0f) as u8)
+    }
+    #[doc = "Bits 4:7 - The Number of 4k Address Blocks Required"]
+    #[inline(always)]
+    pub fn block_count(&self) -> BlockCountR {
+        BlockCountR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:3 - JEP106"]
+    #[inline(always)]
+    #[must_use]
+    pub fn jep106_c_code(&mut self) -> Jep106CCodeW<PeriphId4Spec> {
+        Jep106CCodeW::new(self, 0)
+    }
+    #[doc = "Bits 4:7 - The Number of 4k Address Blocks Required"]
+    #[inline(always)]
+    #[must_use]
+    pub fn block_count(&mut self) -> BlockCountW<PeriphId4Spec> {
+        BlockCountW::new(self, 4)
+    }
+}
+#[doc = "DMA Peripheral ID 4\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`periph_id_4::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`periph_id_4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PeriphId4Spec;
+impl crate::RegisterSpec for PeriphId4Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`periph_id_4::R`](R) reader structure"]
+impl crate::Readable for PeriphId4Spec {}
+#[doc = "`write(|w| ..)` method takes [`periph_id_4::W`](W) writer structure"]
+impl crate::Writable for PeriphId4Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PERIPH_ID_4 to value 0x04"]
+impl crate::Resettable for PeriphId4Spec {
+    const RESET_VALUE: u32 = 0x04;
+}
--- a/va416xx/src/dma/primecell_id_0.rs
+++ b/va416xx/src/dma/primecell_id_0.rs
@ -0,0 +1,40 @@
+#[doc = "Register `PRIMECELL_ID_0` reader"]
+pub type R = crate::R<PrimecellId0Spec>;
+#[doc = "Register `PRIMECELL_ID_0` writer"]
+pub type W = crate::W<PrimecellId0Spec>;
+#[doc = "Field `PRIMECELL_ID_0` reader - PrimeCell Identification"]
+pub type PrimecellId0R = crate::FieldReader;
+#[doc = "Field `PRIMECELL_ID_0` writer - PrimeCell Identification"]
+pub type PrimecellId0W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - PrimeCell Identification"]
+    #[inline(always)]
+    pub fn primecell_id_0(&self) -> PrimecellId0R {
+        PrimecellId0R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - PrimeCell Identification"]
+    #[inline(always)]
+    #[must_use]
+    pub fn primecell_id_0(&mut self) -> PrimecellId0W<PrimecellId0Spec> {
+        PrimecellId0W::new(self, 0)
+    }
+}
+#[doc = "DMA PrimeCell ID 0\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`primecell_id_0::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`primecell_id_0::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PrimecellId0Spec;
+impl crate::RegisterSpec for PrimecellId0Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`primecell_id_0::R`](R) reader structure"]
+impl crate::Readable for PrimecellId0Spec {}
+#[doc = "`write(|w| ..)` method takes [`primecell_id_0::W`](W) writer structure"]
+impl crate::Writable for PrimecellId0Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PRIMECELL_ID_0 to value 0x0d"]
+impl crate::Resettable for PrimecellId0Spec {
+    const RESET_VALUE: u32 = 0x0d;
+}
--- a/va416xx/src/dma/primecell_id_1.rs
+++ b/va416xx/src/dma/primecell_id_1.rs
@ -0,0 +1,40 @@
+#[doc = "Register `PRIMECELL_ID_1` reader"]
+pub type R = crate::R<PrimecellId1Spec>;
+#[doc = "Register `PRIMECELL_ID_1` writer"]
+pub type W = crate::W<PrimecellId1Spec>;
+#[doc = "Field `PRIMECELL_ID_1` reader - PrimeCell Identification"]
+pub type PrimecellId1R = crate::FieldReader;
+#[doc = "Field `PRIMECELL_ID_1` writer - PrimeCell Identification"]
+pub type PrimecellId1W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - PrimeCell Identification"]
+    #[inline(always)]
+    pub fn primecell_id_1(&self) -> PrimecellId1R {
+        PrimecellId1R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - PrimeCell Identification"]
+    #[inline(always)]
+    #[must_use]
+    pub fn primecell_id_1(&mut self) -> PrimecellId1W<PrimecellId1Spec> {
+        PrimecellId1W::new(self, 0)
+    }
+}
+#[doc = "DMA PrimeCell ID 1\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`primecell_id_1::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`primecell_id_1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PrimecellId1Spec;
+impl crate::RegisterSpec for PrimecellId1Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`primecell_id_1::R`](R) reader structure"]
+impl crate::Readable for PrimecellId1Spec {}
+#[doc = "`write(|w| ..)` method takes [`primecell_id_1::W`](W) writer structure"]
+impl crate::Writable for PrimecellId1Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PRIMECELL_ID_1 to value 0xf0"]
+impl crate::Resettable for PrimecellId1Spec {
+    const RESET_VALUE: u32 = 0xf0;
+}
--- a/va416xx/src/dma/primecell_id_2.rs
+++ b/va416xx/src/dma/primecell_id_2.rs
@ -0,0 +1,40 @@
+#[doc = "Register `PRIMECELL_ID_2` reader"]
+pub type R = crate::R<PrimecellId2Spec>;
+#[doc = "Register `PRIMECELL_ID_2` writer"]
+pub type W = crate::W<PrimecellId2Spec>;
+#[doc = "Field `PRIMECELL_ID_2` reader - PrimeCell Identification"]
+pub type PrimecellId2R = crate::FieldReader;
+#[doc = "Field `PRIMECELL_ID_2` writer - PrimeCell Identification"]
+pub type PrimecellId2W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - PrimeCell Identification"]
+    #[inline(always)]
+    pub fn primecell_id_2(&self) -> PrimecellId2R {
+        PrimecellId2R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - PrimeCell Identification"]
+    #[inline(always)]
+    #[must_use]
+    pub fn primecell_id_2(&mut self) -> PrimecellId2W<PrimecellId2Spec> {
+        PrimecellId2W::new(self, 0)
+    }
+}
+#[doc = "DMA PrimeCell ID 2\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`primecell_id_2::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`primecell_id_2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PrimecellId2Spec;
+impl crate::RegisterSpec for PrimecellId2Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`primecell_id_2::R`](R) reader structure"]
+impl crate::Readable for PrimecellId2Spec {}
+#[doc = "`write(|w| ..)` method takes [`primecell_id_2::W`](W) writer structure"]
+impl crate::Writable for PrimecellId2Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PRIMECELL_ID_2 to value 0x05"]
+impl crate::Resettable for PrimecellId2Spec {
+    const RESET_VALUE: u32 = 0x05;
+}
--- a/va416xx/src/dma/primecell_id_3.rs
+++ b/va416xx/src/dma/primecell_id_3.rs
@ -0,0 +1,40 @@
+#[doc = "Register `PRIMECELL_ID_3` reader"]
+pub type R = crate::R<PrimecellId3Spec>;
+#[doc = "Register `PRIMECELL_ID_3` writer"]
+pub type W = crate::W<PrimecellId3Spec>;
+#[doc = "Field `PRIMECELL_ID_3` reader - PrimeCell Identification"]
+pub type PrimecellId3R = crate::FieldReader;
+#[doc = "Field `PRIMECELL_ID_3` writer - PrimeCell Identification"]
+pub type PrimecellId3W<'a, REG> = crate::FieldWriter<'a, REG, 8>;
+impl R {
+    #[doc = "Bits 0:7 - PrimeCell Identification"]
+    #[inline(always)]
+    pub fn primecell_id_3(&self) -> PrimecellId3R {
+        PrimecellId3R::new((self.bits & 0xff) as u8)
+    }
+}
+impl W {
+    #[doc = "Bits 0:7 - PrimeCell Identification"]
+    #[inline(always)]
+    #[must_use]
+    pub fn primecell_id_3(&mut self) -> PrimecellId3W<PrimecellId3Spec> {
+        PrimecellId3W::new(self, 0)
+    }
+}
+#[doc = "DMA PrimeCell ID 3\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`primecell_id_3::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`primecell_id_3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct PrimecellId3Spec;
+impl crate::RegisterSpec for PrimecellId3Spec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`primecell_id_3::R`](R) reader structure"]
+impl crate::Readable for PrimecellId3Spec {}
+#[doc = "`write(|w| ..)` method takes [`primecell_id_3::W`](W) writer structure"]
+impl crate::Writable for PrimecellId3Spec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets PRIMECELL_ID_3 to value 0xb1"]
+impl crate::Resettable for PrimecellId3Spec {
+    const RESET_VALUE: u32 = 0xb1;
+}
--- a/va416xx/src/dma/stall_status.rs
+++ b/va416xx/src/dma/stall_status.rs
@ -0,0 +1,31 @@
+#[doc = "Register `STALL_STATUS` reader"]
+pub type R = crate::R<StallStatusSpec>;
+#[doc = "Register `STALL_STATUS` writer"]
+pub type W = crate::W<StallStatusSpec>;
+#[doc = "Field `STALL_STATUS` reader - DMA is stalled"]
+pub type StallStatusR = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - DMA is stalled"]
+    #[inline(always)]
+    pub fn stall_status(&self) -> StallStatusR {
+        StallStatusR::new((self.bits & 1) != 0)
+    }
+}
+impl W {}
+#[doc = "DMA stall status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`stall_status::R`](R).  You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`stall_status::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct StallStatusSpec;
+impl crate::RegisterSpec for StallStatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`stall_status::R`](R) reader structure"]
+impl crate::Readable for StallStatusSpec {}
+#[doc = "`write(|w| ..)` method takes [`stall_status::W`](W) writer structure"]
+impl crate::Writable for StallStatusSpec {
+    type Safety = crate::Unsafe;
+    const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+    const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
+}
+#[doc = "`reset()` method sets STALL_STATUS to value 0"]
+impl crate::Resettable for StallStatusSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/status.rs
+++ b/va416xx/src/dma/status.rs
@ -0,0 +1,43 @@
+#[doc = "Register `STATUS` reader"]
+pub type R = crate::R<StatusSpec>;
+#[doc = "Field `MASTER_ENABLE` reader - Enable status of the controller"]
+pub type MasterEnableR = crate::BitReader;
+#[doc = "Field `STATE` reader - Current State of the control state machine"]
+pub type StateR = crate::FieldReader;
+#[doc = "Field `CHNLS_MINUS1` reader - Number of Available Channels Minus 1"]
+pub type ChnlsMinus1R = crate::FieldReader;
+#[doc = "Field `TEST_STATUS` reader - Test Status Logic Included"]
+pub type TestStatusR = crate::FieldReader;
+impl R {
+    #[doc = "Bit 0 - Enable status of the controller"]
+    #[inline(always)]
+    pub fn master_enable(&self) -> MasterEnableR {
+        MasterEnableR::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bits 4:7 - Current State of the control state machine"]
+    #[inline(always)]
+    pub fn state(&self) -> StateR {
+        StateR::new(((self.bits >> 4) & 0x0f) as u8)
+    }
+    #[doc = "Bits 16:20 - Number of Available Channels Minus 1"]
+    #[inline(always)]
+    pub fn chnls_minus1(&self) -> ChnlsMinus1R {
+        ChnlsMinus1R::new(((self.bits >> 16) & 0x1f) as u8)
+    }
+    #[doc = "Bits 28:31 - Test Status Logic Included"]
+    #[inline(always)]
+    pub fn test_status(&self) -> TestStatusR {
+        TestStatusR::new(((self.bits >> 28) & 0x0f) as u8)
+    }
+}
+#[doc = "DMA Status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct StatusSpec;
+impl crate::RegisterSpec for StatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`status::R`](R) reader structure"]
+impl crate::Readable for StatusSpec {}
+#[doc = "`reset()` method sets STATUS to value 0"]
+impl crate::Resettable for StatusSpec {
+    const RESET_VALUE: u32 = 0;
+}
--- a/va416xx/src/dma/waitonreq_status.rs
+++ b/va416xx/src/dma/waitonreq_status.rs
@ -0,0 +1,43 @@
+#[doc = "Register `WAITONREQ_STATUS` reader"]
+pub type R = crate::R<WaitonreqStatusSpec>;
+#[doc = "Field `CH0` reader - DMA wait on request"]
+pub type Ch0R = crate::BitReader;
+#[doc = "Field `CH1` reader - DMA wait on request"]
+pub type Ch1R = crate::BitReader;
+#[doc = "Field `CH2` reader - DMA wait on request"]
+pub type Ch2R = crate::BitReader;
+#[doc = "Field `CH3` reader - DMA wait on request"]
+pub type Ch3R = crate::BitReader;
+impl R {
+    #[doc = "Bit 0 - DMA wait on request"]
+    #[inline(always)]
+    pub fn ch0(&self) -> Ch0R {
+        Ch0R::new((self.bits & 1) != 0)
+    }
+    #[doc = "Bit 1 - DMA wait on request"]
+    #[inline(always)]
+    pub fn ch1(&self) -> Ch1R {
+        Ch1R::new(((self.bits >> 1) & 1) != 0)
+    }
+    #[doc = "Bit 2 - DMA wait on request"]
+    #[inline(always)]
+    pub fn ch2(&self) -> Ch2R {
+        Ch2R::new(((self.bits >> 2) & 1) != 0)
+    }
+    #[doc = "Bit 3 - DMA wait on request"]
+    #[inline(always)]
+    pub fn ch3(&self) -> Ch3R {
+        Ch3R::new(((self.bits >> 3) & 1) != 0)
+    }
+}
+#[doc = "DMA channel wait on request status\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`waitonreq_status::R`](R).  See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
+pub struct WaitonreqStatusSpec;
+impl crate::RegisterSpec for WaitonreqStatusSpec {
+    type Ux = u32;
+}
+#[doc = "`read()` method returns [`waitonreq_status::R`](R) reader structure"]
+impl crate::Readable for WaitonreqStatusSpec {}
+#[doc = "`reset()` method sets WAITONREQ_STATUS to value 0"]
+impl crate::Resettable for WaitonreqStatusSpec {
+    const RESET_VALUE: u32 = 0;
+}