Monorepo for Rust support of VA416XX family of radiation hardened MCUs
This commit is contained in:
18
va416xx/src/ioconfig/clkdiv0.rs
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18
va416xx/src/ioconfig/clkdiv0.rs
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@ -0,0 +1,18 @@
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#[doc = "Register `CLKDIV0` reader"]
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pub type R = crate::R<Clkdiv0Spec>;
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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write!(f, "{}", self.bits())
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}
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}
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#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv0::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct Clkdiv0Spec;
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impl crate::RegisterSpec for Clkdiv0Spec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`clkdiv0::R`](R) reader structure"]
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impl crate::Readable for Clkdiv0Spec {}
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#[doc = "`reset()` method sets CLKDIV0 to value 0"]
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impl crate::Resettable for Clkdiv0Spec {
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const RESET_VALUE: u32 = 0;
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}
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27
va416xx/src/ioconfig/clkdiv1.rs
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27
va416xx/src/ioconfig/clkdiv1.rs
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@ -0,0 +1,27 @@
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#[doc = "Register `CLKDIV1` reader"]
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pub type R = crate::R<Clkdiv1Spec>;
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#[doc = "Register `CLKDIV1` writer"]
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pub type W = crate::W<Clkdiv1Spec>;
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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write!(f, "{}", self.bits())
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}
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}
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impl W {}
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#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv1::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv1::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct Clkdiv1Spec;
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impl crate::RegisterSpec for Clkdiv1Spec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`clkdiv1::R`](R) reader structure"]
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impl crate::Readable for Clkdiv1Spec {}
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#[doc = "`write(|w| ..)` method takes [`clkdiv1::W`](W) writer structure"]
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impl crate::Writable for Clkdiv1Spec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CLKDIV1 to value 0"]
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impl crate::Resettable for Clkdiv1Spec {
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const RESET_VALUE: u32 = 0;
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}
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27
va416xx/src/ioconfig/clkdiv2.rs
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27
va416xx/src/ioconfig/clkdiv2.rs
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@ -0,0 +1,27 @@
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#[doc = "Register `CLKDIV2` reader"]
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pub type R = crate::R<Clkdiv2Spec>;
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#[doc = "Register `CLKDIV2` writer"]
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pub type W = crate::W<Clkdiv2Spec>;
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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write!(f, "{}", self.bits())
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}
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}
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impl W {}
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#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv2::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv2::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct Clkdiv2Spec;
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impl crate::RegisterSpec for Clkdiv2Spec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`clkdiv2::R`](R) reader structure"]
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impl crate::Readable for Clkdiv2Spec {}
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#[doc = "`write(|w| ..)` method takes [`clkdiv2::W`](W) writer structure"]
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impl crate::Writable for Clkdiv2Spec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CLKDIV2 to value 0"]
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impl crate::Resettable for Clkdiv2Spec {
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const RESET_VALUE: u32 = 0;
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}
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27
va416xx/src/ioconfig/clkdiv3.rs
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27
va416xx/src/ioconfig/clkdiv3.rs
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@ -0,0 +1,27 @@
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#[doc = "Register `CLKDIV3` reader"]
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pub type R = crate::R<Clkdiv3Spec>;
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#[doc = "Register `CLKDIV3` writer"]
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pub type W = crate::W<Clkdiv3Spec>;
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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write!(f, "{}", self.bits())
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}
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}
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impl W {}
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#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv3::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv3::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct Clkdiv3Spec;
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impl crate::RegisterSpec for Clkdiv3Spec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`clkdiv3::R`](R) reader structure"]
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impl crate::Readable for Clkdiv3Spec {}
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#[doc = "`write(|w| ..)` method takes [`clkdiv3::W`](W) writer structure"]
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impl crate::Writable for Clkdiv3Spec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CLKDIV3 to value 0"]
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impl crate::Resettable for Clkdiv3Spec {
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const RESET_VALUE: u32 = 0;
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}
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27
va416xx/src/ioconfig/clkdiv4.rs
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27
va416xx/src/ioconfig/clkdiv4.rs
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@ -0,0 +1,27 @@
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#[doc = "Register `CLKDIV4` reader"]
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pub type R = crate::R<Clkdiv4Spec>;
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#[doc = "Register `CLKDIV4` writer"]
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pub type W = crate::W<Clkdiv4Spec>;
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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write!(f, "{}", self.bits())
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}
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}
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impl W {}
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#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv4::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv4::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct Clkdiv4Spec;
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impl crate::RegisterSpec for Clkdiv4Spec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`clkdiv4::R`](R) reader structure"]
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impl crate::Readable for Clkdiv4Spec {}
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#[doc = "`write(|w| ..)` method takes [`clkdiv4::W`](W) writer structure"]
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impl crate::Writable for Clkdiv4Spec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CLKDIV4 to value 0"]
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impl crate::Resettable for Clkdiv4Spec {
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const RESET_VALUE: u32 = 0;
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}
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27
va416xx/src/ioconfig/clkdiv5.rs
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27
va416xx/src/ioconfig/clkdiv5.rs
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@ -0,0 +1,27 @@
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#[doc = "Register `CLKDIV5` reader"]
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pub type R = crate::R<Clkdiv5Spec>;
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#[doc = "Register `CLKDIV5` writer"]
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pub type W = crate::W<Clkdiv5Spec>;
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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write!(f, "{}", self.bits())
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}
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}
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impl W {}
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#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv5::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv5::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct Clkdiv5Spec;
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impl crate::RegisterSpec for Clkdiv5Spec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`clkdiv5::R`](R) reader structure"]
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impl crate::Readable for Clkdiv5Spec {}
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#[doc = "`write(|w| ..)` method takes [`clkdiv5::W`](W) writer structure"]
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impl crate::Writable for Clkdiv5Spec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CLKDIV5 to value 0"]
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impl crate::Resettable for Clkdiv5Spec {
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const RESET_VALUE: u32 = 0;
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}
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27
va416xx/src/ioconfig/clkdiv6.rs
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27
va416xx/src/ioconfig/clkdiv6.rs
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@ -0,0 +1,27 @@
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#[doc = "Register `CLKDIV6` reader"]
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pub type R = crate::R<Clkdiv6Spec>;
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#[doc = "Register `CLKDIV6` writer"]
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pub type W = crate::W<Clkdiv6Spec>;
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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write!(f, "{}", self.bits())
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}
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}
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impl W {}
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#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv6::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv6::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct Clkdiv6Spec;
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impl crate::RegisterSpec for Clkdiv6Spec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`clkdiv6::R`](R) reader structure"]
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impl crate::Readable for Clkdiv6Spec {}
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#[doc = "`write(|w| ..)` method takes [`clkdiv6::W`](W) writer structure"]
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impl crate::Writable for Clkdiv6Spec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CLKDIV6 to value 0"]
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impl crate::Resettable for Clkdiv6Spec {
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const RESET_VALUE: u32 = 0;
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}
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27
va416xx/src/ioconfig/clkdiv7.rs
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27
va416xx/src/ioconfig/clkdiv7.rs
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@ -0,0 +1,27 @@
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#[doc = "Register `CLKDIV7` reader"]
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pub type R = crate::R<Clkdiv7Spec>;
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#[doc = "Register `CLKDIV7` writer"]
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pub type W = crate::W<Clkdiv7Spec>;
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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write!(f, "{}", self.bits())
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}
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}
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impl W {}
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#[doc = "Clock divide value. 0 will disable the clock\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`clkdiv7::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`clkdiv7::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct Clkdiv7Spec;
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impl crate::RegisterSpec for Clkdiv7Spec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`clkdiv7::R`](R) reader structure"]
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impl crate::Readable for Clkdiv7Spec {}
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#[doc = "`write(|w| ..)` method takes [`clkdiv7::W`](W) writer structure"]
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impl crate::Writable for Clkdiv7Spec {
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type Safety = crate::Unsafe;
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const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
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}
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#[doc = "`reset()` method sets CLKDIV7 to value 0"]
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impl crate::Resettable for Clkdiv7Spec {
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const RESET_VALUE: u32 = 0;
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}
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18
va416xx/src/ioconfig/perid.rs
Normal file
18
va416xx/src/ioconfig/perid.rs
Normal file
@ -0,0 +1,18 @@
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#[doc = "Register `PERID` reader"]
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pub type R = crate::R<PeridSpec>;
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impl core::fmt::Debug for R {
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fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
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write!(f, "{}", self.bits())
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}
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}
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#[doc = "Peripheral ID Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`perid::R`](R). See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
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pub struct PeridSpec;
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impl crate::RegisterSpec for PeridSpec {
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type Ux = u32;
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}
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#[doc = "`read()` method returns [`perid::R`](R) reader structure"]
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impl crate::Readable for PeridSpec {}
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#[doc = "`reset()` method sets PERID to value 0x0282_07e9"]
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impl crate::Resettable for PeridSpec {
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const RESET_VALUE: u32 = 0x0282_07e9;
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}
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299
va416xx/src/ioconfig/porta.rs
Normal file
299
va416xx/src/ioconfig/porta.rs
Normal file
@ -0,0 +1,299 @@
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#[doc = "Register `PORTA[%s]` reader"]
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pub type R = crate::R<PortaSpec>;
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#[doc = "Register `PORTA[%s]` writer"]
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pub type W = crate::W<PortaSpec>;
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#[doc = "Input Filter Selectoin\n\nValue on reset: 0"]
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#[derive(Clone, Copy, Debug, PartialEq, Eq)]
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#[repr(u8)]
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pub enum Flttype {
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#[doc = "0: Synchronize to system clock"]
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Sync = 0,
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#[doc = "1: Direct input, no synchronization"]
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Direct = 1,
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#[doc = "2: Require 2 samples to have the same value"]
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Filter1 = 2,
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#[doc = "3: Require 3 samples to have the same value"]
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Filter2 = 3,
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#[doc = "4: Require 4 samples to have the same value"]
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Filter3 = 4,
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#[doc = "5: Require 5 samples to have the same value"]
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Filter4 = 5,
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}
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impl From<Flttype> for u8 {
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#[inline(always)]
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fn from(variant: Flttype) -> Self {
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variant as _
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}
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}
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impl crate::FieldSpec for Flttype {
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type Ux = u8;
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}
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impl crate::IsEnum for Flttype {}
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#[doc = "Field `FLTTYPE` reader - Input Filter Selectoin"]
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pub type FlttypeR = crate::FieldReader<Flttype>;
|
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impl FlttypeR {
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#[doc = "Get enumerated values variant"]
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#[inline(always)]
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pub const fn variant(&self) -> Option<Flttype> {
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match self.bits {
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0 => Some(Flttype::Sync),
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1 => Some(Flttype::Direct),
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2 => Some(Flttype::Filter1),
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3 => Some(Flttype::Filter2),
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4 => Some(Flttype::Filter3),
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5 => Some(Flttype::Filter4),
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_ => None,
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}
|
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}
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#[doc = "Synchronize to system clock"]
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#[inline(always)]
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pub fn is_sync(&self) -> bool {
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*self == Flttype::Sync
|
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}
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#[doc = "Direct input, no synchronization"]
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#[inline(always)]
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pub fn is_direct(&self) -> bool {
|
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*self == Flttype::Direct
|
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}
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#[doc = "Require 2 samples to have the same value"]
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#[inline(always)]
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pub fn is_filter1(&self) -> bool {
|
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*self == Flttype::Filter1
|
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}
|
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#[doc = "Require 3 samples to have the same value"]
|
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#[inline(always)]
|
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pub fn is_filter2(&self) -> bool {
|
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*self == Flttype::Filter2
|
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}
|
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#[doc = "Require 4 samples to have the same value"]
|
||||
#[inline(always)]
|
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pub fn is_filter3(&self) -> bool {
|
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*self == Flttype::Filter3
|
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}
|
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#[doc = "Require 5 samples to have the same value"]
|
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#[inline(always)]
|
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pub fn is_filter4(&self) -> bool {
|
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*self == Flttype::Filter4
|
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}
|
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}
|
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#[doc = "Field `FLTTYPE` writer - Input Filter Selectoin"]
|
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pub type FlttypeW<'a, REG> = crate::FieldWriter<'a, REG, 3, Flttype>;
|
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impl<'a, REG> FlttypeW<'a, REG>
|
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where
|
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REG: crate::Writable + crate::RegisterSpec,
|
||||
REG::Ux: From<u8>,
|
||||
{
|
||||
#[doc = "Synchronize to system clock"]
|
||||
#[inline(always)]
|
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pub fn sync(self) -> &'a mut crate::W<REG> {
|
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self.variant(Flttype::Sync)
|
||||
}
|
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#[doc = "Direct input, no synchronization"]
|
||||
#[inline(always)]
|
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pub fn direct(self) -> &'a mut crate::W<REG> {
|
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self.variant(Flttype::Direct)
|
||||
}
|
||||
#[doc = "Require 2 samples to have the same value"]
|
||||
#[inline(always)]
|
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pub fn filter1(self) -> &'a mut crate::W<REG> {
|
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self.variant(Flttype::Filter1)
|
||||
}
|
||||
#[doc = "Require 3 samples to have the same value"]
|
||||
#[inline(always)]
|
||||
pub fn filter2(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(Flttype::Filter2)
|
||||
}
|
||||
#[doc = "Require 4 samples to have the same value"]
|
||||
#[inline(always)]
|
||||
pub fn filter3(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(Flttype::Filter3)
|
||||
}
|
||||
#[doc = "Require 5 samples to have the same value"]
|
||||
#[inline(always)]
|
||||
pub fn filter4(self) -> &'a mut crate::W<REG> {
|
||||
self.variant(Flttype::Filter4)
|
||||
}
|
||||
}
|
||||
#[doc = "Field `FLTCLK` reader - Input Filter Clock Selection"]
|
||||
pub type FltclkR = crate::FieldReader;
|
||||
#[doc = "Field `FLTCLK` writer - Input Filter Clock Selection"]
|
||||
pub type FltclkW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `INVINP` reader - Input Invert Selection"]
|
||||
pub type InvinpR = crate::BitReader;
|
||||
#[doc = "Field `INVINP` writer - Input Invert Selection"]
|
||||
pub type InvinpW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `IEWO` reader - Input Enable While Output enabled"]
|
||||
pub type IewoR = crate::BitReader;
|
||||
#[doc = "Field `IEWO` writer - Input Enable While Output enabled"]
|
||||
pub type IewoW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `OPENDRN` reader - Output Open Drain Mode"]
|
||||
pub type OpendrnR = crate::BitReader;
|
||||
#[doc = "Field `OPENDRN` writer - Output Open Drain Mode"]
|
||||
pub type OpendrnW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `INVOUT` reader - Output Invert Selection"]
|
||||
pub type InvoutR = crate::BitReader;
|
||||
#[doc = "Field `INVOUT` writer - Output Invert Selection"]
|
||||
pub type InvoutW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `PLEVEL` reader - Internal Pull up/down level"]
|
||||
pub type PlevelR = crate::BitReader;
|
||||
#[doc = "Field `PLEVEL` writer - Internal Pull up/down level"]
|
||||
pub type PlevelW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `PEN` reader - Enable Internal Pull up/down"]
|
||||
pub type PenR = crate::BitReader;
|
||||
#[doc = "Field `PEN` writer - Enable Internal Pull up/down"]
|
||||
pub type PenW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `PWOA` reader - Enable Pull when output active"]
|
||||
pub type PwoaR = crate::BitReader;
|
||||
#[doc = "Field `PWOA` writer - Enable Pull when output active"]
|
||||
pub type PwoaW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
#[doc = "Field `FUNSEL` reader - Pin Function Selection"]
|
||||
pub type FunselR = crate::FieldReader;
|
||||
#[doc = "Field `FUNSEL` writer - Pin Function Selection"]
|
||||
pub type FunselW<'a, REG> = crate::FieldWriter<'a, REG, 3>;
|
||||
#[doc = "Field `IODIS` reader - IO Pin Disable"]
|
||||
pub type IodisR = crate::BitReader;
|
||||
#[doc = "Field `IODIS` writer - IO Pin Disable"]
|
||||
pub type IodisW<'a, REG> = crate::BitWriter<'a, REG>;
|
||||
impl R {
|
||||
#[doc = "Bits 0:2 - Input Filter Selectoin"]
|
||||
#[inline(always)]
|
||||
pub fn flttype(&self) -> FlttypeR {
|
||||
FlttypeR::new((self.bits & 7) as u8)
|
||||
}
|
||||
#[doc = "Bits 3:5 - Input Filter Clock Selection"]
|
||||
#[inline(always)]
|
||||
pub fn fltclk(&self) -> FltclkR {
|
||||
FltclkR::new(((self.bits >> 3) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bit 6 - Input Invert Selection"]
|
||||
#[inline(always)]
|
||||
pub fn invinp(&self) -> InvinpR {
|
||||
InvinpR::new(((self.bits >> 6) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 7 - Input Enable While Output enabled"]
|
||||
#[inline(always)]
|
||||
pub fn iewo(&self) -> IewoR {
|
||||
IewoR::new(((self.bits >> 7) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 8 - Output Open Drain Mode"]
|
||||
#[inline(always)]
|
||||
pub fn opendrn(&self) -> OpendrnR {
|
||||
OpendrnR::new(((self.bits >> 8) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 9 - Output Invert Selection"]
|
||||
#[inline(always)]
|
||||
pub fn invout(&self) -> InvoutR {
|
||||
InvoutR::new(((self.bits >> 9) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 10 - Internal Pull up/down level"]
|
||||
#[inline(always)]
|
||||
pub fn plevel(&self) -> PlevelR {
|
||||
PlevelR::new(((self.bits >> 10) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 11 - Enable Internal Pull up/down"]
|
||||
#[inline(always)]
|
||||
pub fn pen(&self) -> PenR {
|
||||
PenR::new(((self.bits >> 11) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bit 12 - Enable Pull when output active"]
|
||||
#[inline(always)]
|
||||
pub fn pwoa(&self) -> PwoaR {
|
||||
PwoaR::new(((self.bits >> 12) & 1) != 0)
|
||||
}
|
||||
#[doc = "Bits 13:15 - Pin Function Selection"]
|
||||
#[inline(always)]
|
||||
pub fn funsel(&self) -> FunselR {
|
||||
FunselR::new(((self.bits >> 13) & 7) as u8)
|
||||
}
|
||||
#[doc = "Bit 16 - IO Pin Disable"]
|
||||
#[inline(always)]
|
||||
pub fn iodis(&self) -> IodisR {
|
||||
IodisR::new(((self.bits >> 16) & 1) != 0)
|
||||
}
|
||||
}
|
||||
impl W {
|
||||
#[doc = "Bits 0:2 - Input Filter Selectoin"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn flttype(&mut self) -> FlttypeW<PortaSpec> {
|
||||
FlttypeW::new(self, 0)
|
||||
}
|
||||
#[doc = "Bits 3:5 - Input Filter Clock Selection"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn fltclk(&mut self) -> FltclkW<PortaSpec> {
|
||||
FltclkW::new(self, 3)
|
||||
}
|
||||
#[doc = "Bit 6 - Input Invert Selection"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn invinp(&mut self) -> InvinpW<PortaSpec> {
|
||||
InvinpW::new(self, 6)
|
||||
}
|
||||
#[doc = "Bit 7 - Input Enable While Output enabled"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn iewo(&mut self) -> IewoW<PortaSpec> {
|
||||
IewoW::new(self, 7)
|
||||
}
|
||||
#[doc = "Bit 8 - Output Open Drain Mode"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn opendrn(&mut self) -> OpendrnW<PortaSpec> {
|
||||
OpendrnW::new(self, 8)
|
||||
}
|
||||
#[doc = "Bit 9 - Output Invert Selection"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn invout(&mut self) -> InvoutW<PortaSpec> {
|
||||
InvoutW::new(self, 9)
|
||||
}
|
||||
#[doc = "Bit 10 - Internal Pull up/down level"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn plevel(&mut self) -> PlevelW<PortaSpec> {
|
||||
PlevelW::new(self, 10)
|
||||
}
|
||||
#[doc = "Bit 11 - Enable Internal Pull up/down"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn pen(&mut self) -> PenW<PortaSpec> {
|
||||
PenW::new(self, 11)
|
||||
}
|
||||
#[doc = "Bit 12 - Enable Pull when output active"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn pwoa(&mut self) -> PwoaW<PortaSpec> {
|
||||
PwoaW::new(self, 12)
|
||||
}
|
||||
#[doc = "Bits 13:15 - Pin Function Selection"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn funsel(&mut self) -> FunselW<PortaSpec> {
|
||||
FunselW::new(self, 13)
|
||||
}
|
||||
#[doc = "Bit 16 - IO Pin Disable"]
|
||||
#[inline(always)]
|
||||
#[must_use]
|
||||
pub fn iodis(&mut self) -> IodisW<PortaSpec> {
|
||||
IodisW::new(self, 16)
|
||||
}
|
||||
}
|
||||
#[doc = "PORTA Pin Configuration Register\n\nYou can [`read`](crate::generic::Reg::read) this register and get [`porta::R`](R). You can [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`write_with_zero`](crate::generic::Reg::write_with_zero) this register using [`porta::W`](W). You can also [`modify`](crate::generic::Reg::modify) this register. See [API](https://docs.rs/svd2rust/#read--modify--write-api)."]
|
||||
pub struct PortaSpec;
|
||||
impl crate::RegisterSpec for PortaSpec {
|
||||
type Ux = u32;
|
||||
}
|
||||
#[doc = "`read()` method returns [`porta::R`](R) reader structure"]
|
||||
impl crate::Readable for PortaSpec {}
|
||||
#[doc = "`write(|w| ..)` method takes [`porta::W`](W) writer structure"]
|
||||
impl crate::Writable for PortaSpec {
|
||||
type Safety = crate::Unsafe;
|
||||
const ZERO_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
const ONE_TO_MODIFY_FIELDS_BITMAP: u32 = 0;
|
||||
}
|
||||
#[doc = "`reset()` method sets PORTA[%s]
|
||||
to value 0"]
|
||||
impl crate::Resettable for PortaSpec {
|
||||
const RESET_VALUE: u32 = 0;
|
||||
}
|
||||
Reference in New Issue
Block a user